diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/atod-ep93xx.c linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/atod-ep93xx.c --- linux-2.6.25/arch/arm/mach-ep93xx/atod-ep93xx.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/atod-ep93xx.c 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,88 @@ +/* + * arch/arm/mach-ep93xx/atod-ep93xx.c + * EMAC.Inc ep93xx low level AtoD interactions + * + * Copyright (C) 2007 EMAC.Inc + */ + +#include +#include +#include +#include "atod-ep93xx.h" + +int ep93xx_atod_init(void){ + __u32 devicecfg = ioread32((void *)EP93XX_SYSCON_DEVICE_CONFIG); + EP93XX_SYSUNLOCK(); + //iowrite32(EP93XX_SYSCON_ADCCLKDIV_ADCEN|EP93XX_SYSCON_ADCCLKDIV_ADIV,(void *)EP93XX_SYSCON_ADCCLKDIV);//enable AtoD clocks + iowrite32(EP93XX_SYSCON_ADCCLKDIV_ADCEN,(void *)EP93XX_SYSCON_ADCCLKDIV);//enable AtoD clocks + printk("atod: EP93XX_SYSCON_ADCCLKDIV: %x\n",ioread32((void *)EP93XX_SYSCON_ADCCLKDIV)); + devicecfg|=EP93XX_SYSCON_DEVICE_CONFIG_ADCEN;//disable touchscreen (TIN on the ep9315) + devicecfg&=~EP93XX_SYSCON_DEVICE_CONFIG_ADCPD;//turn on the AtoD clock + EP93XX_DEVCFG_WRITE(devicecfg);//enable the AtoD + iowrite32(0,(void *)EP93XX_ADCSETUP1);//clear out any TS settings. + printk("atod: device config set to %x\n",ioread32((void *)EP93XX_SYSCON_DEVICE_CONFIG)); + return 0; +} + +int ep93xx_atod_switch(int channel){ + const int decoder[5] = {0x608,0x680,0x640,0x620,0x610}; + int code = decoder[channel]; + iowrite32(0xAA,(void *)EP93XX_ADCSWLOCK);//this may have to be inlined. + iowrite32(code,(void *)EP93XX_ADCSWITCH); + return 0; +} + +/** + * read result, reads a 16 bit signed value, + * some number massaging is done in accordance with the discussion posted on + * http://arm.cirrus.com/forum/viewtopic.php?p=8563#8563 + * + * if a new conversion is not yet ready -1 is returned. + */ + +int ep93xx_atod_read_current(void){ + int reading = ioread32((void *)EP93XX_ADCRESULT); + u16 data = reading;//implicity cut off the top. + if(!(reading&EP93XX_ADCRESULT_SDR)){ + //printk("no new data, read %x\n",reading); + return -1;//no new reading available yet. + } + //Check limits and adjust bias (see page 34 in EP9302 datasheet (DS653PP3)) + if ((data>25000)&&(data<=32767)) data=25000; //Enforce +25000 count limit + if ((data>=32678)&&(data<40536)) data=40536;//Enforce -25000 count limit + data-=40536; //Adjust bias value + return (data); +} + +static gpio_data atod_data_read(struct gpio_s *gpio){ + int data; + do {data = ep93xx_atod_read_current();}while(data==-1);//get first available data + return data; +} + +static gpio_data atod_index_read(struct gpio_s *gpio){ + return gpio->index; +} + +static int atod_index_write(struct gpio_s *gpio,gpio_data index){ + if(index>4)return -1; + if(index<0)return -1; + gpio->index = index; + ep93xx_atod_switch(index); + ioread32((void *)EP93XX_ADCRESULT);//begin conversion cycle on the new channel + return 0; +} + +struct class_device *ep93xx_atod_class_create(const char *name){ + gpio_t *gpio = kmalloc(sizeof(gpio_t),GFP_KERNEL); + memset(gpio,0,sizeof(gpio_t)); + gpio->name = name; + gpio->subclass = GPIO_SUBCLASS; + gpio->data_write = gpio_empty_write; + gpio->data_read = atod_data_read; + gpio->index_write = atod_index_write; + gpio->index_read = atod_index_read; + atod_index_write(gpio,0); + printk("registering indexed atod device: %s\n",name); + return gpio_register_class_device(gpio); +} diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/atod-ep93xx.h linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/atod-ep93xx.h --- linux-2.6.25/arch/arm/mach-ep93xx/atod-ep93xx.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/atod-ep93xx.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,12 @@ +#ifndef ATODEP93XX_H_ +#define ATODEP93XX_H_ + +#include +#include + +int ep93xx_atod_init(void); +int ep93xx_atod_switch(int channel); +int ep93xx_atod_read_current(void); +struct class_device *ep93xx_atod_class_create(const char *name); + +#endif /*ATODEP93XX_H_*/ diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/core.c linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/core.c --- linux-2.6.25/arch/arm/mach-ep93xx/core.c 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/core.c 2008-08-18 14:05:42.000000000 -0500 @@ -215,6 +215,12 @@ local_irq_restore(flags); } +void gpio_line_config(int line, int direction) +{ + ep93xx_gpio_set_direction(line,direction); +} +EXPORT_SYMBOL(gpio_line_config); + int gpio_direction_input(unsigned gpio) { if (gpio > EP93XX_GPIO_LINE_MAX) @@ -267,6 +273,11 @@ } EXPORT_SYMBOL(gpio_set_value); +void gpio_line_set(int line, int value) +{ + gpio_set_value(line, value); +} +EXPORT_SYMBOL(gpio_line_set); /************************************************************************* * EP93xx IRQ handling diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/dma_ep93xx.c linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/dma_ep93xx.c --- linux-2.6.25/arch/arm/mach-ep93xx/dma_ep93xx.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/dma_ep93xx.c 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,2933 @@ +/****************************************************************************** + * arch/arm/mach-ep9312/dma_ep93xx.c + * + * Support functions for the ep93xx internal DMA channels. + * (see also Documentation/arm/ep93xx/dma.txt) + * + * Copyright (C) 2003 Cirrus Logic + * + * A large portion of this file is based on the dma api implemented by + * Nicolas Pitre, dma-sa1100.c, copyrighted 2000. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + ****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include "dma_ep93xx.h" + +/***************************************************************************** + * + * Debugging macros + * + ****************************************************************************/ +#undef DEBUG +//#define DEBUG 1 +#ifdef DEBUG +#define DPRINTK( fmt, arg... ) printk( fmt, ##arg ) +#else +#define DPRINTK( fmt, arg... ) +#endif + +/***************************************************************************** + * + * static global variables + * + ****************************************************************************/ +ep93xx_dma_t dma_chan[MAX_EP93XX_DMA_CHANNELS]; + +/* + * lock used to protect the list of dma channels while searching for a free + * channel during dma_request. + */ +//static spinlock_t dma_list_lock; +static spinlock_t dma_list_lock = SPIN_LOCK_UNLOCKED; + +/***************************************************************************** + * + * Internal DMA processing functions. + * + ****************************************************************************/ +/***************************************************************************** + * + * get_dma_channel_from_handle() + * + * If Handle is valid, returns the DMA channel # (0 to 9 for channels 1-10) + * If Handle is not valid, returns -1. + * + ****************************************************************************/ +static int +dma_get_channel_from_handle(int handle) +{ + int channel; + + /* + * Get the DMA channel # from the handle. + */ + channel = ((int)handle & DMA_HANDLE_SPECIFIER_MASK) >> 28; + + /* + * See if this is a valid handle. + */ + if (dma_chan[channel].last_valid_handle != (int)handle) { + DPRINTK("DMA ERROR - invalid handle 0x%x \n", handle); + return(-1); + } + + /* + * See if this instance is still open + */ + if (!dma_chan[channel].ref_count ) + return(-1); + + return(channel); +} + +static void dma_m2m_transfer_done(ep93xx_dma_t *dma) +{ + unsigned int uiCONTROL; + unsigned int M2M_reg_base = dma->reg_base; + unsigned int read_back; + + DPRINTK("1 "); + + outl( 0, M2M_reg_base+M2M_OFFSET_INTERRUPT ); + + if (dma->total_buffers) { + /* + * The current_buffer has already been tranfered, so add the + * byte count to the total_bytes field. + */ + dma->total_bytes = dma->total_bytes + + dma->buffer_queue[dma->current_buffer].size; + + /* + * Mark the current_buffer as used. + */ + dma->buffer_queue[dma->current_buffer].used = TRUE; + + /* + * Increment the used buffer counter + */ + dma->used_buffers++; + + DPRINTK("#%d", dma->current_buffer); + + /* + * Increment the current_buffer + */ + dma->current_buffer = (dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS; + + /* + * check if there's a new buffer to transfer. + */ + if (dma->new_buffers && dma->xfer_enable) { + /* + * We have a new buffer to transfer so program in the + * buffer values. Since a STALL interrupt was + * triggered, we program the buffer descriptor 0 + * + * Set the SAR_BASE/DAR_BASE/BCR registers with values + * from the next buffer in the queue. + */ + outl( dma->buffer_queue[dma->current_buffer].source, + M2M_reg_base + M2M_OFFSET_SAR_BASE0 ); + + outl( dma->buffer_queue[dma->current_buffer].dest, + M2M_reg_base + M2M_OFFSET_DAR_BASE0 ); + + outl( dma->buffer_queue[dma->current_buffer].size, + M2M_reg_base + M2M_OFFSET_BCR0 ); + + DPRINTK("SAR_BASE0 - 0x%x\n", dma->buffer_queue[dma->current_buffer].source); + DPRINTK("DAR_BASE0 - 0x%x\n", dma->buffer_queue[dma->current_buffer].dest); + DPRINTK("BCR0 - 0x%x\n", dma->buffer_queue[dma->current_buffer].size); + + /* + * Decrement the new buffer counter + */ + dma->new_buffers--; + + /* + * If there's a second new buffer, we program the + * second buffer descriptor. + */ + if (dma->new_buffers) { + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].source, + M2M_reg_base+M2M_OFFSET_SAR_BASE1 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].dest, + M2M_reg_base+M2M_OFFSET_DAR_BASE1 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].size, + M2M_reg_base+M2M_OFFSET_BCR1 ); + + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2M_NFBINTEN; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + dma->new_buffers--; + } + } else { + DPRINTK("2 \n"); + /* + * There's a chance we setup both buffer descriptors, + * but didn't service the NFB quickly enough, causing + * the channel to transfer both buffers, then enter the + * stall state. So, we need to be able to process the + * second buffer. + */ + if ((dma->used_buffers + dma->new_buffers) < dma->total_buffers) + { + DPRINTK("3 "); + + /* + * The current_buffer has already been + * tranferred, so add the byte count to the + * total_bytes field. + */ + dma->total_bytes = dma->total_bytes + + dma->buffer_queue[dma->current_buffer].size; + + /* + * Mark the current_buffer as used. + */ + dma->buffer_queue[dma->current_buffer].used = TRUE; + + /* + * Increment the used buffer counter + */ + dma->used_buffers++; + + DPRINTK("#%d", dma->current_buffer); + + /* + * Increment the current buffer pointer. + */ + dma->current_buffer = (dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS; + + } + + /* + * No new buffers to transfer, so disable the channel. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_ENABLE; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * Indicate that this channel is in the pause by + * starvation state by setting the pause bit to true. + */ + dma->pause = TRUE; + } + } else { + /* + * No buffers to transfer, or old buffers to mark as used, + * so disable the channel + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_ENABLE; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * Must read the control register back after a write. + */ + read_back = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + + /* + * Indicate that this channel is in the pause by + * starvation state by setting the pause bit to true. + */ + dma->pause = TRUE; + } +} + +static void dma_m2m_next_frame_buffer(ep93xx_dma_t *dma) +{ + int loop; + unsigned int uiCONTROL; + unsigned int M2M_reg_base = dma->reg_base; + + DPRINTK("5 "); + + if (dma->total_buffers) { + DPRINTK("6 "); + /* + * The iCurrentBuffer has already been transfered. so add the + * byte count from the current buffer to the total byte count. + */ + dma->total_bytes = dma->total_bytes + + dma->buffer_queue[dma->current_buffer].size; + + /* + * Mark the Current Buffer as used. + */ + dma->buffer_queue[dma->current_buffer].used = TRUE; + + /* + * Increment the used buffer counter + */ + dma->used_buffers++; + + DPRINTK("#%d", dma->current_buffer); + + if ((dma->buffer_queue[ + (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS].last) || + (dma->new_buffers == 0) || (dma->xfer_enable == FALSE)) { + DPRINTK("7 "); + + /* + * This is the last Buffer in this transaction, so + * disable the NFB interrupt. We shouldn't get an NFB + * int when the FSM moves to the ON state where it + * would typically get the NFB int indicating a new + * buffer can be programmed. Instead, once in the ON + * state, the DMA will just proceed to complete the + * transfer of the current buffer, move the FSB + * directly to the STALL state where a STALL interrupt + * will be generated. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_NFBINTEN ; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * The current buffer has been transferred, so + * increment the current buffer counter to reflect + * this. + */ + dma->current_buffer = (dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS; + + DPRINTK("End of NFB handling. \n"); + DPRINTK("CONTROL - 0x%x \n", + inl(M2M_reg_base+M2M_OFFSET_CONTROL) ); + DPRINTK("STATUS - 0x%x \n", + inl(M2M_reg_base+M2M_OFFSET_STATUS) ); + DPRINTK("SAR_BASE0 - 0x%x \n", + inl(M2M_reg_base+M2M_OFFSET_SAR_BASE0) ); + DPRINTK("SAR_CUR0 - 0x%x \n", + inl(M2M_reg_base+M2M_OFFSET_SAR_CURRENT0) ); + DPRINTK("DAR_BASE0 - 0x%x \n", + inl(M2M_reg_base+M2M_OFFSET_DAR_BASE0) ); + DPRINTK("DAR_CUR0 - 0x%x \n", + inl(M2M_reg_base+M2M_OFFSET_DAR_CURRENT0) ); + + DPRINTK("Buffer buf_id source size last used \n"); + for (loop = 0; loop < 32; loop ++) + DPRINTK("%d 0x%x 0x%x 0x%x %d %d \n", + loop, dma->buffer_queue[loop].buf_id, + dma->buffer_queue[loop].source, + dma->buffer_queue[loop].size, + dma->buffer_queue[loop].last, + dma->buffer_queue[loop].used); + DPRINTK("pause 0x%x 0x%x 0x%x %d %d \n", + dma->pause_buf.buf_id, dma->pause_buf.source, + dma->pause_buf.size, dma->pause_buf.last, + dma->pause_buf.used); + + DPRINTK("Pause - %d \n", dma->pause); + DPRINTK("xfer_enable - %d \n", dma->xfer_enable); + DPRINTK("total bytes - 0x%x \n", dma->total_bytes); + DPRINTK("total buffer - %d \n", dma->total_buffers); + DPRINTK("new buffers - %d \n", dma->new_buffers); + DPRINTK("current buffer - %d \n", dma->current_buffer); + DPRINTK("last buffer - %d \n", dma->last_buffer); + DPRINTK("used buffers - %d \n", dma->used_buffers); + DPRINTK("callback addr - 0x%p \n", dma->callback); + + } else if (dma->new_buffers) { + DPRINTK("8 "); + /* + * We have a new buffer, so increment the current + * buffer to point to the next buffer, which is already + * programmed into the DMA. Next time around, it'll be + * pointing to the current buffer. + */ + dma->current_buffer = (dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS; + + /* + * We know we have a new buffer to program as the next + * buffer, so check which set of SAR_BASE/DAR_BASE/BCR + * registers to program. + */ + if ( inl(M2M_reg_base+M2M_OFFSET_STATUS) & STATUS_M2M_NB ) { + /* + * Set the SAR_BASE1/DAR_BASE1/BCR1 registers + * with values from the next buffer in the + * queue. + */ + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].source, + M2M_reg_base+M2M_OFFSET_SAR_BASE1 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].dest, + M2M_reg_base+M2M_OFFSET_DAR_BASE1 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].size, + M2M_reg_base+M2M_OFFSET_BCR1 ); + } else { + /* + * Set the SAR_BASE0/DAR_BASE0/BCR0 registers + * with values from the next buffer in the + * queue. + */ + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].source, + M2M_reg_base+M2M_OFFSET_SAR_BASE0 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].dest, + M2M_reg_base+M2M_OFFSET_DAR_BASE0 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].size, + M2M_reg_base+M2M_OFFSET_BCR0 ); + } + + /* + * Decrement the new buffers counter + */ + dma->new_buffers--; + } + } else { + /* + * Total number of buffers is 0 - really we should never get + * here, but just in case. + */ + DPRINTK("9 \n"); + + /* + * No new buffers to transfer, so Disable the channel + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_ENABLE; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * Indicate that the channel is paused by starvation. + */ + dma->pause = 1; + } +} + +/***************************************************************************** + * + * dma_m2m_irq_handler + * + ****************************************************************************/ +static irqreturn_t +dma_m2m_irq_handler(int irq, void *dev_id) +{ + ep93xx_dma_t *dma = (ep93xx_dma_t *)dev_id; + unsigned int M2M_reg_base = dma->reg_base; + ep93xx_dma_dev_t dma_int = UNDEF_INT; + int status; + +// printk("+m2m irq=%d\n", irq); + + /* + * Determine what kind of dma interrupt this is. + */ + status = inl(M2M_reg_base + M2M_OFFSET_INTERRUPT); + if ( status & INTERRUPT_M2M_DONEINT ) + dma_int = DONE; // we're done with a requested dma + else if ( status & INTERRUPT_M2M_NFBINT ) + dma_int = NFB; // we're done with one dma buffer + + DPRINTK("IRQ: b=%#x st=%#x\n", (int)dma->current_buffer, dma_int); + + switch (dma_int) { + /* + * Next Frame Buffer Interrupt. If there's a new buffer program it + * Check if this is the last buffer in the transfer, + * and if it is, disable the NFB int to prevent being + * interrupted for another buffer when we know there won't be + * another. + */ + case NFB: + dma_m2m_next_frame_buffer(dma); + break; + /* + * Done interrupt generated, indicating that the transfer is complete. + */ + case DONE: + dma_m2m_transfer_done(dma); + break; + + default: + break; + } + + if ((dma_int != UNDEF_INT) && dma->callback) + dma->callback(dma_int, dma->device, dma->user_data); + + return IRQ_HANDLED; +} + +/***************************************************************************** + * + * dma_m2p_irq_handler + * + * + * + ****************************************************************************/ +static irqreturn_t +dma_m2p_irq_handler(int irq, void *dev_id) +{ + ep93xx_dma_t *dma = (ep93xx_dma_t *) dev_id; + unsigned int M2P_reg_base = dma->reg_base; + unsigned int read_back; + ep93xx_dma_dev_t dma_int = UNDEF_INT; + unsigned int loop, uiCONTROL, uiINTERRUPT; + + /* + * Determine what kind of dma interrupt this is. + */ + if ( inl(M2P_reg_base+M2P_OFFSET_INTERRUPT) & INTERRUPT_M2P_STALLINT ) + dma_int = STALL; + else if ( inl(M2P_reg_base+M2P_OFFSET_INTERRUPT) & INTERRUPT_M2P_NFBINT ) + dma_int = NFB; + else if ( inl(M2P_reg_base+M2P_OFFSET_INTERRUPT) & INTERRUPT_M2P_CHERRORINT ) + dma_int = CHERROR; + + /* + * Stall Interrupt: The Channel is stalled, meaning nothing is + * programmed to transfer right now. So, we're back to the + * beginnning. If there's a buffer to transfer, program it into + * max and base 0 registers. + */ + if (dma_int == STALL) { + DPRINTK("1 "); + + if (dma->total_buffers) { + /* + * The current_buffer has already been tranfered, so + * add the byte count to the total_bytes field. + */ + dma->total_bytes = dma->total_bytes + + dma->buffer_queue[dma->current_buffer].size; + + /* + * Mark the current_buffer as used. + */ + dma->buffer_queue[dma->current_buffer].used = TRUE; + + /* + * Increment the used buffer counter + */ + dma->used_buffers++; + + DPRINTK("#%d", dma->current_buffer); + + /* + * Increment the current_buffer + */ + dma->current_buffer = (dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS; + + /* + * check if there's a new buffer to transfer. + */ + if (dma->new_buffers && dma->xfer_enable) { + /* + * We have a new buffer to transfer so program + * in the buffer values. Since a STALL + * interrupt was triggered, we program the + * base0 and maxcnt0 + * + * Set the MAXCNT0 register with the buffer + * size + */ + outl( dma->buffer_queue[dma->current_buffer].size, + M2P_reg_base+M2P_OFFSET_MAXCNT0 ); + + /* + * Set the BASE0 register with the buffer base + * address + */ + outl( dma->buffer_queue[dma->current_buffer].source, + M2P_reg_base+M2P_OFFSET_BASE0 ); + + /* + * Decrement the new buffer counter + */ + dma->new_buffers--; + + if (dma->new_buffers) { + DPRINTK("A "); + /* + * Set the MAXCNT1 register with the + * buffer size + */ + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].size, + M2P_reg_base+M2P_OFFSET_MAXCNT1 ); + + /* + * Set the BASE1 register with the + * buffer base address + */ + outl( dma->buffer_queue[dma->current_buffer + 1 % + MAX_EP93XX_DMA_BUFFERS].source, + M2P_reg_base+M2P_OFFSET_BASE1 ); + + /* + * Decrement the new buffer counter + */ + dma->new_buffers--; + + /* + * Enable the NFB Interrupt. + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2P_NFBINTEN; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + } + } else { + /* + * No new buffers. + */ + DPRINTK("2 \n"); + + /* + * There's a chance we setup both buffer descriptors, but + * didn't service the NFB quickly enough, causing the channel + * to transfer both buffers, then enter the stall state. + * So, we need to be able to process the second buffer. + */ + if ((dma->used_buffers + dma->new_buffers) < dma->total_buffers) { + DPRINTK("3 "); + + /* + * The current_buffer has already been tranfered, so add the + * byte count to the total_bytes field. + */ + dma->total_bytes = dma->total_bytes + + dma->buffer_queue[dma->current_buffer].size; + + /* + * Mark the current_buffer as used. + */ + dma->buffer_queue[dma->current_buffer].used = TRUE; + + /* + * Increment the used buffer counter + */ + dma->used_buffers++; + + DPRINTK("#%d", dma->current_buffer); + + /* + * Increment the current buffer pointer. + */ + dma->current_buffer = (dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS; + + } + + /* + * No new buffers to transfer, so disable the channel. + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2P_ENABLE; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + /* + * Indicate that this channel is in the pause by starvation + * state by setting the pause bit to true. + */ + dma->pause = TRUE; + + DPRINTK("STATUS - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_STATUS) ); + DPRINTK("CONTROL - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CONTROL) ); + DPRINTK("REMAIN - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_REMAIN) ); + DPRINTK("PPALLOC - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_PPALLOC) ); + DPRINTK("BASE0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE0) ); + DPRINTK("MAXCNT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT0) ); + DPRINTK("CURRENT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT0) ); + DPRINTK("BASE1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE1) ); + DPRINTK("MAXCNT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT1) ); + DPRINTK("CURRENT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT1) ); + + DPRINTK("Buffer buf_id source size last used \n"); + for (loop = 0; loop < 32; loop ++) + DPRINTK("%d 0x%x 0x%x 0x%x %d %d \n", + loop, dma->buffer_queue[loop].buf_id, dma->buffer_queue[loop].source, + dma->buffer_queue[loop].size, + dma->buffer_queue[loop].last, dma->buffer_queue[loop].used); + DPRINTK("pause 0x%x 0x%x 0x%x %d %d \n", + dma->pause_buf.buf_id, dma->pause_buf.source, dma->pause_buf.size, + dma->pause_buf.last, dma->pause_buf.used); + + DPRINTK("Pause - %d \n", dma->pause); + DPRINTK("xfer_enable - %d \n", dma->xfer_enable); + DPRINTK("total bytes - 0x%x \n", dma->total_bytes); + DPRINTK("total buffer - %d \n", dma->total_buffers); + DPRINTK("new buffers - %d \n", dma->new_buffers); + DPRINTK("current buffer - %d \n", dma->current_buffer); + DPRINTK("last buffer - %d \n", dma->last_buffer); + DPRINTK("used buffers - %d \n", dma->used_buffers); + DPRINTK("callback addr - 0x%p \n", dma->callback); + } + } else { + /* + * No buffers to transfer, or old buffers to mark as used, + * so Disable the channel + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2P_ENABLE; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + /* + * Must read the control register back after a write. + */ + read_back = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + + /* + * Indicate that this channel is in the pause by + * starvation state by setting the pause bit to true. + */ + dma->pause = TRUE; + } + } + + /* + * Next Frame Buffer Interrupt. If there's a new buffer program it + * Check if this is the last buffer in the transfer, + * and if it is, disable the NFB int to prevent being + * interrupted for another buffer when we know there won't be + * another. + */ + if (dma_int == NFB) { + DPRINTK("5 "); + + if (dma->total_buffers) { + DPRINTK("6 "); + /* + * The iCurrentBuffer has already been transfered. so add the + * byte count from the current buffer to the total byte count. + */ + dma->total_bytes = dma->total_bytes + + dma->buffer_queue[dma->current_buffer].size; + + /* + * Mark the Current Buffer as used. + */ + dma->buffer_queue[dma->current_buffer].used = TRUE; + + /* + * Increment the used buffer counter + */ + dma->used_buffers++; + + DPRINTK("#%d", dma->current_buffer); + + if ((dma->buffer_queue[ + (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS].last) || + (dma->new_buffers == 0) || (dma->xfer_enable == FALSE)) { + DPRINTK("7 "); + + /* + * This is the last Buffer in this transaction, so disable + * the NFB interrupt. We shouldn't get an NFB int when the + * FSM moves to the ON state where it would typically get the + * NFB int indicating a new buffer can be programmed. + * Instead, once in the ON state, the DMA will just proceed + * to complet the transfer of the current buffer, move the + * FSB directly to the STALL state where a STALL interrupt + * will be generated. + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2P_NFBINTEN; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + /* + * The current buffer has been transferred, so increment + * the current buffer counter to reflect this. + */ + dma->current_buffer = (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS; + + DPRINTK("End of NFB handling. \n"); + DPRINTK("STATUS - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_STATUS) ); + DPRINTK("CONTROL - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CONTROL) ); + DPRINTK("REMAIN - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_REMAIN) ); + DPRINTK("PPALLOC - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_PPALLOC) ); + DPRINTK("BASE0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE0) ); + DPRINTK("MAXCNT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT0) ); + DPRINTK("CURRENT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT0) ); + DPRINTK("BASE1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE1) ); + DPRINTK("MAXCNT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT1) ); + DPRINTK("CURRENT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT1) ); + + DPRINTK("Buffer buf_id source size last used \n"); + for (loop = 0; loop < 32; loop ++) + DPRINTK("%d 0x%x 0x%x 0x%x %d %d \n", + loop, dma->buffer_queue[loop].buf_id, dma->buffer_queue[loop].source, + dma->buffer_queue[loop].size, + dma->buffer_queue[loop].last, dma->buffer_queue[loop].used); + DPRINTK("pause 0x%x 0x%x 0x%x %d %d \n", + dma->pause_buf.buf_id, dma->pause_buf.source, dma->pause_buf.size, + dma->pause_buf.last, dma->pause_buf.used); + + DPRINTK("Pause - %d \n", dma->pause); + DPRINTK("xfer_enable - %d \n", dma->xfer_enable); + DPRINTK("total bytes - 0x%x \n", dma->total_bytes); + DPRINTK("total buffer - %d \n", dma->total_buffers); + DPRINTK("new buffers - %d \n", dma->new_buffers); + DPRINTK("current buffer - %d \n", dma->current_buffer); + DPRINTK("last buffer - %d \n", dma->last_buffer); + DPRINTK("used buffers - %d \n", dma->used_buffers); + DPRINTK("callback addr - 0x%p \n", dma->callback); + + } else if (dma->new_buffers) { + DPRINTK("8 "); + /* + * we have a new buffer, so increment the current buffer to + * point to the next buffer, which is already programmed into + * the DMA. Next time around, it'll be pointing to the + * current buffer. + */ + dma->current_buffer = (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS; + + /* + * we know we have a new buffer to program as the next + * buffer, so check which set of MAXCNT and BASE registers + * to program. + */ + if ( inl(M2P_reg_base+M2P_OFFSET_STATUS) & STATUS_M2P_NEXTBUFFER ) { + /* + * Set the MAXCNT1 register with the buffer size + */ + outl( dma->buffer_queue[ + (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS].size, + M2P_reg_base+M2P_OFFSET_MAXCNT1 ); + + /* + * Set the BASE1 register with the buffer base address + */ + outl( dma->buffer_queue[ + (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS].source, + M2P_reg_base+M2P_OFFSET_BASE1 ); + } else { + /* + * Set the MAXCNT0 register with the buffer size + */ + outl( dma->buffer_queue[ + (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS].size, + M2P_reg_base+M2P_OFFSET_MAXCNT0 ); + + /* + * Set the BASE0 register with the buffer base address + */ + outl( dma->buffer_queue[ + (dma->current_buffer + 1) % MAX_EP93XX_DMA_BUFFERS].source, + M2P_reg_base+M2P_OFFSET_BASE0 ); + } + + /* + * Decrement the new buffers counter + */ + dma->new_buffers--; + } + } else { + /* + * Total number of buffers is 0 - really we should never get here, + * but just in case. + */ + DPRINTK("9 \n"); + + /* + * No new buffers to transfer, so Disable the channel + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2P_ENABLE; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + } + } + + /* + * Channel Error Interrupt, or perhipheral interrupt, specific to the + * memory to/from peripheral channels. + */ + if (dma_int == CHERROR) { + /* + * just clear the interrupt, it's really up to the peripheral + * driver to determine if any further action is necessary. + */ + uiINTERRUPT = inl(M2P_reg_base+M2P_OFFSET_INTERRUPT); + uiINTERRUPT &= ~INTERRUPT_M2P_CHERRORINT; + outl( uiINTERRUPT, M2P_reg_base+M2P_OFFSET_INTERRUPT ); + } + + /* + * Make sure the interrupt was valid, and if it was, then check + * if a callback function was installed for this DMA channel. If a + * callback was installed call it. + */ + if ((dma_int != UNDEF_INT) && dma->callback) + dma->callback(dma_int, dma->device, dma->user_data); + + return IRQ_HANDLED; +} + +/***************************************************************************** + * + * ep9312_dma_open_m2p(int device) + * + * Description: This function will attempt to open a M2P/P2M DMA channel. + * If the open is successful, the channel number is returned, + * otherwise a negative number is returned. + * + * Parameters: + * device: device for which the dma channel is requested. + * + ****************************************************************************/ +static int +dma_open_m2p(int device) +{ + int channel = -1; + unsigned int loop; + unsigned int M2P_reg_base; + unsigned int uiPWRCNT; + /*unsigned long flags;*/ + + DPRINTK("DMA Open M2P with hw dev %d\n", device); + + /* + * Lock the dma channel list. + */ + //spin_lock_irqsave(&dma_list_lock, flags); + spin_lock(&dma_list_lock); + + /* + * Verify that the device requesting DMA isn't already using a DMA channel + */ + if (device >= 10) + loop = 1; // Rx transfer requested + else + loop = 0; // Tx transfer requested + + for (; loop < 10; loop = loop + 2) + /* + * Before checking for a matching device, check that the + * channel is in use, otherwise the device field is + * invalid. + */ + if (dma_chan[loop].ref_count) + if (device == dma_chan[loop].device) { + DPRINTK("DMA Open M2P - Error\n"); + return(-1); + } + + /* + * Get a DMA channel instance for the given hardware device. + * If this is a TX look for even numbered channels, else look for + * odd numbered channels + */ + if (device >= 10) + loop = 1; /* Rx transfer requested */ + else + loop = 0; /* Tx transfer requested */ + + for (; loop < 10; loop = loop + 2) + if (!dma_chan[loop].ref_count) { + /* + * Capture the channel and increment the reference count. + */ + channel = loop; + dma_chan[channel].ref_count++; + break; + } + + /* + * Unlock the dma channel list. + */ + //spin_unlock_irqrestore(&dma_list_lock, flags); + spin_unlock(&dma_list_lock); + /* + * See if we got a valid channel. + */ + if (channel < 0) + return(-1); + + /* + * Point regs to the correct dma channel register base. + */ + M2P_reg_base = dma_chan[channel].reg_base; + + /* + * Turn on the clock for the specified DMA channel + * TODO: need to use the correct register name for the + * power control register. + */ + uiPWRCNT = inl(/*SYSCON_PWRCNT*/EP93XX_SYSCON_CLOCK_CONTROL); + switch (channel) { + case 0: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH0; + break; + + case 1: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH1; + break; + + case 2: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH2; + break; + + case 3: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH3; + break; + + case 4: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH4; + break; + + case 5: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH5; + break; + + case 6: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH6; + break; + + case 7: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH7; + break; + + case 8: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH8; + break; + + case 9: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2PCH9; + break; + + default: + return(-1); + } + outl( uiPWRCNT, /*SYSCON_PWRCNT*/EP93XX_SYSCON_CLOCK_CONTROL ); + + /* + * Clear out the control register before any further setup. + */ + outl( 0, M2P_reg_base+M2P_OFFSET_CONTROL ); + + /* + * Setup the peripheral port value in the DMA channel registers. + */ + if (device < 10) + outl( (unsigned int)device, M2P_reg_base+M2P_OFFSET_PPALLOC ); + else + outl( (unsigned int)(device - 10), M2P_reg_base+M2P_OFFSET_PPALLOC ); + + /* + * Let's hold on to the value of the Hw device for comparison later. + */ + dma_chan[channel].device = device; + + /* + * Success. + */ + return(channel); +} + +/***************************************************************************** + * + * dma_open_m2m(int device) + * + * Description: This function will attempt to open a M2M DMA channel. + * If the open is successful, the channel number is returned, + * otherwise a negative number is returned. + * + * Parameters: + * device: device for which the dma channel is requested. + * + ****************************************************************************/ +static int +dma_open_m2m(int device) +{ + int channel = -1; + unsigned int loop; + unsigned int M2M_reg_base; + unsigned int uiPWRCNT, uiCONTROL; + /*unsigned long flags;*/ + + DPRINTK("DMA Open M2M with hw dev %d\n", device); + + /* + * Lock the dma channel list. + */ + //spin_lock_irqsave(&dma_list_lock, flags); + spin_lock(&dma_list_lock); + + + /* + * Check if this device is already allocated a channel. + * TODO: can one M2M device be allocated multiple channels? + */ + for (loop = DMA_MEMORY; loop < UNDEF; loop++) + /* + * Before checking for a matching device, check that the + * channel is in use, otherwise the device field is + * invalid. + */ + if (dma_chan[loop].ref_count) + if (device == dma_chan[loop].device) { + DPRINTK("Error - dma_open_m2m - already allocated channel\n"); + + /* + * Unlock the dma channel list. + */ + //spin_unlock_irqrestore(&dma_list_lock, flags); + spin_unlock(&dma_list_lock); + /* + * Fail. + */ + return(-1); + } + + /* + * Get a DMA channel instance for the given hardware device. + */ + for (loop = 10; loop < 12; loop++) + if (!dma_chan[loop].ref_count) { + /* + * Capture the channel and increment the reference count. + */ + channel = loop; + dma_chan[channel].ref_count++; + break; + } + + /* + * Unlock the dma channel list. + */ + //spin_unlock(dma_list_lock); + spin_unlock(&dma_list_lock); + //spin_unlock_irqrestore(&dma_list_lock, flags); + + /* + * See if we got a valid channel. + */ + if (channel < 0) + return(-1); + + /* + * Point regs to the correct dma channel register base. + */ + M2M_reg_base = dma_chan[channel].reg_base; + + /* + * Turn on the clock for the specified DMA channel + * TODO: need to use the correct register name for the + * power control register. + */ + uiPWRCNT = inl(/*SYSCON_PWRCNT*/EP93XX_SYSCON_CLOCK_CONTROL); + switch (channel) { + case 10: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2MCH0; + break; + + case 11: + uiPWRCNT |= SYSCON_PWRCNT_DMA_M2MCH1; + break; + + default: + return(-1); + } + outl( uiPWRCNT, /*SYSCON_PWRCNT*/EP93XX_SYSCON_CLOCK_CONTROL); + + DPRINTK("DMA Open - power control: 0x%x \n", inl(SYSCON_PWRCNT) ); + + /* + * Clear out the control register before any further setup. + */ + outl( 0, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * Setup the transfer mode and the request source selection within + * the DMA M2M channel registers. + */ + switch (device) { + case DMA_MEMORY: + /* + * Clear TM field, set RSS field to 0 + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~(CONTROL_M2M_TM_MASK | CONTROL_M2M_RSS_MASK); + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + break; + + case DMA_IDE: + /* + * Set RSS field to 3, Set NO_HDSK, Set PW field to 1 + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~(CONTROL_M2M_RSS_MASK|CONTROL_M2M_PW_MASK); + uiCONTROL |= (3<pause || (!dma->pause && dma->xfer_enable)) */ + if (dma->xfer_enable) { + /* + * DMA channel is not paused, so we can't configure it. + */ + DPRINTK("DMA channel not paused, so can't configure! \n"); + return(-1); + } + + /* + * Mask interrupts. + */ + local_irq_save(flags); + + /* + * Setup a pointer into the dma channel's register set. + */ + M2M_reg_base = dma->reg_base; + + uiCONTROL = inl(M2M_reg_base + M2M_OFFSET_CONTROL); + outl(0, M2M_reg_base + M2M_OFFSET_CONTROL); + inl(M2M_reg_base + M2M_OFFSET_CONTROL); + outl(uiCONTROL, M2M_reg_base + M2M_OFFSET_CONTROL); + + /* + * By default we disable the stall interrupt. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_STALLINTEN; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * By default we disable the done interrupt. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_DONEINTEN; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * Set up the transfer control fields based on values passed in + * the flags_m2m field. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + + if ( flags_m2m & DESTINATION_HOLD ) + uiCONTROL |= CONTROL_M2M_DAH; + else + uiCONTROL &= ~CONTROL_M2M_DAH; + + if ( flags_m2m & SOURCE_HOLD ) + uiCONTROL |= CONTROL_M2M_SAH; + else + uiCONTROL &= ~CONTROL_M2M_SAH; + + uiCONTROL &= ~CONTROL_M2M_TM_MASK; + uiCONTROL |= (((flags_m2m & TRANSFER_MODE_MASK) >> TRANSFER_MODE_SHIFT) << + CONTROL_M2M_TM_SHIFT) & CONTROL_M2M_TM_MASK; + + uiCONTROL &= ~CONTROL_M2M_PWSC_MASK; + uiCONTROL |= (((flags_m2m & WAIT_STATES_MASK) >> WAIT_STATES_SHIFT) << + CONTROL_M2M_PWSC_SHIFT) & CONTROL_M2M_PWSC_MASK; + + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + inl(M2M_reg_base + M2M_OFFSET_CONTROL); + + /* + * Save the callback function in the dma instance for this channel. + */ + dma->callback = callback; + + /* + * Save the user data in the the dma instance for this channel. + */ + dma->user_data = user_data; + + /* + * Put the dma instance into the pause state by setting the + * pause bit to true. + */ + dma->pause = TRUE; + + local_irq_restore(flags); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * int dma_start(int handle, unsigned int channels, unsigned int * handles) + * + * Description: Initiate a transfer on up to 3 channels. + * + * handle: handle for the channel to initiate transfer on. + * channels: number of channels to initiate transfers on. + * handles: pointer to an array of handles, one for each channel which + * is to be started. + * + ****************************************************************************/ +static int +dma_start_m2m(int channel, ep93xx_dma_t * dma) +{ + unsigned long flags; + unsigned int M2M_reg_base = dma->reg_base; + unsigned int uiCONTROL; + + /* + * Mask interrupts while we get this started. + */ + local_irq_save(flags); + + /* + * Make sure the channel has at least one buffer in the queue. + */ + if (dma->new_buffers < 1) { + /* + * Unmask irqs + */ + local_irq_restore(flags); + + DPRINTK("DMA Start: Channel starved.\n"); + + /* + * This channel does not have enough buffers queued up, + * so enter the pause by starvation state. + */ + dma->xfer_enable = TRUE; + dma->pause = TRUE; + + /* + * Success. + */ + return(0); + } + + /* + * Clear any pending interrupts. + */ + outl(0x0, M2M_reg_base+M2M_OFFSET_INTERRUPT); + + /* + * Set up one or both buffer descriptors with values from the next one or + * two buffers in the queue. By default disable the next frame buffer + * interrupt on the channel. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_NFBINTEN; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * enable the done interrupt. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2M_DONEINTEN; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + /* + * Update the dma channel instance transfer state. + */ + dma->xfer_enable = TRUE; + dma->pause = FALSE; + + /* + * Program up the first buffer descriptor with a source and destination + * and a byte count. + */ + outl( dma->buffer_queue[dma->current_buffer].source, + M2M_reg_base+M2M_OFFSET_SAR_BASE0 ); + + outl( dma->buffer_queue[dma->current_buffer].dest, + M2M_reg_base+M2M_OFFSET_DAR_BASE0 ); + + outl( dma->buffer_queue[dma->current_buffer].size, + M2M_reg_base+M2M_OFFSET_BCR0 ); + + /* + * Decrement the new buffers counter. + */ + dma->new_buffers--; + + /* + * Set up the second buffer descriptor with a second buffer if we have + * a second buffer. + */ + if (dma->new_buffers) { + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].source, + M2M_reg_base+M2M_OFFSET_SAR_BASE1 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].dest, + M2M_reg_base+M2M_OFFSET_DAR_BASE1 ); + + outl( dma->buffer_queue[(dma->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].size, + M2M_reg_base+M2M_OFFSET_BCR1 ); + + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2M_NFBINTEN; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + + dma->new_buffers--; + } + + /* + * Now we enable the channel. This initiates the transfer. + */ + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2M_ENABLE; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + inl(M2M_reg_base + M2M_OFFSET_CONTROL); + + /* + * If this is a memory to memory transfer, we need to s/w trigger the + * transfer by setting the start bit within the control register. + */ + if (dma->device == DMA_MEMORY) { + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2M_START; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + } + + DPRINTK("DMA - It's been started!!"); + DPRINTK("CONTROL - 0x%x \n", inl(M2M_reg_base+M2M_OFFSET_CONTROL) ); + DPRINTK("STATUS - 0x%x \n", inl(M2M_reg_base+M2M_OFFSET_STATUS) ); + DPRINTK("BCR0 - 0x%x \n", dma->buffer_queue[dma->current_buffer].size); + DPRINTK("SAR_BASE0 - 0x%x \n", inl(M2M_reg_base+M2M_OFFSET_SAR_BASE0) ); + DPRINTK("SAR_CUR0 - 0x%x \n", inl(M2M_reg_base+M2M_OFFSET_SAR_CURRENT0) ); + DPRINTK("DAR_BASE0 - 0x%x \n", inl(M2M_reg_base+M2M_OFFSET_DAR_BASE0) ); + DPRINTK("DAR_CUR0 - 0x%x \n", inl(M2M_reg_base+M2M_OFFSET_DAR_CURRENT0) ); + + /* + * Unmask irqs + */ + local_irq_restore(flags); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * DMA interface functions + * + ****************************************************************************/ + +/***************************************************************************** + * + * int dma_init(int handle, unsigned int flags_m2p, unsigned int flags_m2m, + * dma_callback callback, unsigned int user_data) + * + * Description: Configure the DMA channel and install a callback function. + * + * handle: Handle unique the each instance of the dma interface, used + * to verify this call. + * flags_m2p Flags used to configure an M2P/P2M dma channel and determine + * if a callback function and user_data information are included + * in this call. This field should be NULL if handle represents + * an M2M channel. + * flags_m2m Flags used to configure an M2M dma channel and determine + * if a callback function and user_data information are included + * in this call. This field should be NULL if handle represents + * an M2P/P2M channel. + * callback function pointer which is called near the end of the + * dma channel's irq handler. + * user_data defined by the calling driver. + * + ****************************************************************************/ +int +ep93xx_dma_config(int handle, unsigned int flags_m2p, unsigned int flags_m2m, + dma_callback callback, unsigned int user_data) +{ + int channel; + ep93xx_dma_t * dma; + unsigned long flags; + unsigned int M2P_reg_base, uiCONTROL; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR + "DMA Config: Invalid dma handle.\n"); + return(-EINVAL); + } + + DPRINTK("DMA Config \n"); + + dma = &dma_chan[channel]; + + local_irq_save(flags); + + /* + * Check if the channel is currently transferring. + */ + if (dma->xfer_enable) { + local_irq_restore(flags); + return(-EINVAL); + } + + /* + * Check if this is an m2m function. + */ + if (channel >= 10) { + local_irq_restore(flags); + + /* + * Call another function to handle m2m config. + */ + return(dma_config_m2m(dma, flags_m2m, callback, user_data)); + } + + /* + * Setup a pointer into the dma channel's register set. + */ + M2P_reg_base = dma->reg_base; + + /* + * By default we enable the stall interrupt. + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2P_STALLINTEN; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + /* + * Configure the channel for an error from the peripheral. + */ + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + if ( flags_m2p && CHANNEL_ERROR_INT_ENABLE ) + uiCONTROL |= CONTROL_M2P_CHERRORINTEN; + else + uiCONTROL &= ~CONTROL_M2P_CHERRORINTEN; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + if ( flags_m2p && CHANNEL_ABORT ) + uiCONTROL |= CONTROL_M2P_ABRT; + else + uiCONTROL &= ~CONTROL_M2P_ABRT; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + if ( flags_m2p && IGNORE_CHANNEL_ERROR ) + uiCONTROL |= CONTROL_M2P_ICE; + else + uiCONTROL &= ~CONTROL_M2P_ICE; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + + /* + * Save the callback function in the dma instance for this channel. + */ + dma->callback = callback; + + /* + * Save the user data in the the dma instance for this channel. + */ + dma->user_data = user_data; + + /* + * Put the dma instance into the pause state by setting the + * pause bit to true. + */ + dma->pause = TRUE; + + local_irq_restore(flags); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * int dma_start(int handle, unsigned int channels, unsigned int * handles) + * + * Description: Initiate a transfer on up to 3 channels. + * + * handle: handle for the channel to initiate transfer on. + * channels: number of channels to initiate transfers on. + * handles: pointer to an array of handles, one for each channel which + * is to be started. + * + ****************************************************************************/ +int +ep93xx_dma_start(int handle, unsigned int channels, unsigned int * handles) +{ + ep93xx_dma_t * dma_pointers[3]; + unsigned int M2P_reg_bases[3]; + unsigned int loop, uiCONTROL; + unsigned long flags; + int channel; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR "DMA Start: Invalid dma handle.\n"); + return(-EINVAL); + } + + if (channels < 1) { + printk(KERN_ERR "DMA Start: Invalid parameter.\n"); + return(-EINVAL); + } + + DPRINTK("DMA Start \n"); + + /* + * Mask off registers. + */ + local_irq_save(flags); + + /* + * Check if this is a start multiple. + */ + if (channels > 1) { + DPRINTK("DMA ERROR: Start, multiple start not supported yet \n"); + return(-1); + } else { + /* + * Check if this channel is already transferring. + */ + if (dma_chan[channel].xfer_enable && !dma_chan[channel].pause) { + printk(KERN_ERR + "DMA Start: Invalid command for channel %d.\n", channel); + + /* + * Unmask irqs + */ + local_irq_restore(flags); + + /* + * This channel is already transferring, so return an error. + */ + return(-EINVAL); + } + + /* + * If this is an M2M channel, call a different function. + */ + if (channel >= 10) { + /* + * Unmask irqs + */ + local_irq_restore(flags); + + /* + * Call the m2m start function. Only start one channel. + */ + return(dma_start_m2m(channel, &dma_chan[channel])); + } + + /* + * Make sure the channel has at least one buffer in the queue. + */ + if (dma_chan[channel].new_buffers < 1) { + DPRINTK("DMA Start: Channel starved.\n"); + + /* + * This channel does not have enough buffers queued up, + * so enter the pause by starvation state. + */ + dma_chan[channel].xfer_enable = TRUE; + dma_chan[channel].pause = TRUE; + + /* + * Unmask irqs + */ + local_irq_restore(flags); + + /* + * Success. + */ + return(0); + } + + /* + * Set up a dma instance pointer for this dma channel. + */ + dma_pointers[0] = &dma_chan[channel]; + + /* + * Set up a pointer to the register set for this channel. + */ + M2P_reg_bases[0] = dma_pointers[0]->reg_base; + } + + /* + * Setup both MAXCNT registers with values from the next two buffers + * in the queue, and enable the next frame buffer interrupt on the channel. + */ + for (loop = 0; loop < channels; loop++) { + /* + * Check if we need to restore a paused transfer. + */ + if (dma_pointers[loop]->pause_buf.buf_id != -1) + outl( dma_pointers[loop]->pause_buf.size, + M2P_reg_bases[loop]+M2P_OFFSET_MAXCNT0 ); + else + outl( dma_pointers[loop]->buffer_queue[dma_pointers[loop]->current_buffer].size, + M2P_reg_bases[loop]+M2P_OFFSET_MAXCNT0 ); + } + + for (loop = 0; loop < channels; loop++) { + /* + * Enable the specified dma channels. + */ + uiCONTROL = inl(M2P_reg_bases[loop]+M2P_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2P_ENABLE; + outl( uiCONTROL, M2P_reg_bases[loop]+M2P_OFFSET_CONTROL ); + + /* + * Update the dma channel instance transfer state. + */ + dma_pointers[loop]->xfer_enable = TRUE; + dma_pointers[loop]->pause = FALSE; + } + + /* + * Program up the BASE0 registers for all specified channels, this + * will initiate transfers on all specified channels. + */ + for (loop = 0; loop < channels; loop++) + /* + * Check if we need to restore a paused transfer. + */ + if (dma_pointers[loop]->pause_buf.buf_id != -1) { + outl( dma_pointers[loop]->pause_buf.source, + M2P_reg_bases[loop]+M2P_OFFSET_BASE0 ); + + /* + * Set the pause buffer to NULL + */ + dma_pointers[loop]->pause_buf.buf_id = -1; + dma_pointers[loop]->pause_buf.size = 0; + } else if(dma_pointers[loop]->new_buffers){ + outl( dma_pointers[loop]->buffer_queue[ + dma_pointers[loop]->current_buffer].source, + M2P_reg_bases[loop]+M2P_OFFSET_BASE0 ); + dma_pointers[loop]->new_buffers--; + + } + + /* + * Before restoring irqs setup the second MAXCNT/BASE + * register with a second buffer. + */ + for (loop = 0; loop < channels; loop++) + if (dma_pointers[loop]->new_buffers) { + /* + * By default we enable the next frame buffer interrupt. + */ + uiCONTROL = inl(M2P_reg_bases[loop]+M2P_OFFSET_CONTROL); + uiCONTROL |= CONTROL_M2P_NFBINTEN; + outl( uiCONTROL, M2P_reg_bases[loop]+M2P_OFFSET_CONTROL ); + + outl( dma_pointers[loop]->buffer_queue[ + (dma_pointers[loop]->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].size, + M2P_reg_bases[loop]+M2P_OFFSET_MAXCNT1 ); + + outl( dma_pointers[loop]->buffer_queue[ + (dma_pointers[loop]->current_buffer + 1) % + MAX_EP93XX_DMA_BUFFERS].source, + M2P_reg_bases[loop]+M2P_OFFSET_BASE1 ); + dma_pointers[loop]->new_buffers--; + } + + /* + DPRINTK("DMA - It's been started!!"); + DPRINTK("STATUS - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_STATUS) ); + DPRINTK("CONTROL - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CONTROL) ); + DPRINTK("REMAIN - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_REMAIN) ); + DPRINTK("PPALLOC - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_PPALLOC) ); + DPRINTK("BASE0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE0) ); + DPRINTK("MAXCNT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT0) ); + DPRINTK("CURRENT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT0) ); + DPRINTK("BASE1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE1) ); + DPRINTK("MAXCNT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT1) ); + DPRINTK("CURRENT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT1) ); + + DPRINTK("Pause - %d \n", dma_pointers[0]->pause); + DPRINTK("xfer_enable - %d \n", dma_pointers[0]->xfer_enable); + DPRINTK("total bytes - 0x%x \n", dma_pointers[0]->total_bytes); + DPRINTK("total buffer - %d \n", dma_pointers[0]->total_buffers); + DPRINTK("new buffers - %d \n", dma_pointers[0]->new_buffers); + DPRINTK("current buffer - %d \n", dma_pointers[0]->current_buffer); + DPRINTK("last buffer - %d \n", dma_pointers[0]->last_buffer); + DPRINTK("used buffers - %d \n", dma_pointers[0]->used_buffers); + */ + /* + * Unmask irqs + */ + local_irq_restore(flags); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * int ep93xx_dma_add_buffer(int handle, unsigned int * address, + * unsigned int size, unsigned int last) + * + * Description: Add a buffer entry to the DMA buffer queue. + * + * handle: handle for the channel to add this buffer to. + * address: Pointer to an integer which is the start address of the + * buffer which is to be added to the queue. + * size: size of the buffer in bytes. + * last: 1 if this is the last buffer in this stream, 0 otherwise. + * + ****************************************************************************/ +int +ep93xx_dma_add_buffer(int handle, unsigned int source, unsigned int dest, + unsigned int size, unsigned int last, + unsigned int buf_id) +{ + unsigned long flags; + ep93xx_dma_t * dma; + int channel; +#if 0 + static int peak_total_buffers=0; +#endif + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR + "DMA Add Buffer: Invalid dma handle.\n"); + return(-EINVAL); + } + + /* + * Get a pointer to the dma instance. + */ + dma = &dma_chan[channel]; + +#if 0 + if( dma->total_buffers > peak_total_buffers ) + { + peak_total_buffers=dma->total_buffers; + printk("peak_total_buffers=%d\n", peak_total_buffers ); + } +#endif + /* + * Mask interrupts and hold on to the original state. + */ + local_irq_save(flags); + + /* + * If the buffer queue is full, last_buffer is the same as current_buffer and + * we're not tranfering, or last_buffer is pointing to a used buffer, then exit. + * TODO: do I need to do any more checks? + */ + if (dma->total_buffers >= MAX_EP93XX_DMA_BUFFERS) + { + DPRINTK("too many dma buffers: MAX_EP93XX_DMA_BUFFERS set to low ?\n"); + /* + * Restore the state of the irqs + */ + local_irq_restore(flags); + + /* + * Fail. + */ + return(-1); + } + + /* + * Add this buffer to the queue + */ + dma->buffer_queue[dma->last_buffer].source = source; + dma->buffer_queue[dma->last_buffer].dest = dest; + dma->buffer_queue[dma->last_buffer].size = size; + dma->buffer_queue[dma->last_buffer].last = last; + dma->buffer_queue[dma->last_buffer].buf_id = buf_id; + + /* + * Reset the used field of the buffer structure. + */ + dma->buffer_queue[dma->last_buffer].used = FALSE; + + /* + * Increment the End Item Pointer. + */ + dma->last_buffer = (dma->last_buffer + 1) % MAX_EP93XX_DMA_BUFFERS; + + /* + * Increment the new buffers counter and the total buffers counter + */ + dma->new_buffers++; + dma->total_buffers++; + + /* + * restore the interrupt state. + */ + local_irq_restore(flags); + + /* + * Check if the channel was starved into a stopped state. + */ + if (dma->pause && dma->xfer_enable) { + if (dma->new_buffers >= 1) { + DPRINTK("DMA - calling start from add after starve. \n"); + + /* + * The channel was starved into a stopped state, and we've got + * 2 new buffers, so start tranferring again. + */ + ep93xx_dma_start(handle, 1, 0); + } + } + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * int ep93xx_dma_remove_buffer(int handle, unsigned int * address, + * unsigned int * size) + * + * Description: Remove a buffer entry from the DMA buffer queue. If + * buffer was removed successfully, return 0, otherwise + * return -1. + * + * handle: handle for the channel to remove a buffer from. + * address: Pointer to an integer which is filled in with the start + * address of the removed buffer. + * size: Pointer to an integer which is filled in with the size in + * bytes of the removed buffer. + * + ****************************************************************************/ +int +ep93xx_dma_remove_buffer(int handle, unsigned int * buf_id) +{ + unsigned int test; + unsigned int loop; + int return_val = -1; + unsigned long flags; + ep93xx_dma_t *dma; + int channel; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR + "DMA Remove Buffer: Invalid dma handle.\n"); + return(-EINVAL); + } + + dma = &dma_chan[channel]; + + /* + * Mask interrupts and hold on to the original state. + */ + local_irq_save(flags); + + /* + * Make sure there are used buffers to be returned. + */ + if (dma->used_buffers) { + test = dma->last_buffer; + + for (loop = 0; loop < MAX_EP93XX_DMA_BUFFERS; loop++) { + if (dma->buffer_queue[test].used && (dma->buffer_queue[test].buf_id != -1)) { + /*DPRINTK("buffer %d used \n", test); */ + + /* + * This is a used buffer, fill in the buf_id pointer + * with the buf_id for this buffer. + */ + *buf_id = dma->buffer_queue[test].buf_id; + + /* + * Reset this buffer structure + */ + dma->buffer_queue[test].buf_id = -1; + + /* + * Decrement the used buffer counter, and the total buffer counter. + */ + dma->used_buffers--; + dma->total_buffers--; + + /* + * Successful removal of a buffer, so set the return + * value to 0, then exit this loop. + */ + return_val = 0; + break; + } + + /* + * This buffer isn't used, let's see if the next one is. + */ + test = (test + 1) % MAX_EP93XX_DMA_BUFFERS; + } + } + + /* + * Restore interrupts. + */ + local_irq_restore(flags); + + /* + * Success. + */ + return(return_val); +} + +/***************************************************************************** + * + * int ep93xx_dma_pause(int handle, unsigned int channels, + * unsigned int * handles) + * + * Description: Disable any ongoing transfer for the given channel, retaining + * the state of the current buffer transaction so that upon + * resume, the dma will continue where it left off. + * + * handle: Handle for the channel to be paused. If this is a pause for + * for multiple channels, handle is a valid handle for one of + * the channels to be paused. + * channels: number of channel to pause transfers on. + * handles: Pointer to an array of handles, one for each channel which + * to be paused. If this pause is intended only for one + * channel, this field should be set to NULL. + * + ****************************************************************************/ +int +ep93xx_dma_pause(int handle, unsigned int channels, unsigned int * handles) +{ + unsigned long flags; + ep93xx_dma_t * dma; + int channel; + + DPRINTK("ep93xx_dma_pause \n"); + + /* + * Mask interrupts and hold on to the original state. + */ + local_irq_save(flags); + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + /* + * restore interrupts. + */ + local_irq_restore(flags); + + printk(KERN_ERR + "DMA Pause: Invalid dma handle.\n"); + + /* + * Fail. + */ + return(-EINVAL); + } + + DPRINTK("DMA %d: pause \n", channel); + + /* + * Set up a pointer to the dma instance data. + */ + dma = &dma_chan[channel]; + + /* + * Check if we're already paused. + */ + if (dma->pause) { + /* + * We're paused, but are we stopped? + */ + if (dma->xfer_enable) + /* + * Put the channel in the stopped state. + */ + dma->xfer_enable = FALSE; + + DPRINTK("DMA Pause - already paused."); + } else { + /* + * Put the channel into the stopped state. + */ + dma->xfer_enable = FALSE; + dma->pause = TRUE; + } + + /* + * restore interrupts. + */ + local_irq_restore(flags); + + /* + * Already paused, so exit. + */ + return(0); +} + +/***************************************************************************** + * + * void ep93xx_dma_flush(int handle) + * + * Description: Flushes all queued buffers and transfers in progress + * for the given channel. Return the buffer entries + * to the calling function. + * + * handle: handle for the channel for which the flush is intended. + * + ****************************************************************************/ +int +ep93xx_dma_flush(int handle) +{ + unsigned int loop; + unsigned long flags; + ep93xx_dma_t * dma; + int channel; + unsigned int M2P_reg_base,uiCONTROL; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR "DMA Flush: Invalid dma handle.\n"); + return(-EINVAL); + } + + DPRINTK("DMA %d: flush \n", channel); + + /* + * Set up a pointer to the dma instance data for this channel + */ + dma = &dma_chan[channel]; + + /* + * Mask interrupts and hold on to the original state. + */ + local_irq_save(flags); + + /* + * Disable the dma channel + */ + if (channel < 10) { + /* + * M2P channel + */ + uiCONTROL = inl(dma->reg_base+M2P_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2P_ENABLE; + outl( uiCONTROL, dma->reg_base+M2P_OFFSET_CONTROL ); + } else { + /* + * M2M channel + */ + uiCONTROL = inl(dma->reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_ENABLE; + outl( uiCONTROL, dma->reg_base+M2M_OFFSET_CONTROL ); + } + + for (loop = 0; loop < MAX_EP93XX_DMA_BUFFERS; loop++) + { + dma->buffer_queue[loop].buf_id = -1; + dma->buffer_queue[loop].last = 0; + } + + /* + * Set the Current and Last item to zero. + */ + dma->current_buffer = 0; + dma->last_buffer = 0; + + /* + * Reset the Buffer counters + */ + dma->used_buffers = 0; + dma->new_buffers = 0; + dma->total_buffers = 0; + + /* + * reset the Total bytes counter. + */ + dma->total_bytes = 0; + + /* + * Reset the paused buffer. + */ + dma->pause_buf.last = 0; + dma->pause_buf.buf_id = -1; + + M2P_reg_base = dma_chan[channel].reg_base; + + /* + * restore interrupts. + */ + local_irq_restore(flags); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * int ep93xx_dma_queue_full(int handle) + * + * Description: Query to determine if the DMA queue of buffers for + * a given channel is full. + * 0 = queue is full + * 1 = queue is not full + * + * handle: handle for the channel to query. + * + ****************************************************************************/ +int +ep93xx_dma_queue_full(int handle) +{ + int list_full = 0; + unsigned long flags; + int channel; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR "DMA Queue Full: Invalid dma handle.\n"); + return(-EINVAL); + } + + DPRINTK("DMA %d: queue full \n", channel); + + /* + * Mask interrupts and hold on to the original state. + */ + local_irq_save(flags); + + /* + * If the last item is equal to the used item then + * the queue is full. + */ + if (dma_chan[channel].total_buffers < MAX_EP93XX_DMA_BUFFERS) + list_full = FALSE; + else + list_full = TRUE; + + /* + * restore interrupts. + */ + local_irq_restore(flags); + + return(list_full); +} + +/***************************************************************************** + * + * int ep93xx_dma_get_position() + * + * Description: Takes two integer pointers and fills them with the start + * and current address of the buffer currently transferring + * on the specified DMA channel. + * + * handle handle for the channel to query. + * *buf_id buffer id for the current buffer transferring on the + * dma channel. + * *total total bytes transferred on the channel. Only counts + * whole buffers transferred. + * *current_frac number of bytes transferred so far in the current buffer. + ****************************************************************************/ +int +ep93xx_dma_get_position(int handle, unsigned int * buf_id, + unsigned int * total, unsigned int * current_frac ) +{ + int channel; + ep93xx_dma_t * dma; + unsigned int buf_id1, total1, current_frac1, buf_id2, total2; + unsigned int Status, NextBuffer, StateIsBufNext, M2P_reg_base=0; + unsigned int pause1, pause2; + + /* + * Get the DMA hw channel # from the handle. See if this is a + * valid handle. + */ + channel = dma_get_channel_from_handle(handle); + if (channel < 0) { + printk(KERN_ERR "DMA Get Position: Invalid dma handle.\n"); + return(-EINVAL); + } + + dma = &dma_chan[channel]; + + /* + * If DMA moves to a new buffer in the middle of us grabbing the + * buffer info, then do it over again. + */ + do{ + buf_id1 = dma->buffer_queue[dma->current_buffer].buf_id; + total1 = dma->total_bytes; + pause1 = dma->pause; + + if (channel < 10) { + // M2P + M2P_reg_base = dma->reg_base; + + Status = inl(M2P_reg_base+M2P_OFFSET_STATUS); + + NextBuffer = ((Status & STATUS_M2P_NEXTBUFFER) != 0); + + StateIsBufNext = ((Status & STATUS_M2P_CURRENT_MASK) == + STATUS_M2P_DMA_BUF_NEXT); + + if( NextBuffer ^ StateIsBufNext ) + current_frac1 = inl(M2P_reg_base+M2P_OFFSET_CURRENT1) - + inl(M2P_reg_base+M2P_OFFSET_BASE1); + else + current_frac1 = inl(M2P_reg_base+M2P_OFFSET_CURRENT0) - + inl(M2P_reg_base+M2P_OFFSET_BASE0); + + } else { + // M2M - TODO implement this for M2M + current_frac1 = 0; + } + + buf_id2 = dma->buffer_queue[dma->current_buffer].buf_id; + total2 = dma->total_bytes; + pause2 = dma->pause; + + } while ( (buf_id1 != buf_id2) || (total1 != total2) || (pause1 != pause2) ); + + if (pause1) + current_frac1 = 0; + + if (buf_id) + *buf_id = buf_id1; + + if (total) + *total = total1; + + if (current_frac) + *current_frac = current_frac1; + +// DPRINTK("DMA buf_id %d, total %d, frac %d\n", buf_id1, total1, current_frac1); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * int ep93xx_dma_get_total(int handle) + * + * Description: Returns the total number of bytes transferred on the + * specified channel since the channel was requested. + * + * handle: handle for the channel to query. + * + ****************************************************************************/ +int +ep93xx_dma_get_total(int handle) +{ + int channel; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR "DMA Get Total: Invalid dma handle.\n"); + return(-EINVAL); + } + + DPRINTK("DMA %d: total: %d \n", channel, dma_chan[channel].total_bytes); + + /* + * Return the total number of bytes transferred on this channel since + * it was requested. + */ + return(dma_chan[channel].total_bytes); +} + +/***************************************************************************** + * + * int ep93xx_dma_is_done(int handle) + * + * Description: Determines if the specified channel is done + * transferring the requested data. + * + * handle: handle for the channel to query. + * + ****************************************************************************/ +int +ep93xx_dma_is_done(int handle) +{ + ep93xx_dma_t *dma; + int channel; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR "ep93xx_dma_is_done: Invalid dma handle.\n"); + return(-EINVAL); + } + + /* + * Get a pointer to the DMA channel state structure. + */ + dma = &dma_chan[channel]; + + /* + * See if there are any buffers remaining to be provided to the HW. + */ + if (dma->new_buffers) + return 0; + + /* + * See if this is a M2P or M2M channel. + */ + if (channel < 10) { + /* + * If the bytes remaining register of the HW is not zero, then + * there is more work to be done. + */ + if (inl(dma->reg_base + M2P_OFFSET_REMAIN) != 0) + return 0; + } else { + /* + * If either byte count register in the HW is not zero, then there + * is more work to be done. + */ + if ((inl(dma->reg_base + M2M_OFFSET_BCR0) != 0) || + (inl(dma->reg_base + M2M_OFFSET_BCR1) != 0)) + return 0; + } + + /* + * The DMA is complete. + */ + return 1; +} + +/***************************************************************************** + * ep93xx_dma_request + * + * Description: This function will allocate a DMA channel for a particular + * hardware peripheral. Before initiating a transfer on the allocated + * channel, the channel must be set up and buffers have to queued up. + * + * handle: pointer to an integer which is filled in with a unique + * handle for this instance of the dma interface. + * device_id string with the device name, primarily used by /proc. + * device hardware device ID for which the requested dma channel will + * transfer data. + * + ****************************************************************************/ +int +ep93xx_dma_request(int * handle, const char *device_id, + ep93xx_dma_dev_t device) +{ + ep93xx_dma_t *dma = NULL; + int channel; + unsigned int error = 0; + unsigned int loop; + unsigned int M2P_reg_base; + + /* + * Check if the device requesting a DMA channel is a valid device. + */ + if ((device >= UNDEF) || (device < 0)) + return(-ENODEV); + + /* + * We've got a valid hardware device requesting a DMA channel. + * Now check if the device should open an M2P or M2M channel + */ + if (device < 20) + channel = dma_open_m2p(device); + else + channel = dma_open_m2m(device); + + /* + * Check if we successfully opened a DMA channel + */ + if (channel < 0) { + printk(KERN_ERR "%s: Could not open dma channel for this device.\n", + device_id); + return(-EBUSY); + } + + dma = &dma_chan[channel]; + + /* + * Request the appropriate IRQ for the specified channel + */ + if (channel < 10) + error = request_irq(dma->irq, dma_m2p_irq_handler, + IRQF_DISABLED, device_id, (void *) dma); + else + error = request_irq(dma->irq, &dma_m2m_irq_handler, + IRQF_DISABLED, device_id, (void *) dma); + /* + * Check for any errors during the irq request + */ + if (error) { + printk(KERN_ERR "%s: unable to request IRQ %d for DMA channel\n", + device_id, dma->irq); + return(error); + } + + /* + * Generate a valid handle and exit. + * + * Increment the last valid handle. + * Check for wraparound (unlikely, but we like to be complete). + */ + dma->last_valid_handle++; + + if ( (dma->last_valid_handle & DMA_HANDLE_SPECIFIER_MASK) != + (channel << 28) ) + dma->last_valid_handle = (channel << 28) + 1; + + /* + * Fill in the handle pointer with a valid handle for + * this dma channel instance. + */ + *handle = dma->last_valid_handle; + + DPRINTK("Handle for channel %d: 0x%x\n", channel, *handle); + + /* + * Save the device ID and device name. + */ + dma->device = device; + dma->device_id = device_id; + + /* + * Init all fields within the dma instance. + */ + for (loop = 0; loop < MAX_EP93XX_DMA_BUFFERS; loop++) + dma->buffer_queue[loop].buf_id = -1; + + /* + * Initialize all buffer queue variables. + */ + dma->current_buffer = 0; + dma->last_buffer = 0; + + dma->new_buffers = 0; + dma->used_buffers = 0; + dma->total_buffers = 0; + + /* + * Initialize the total bytes variable + */ + dma->total_bytes = 0; + + /* + * Initialize the transfer and pause state variables to 0. + */ + dma->xfer_enable = 0; + + dma->pause = 0; + + /* + * Initialize the pause buffer structure. + */ + dma->pause_buf.buf_id = -1; + + /* + * Initialize the callback function and user data fields. + */ + dma->callback = NULL; + + /* + * User data used as a parameter for the Callback function. The user + * sets up the data and sends it with the callback function. + */ + dma->user_data = 0; + + M2P_reg_base = dma_chan[channel].reg_base; + + /* + * Debugging message. + */ + DPRINTK("Successfully requested dma channel %d\n", channel); + DPRINTK("STATUS - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_STATUS) ); + DPRINTK("CONTROL - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CONTROL) ); + DPRINTK("REMAIN - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_REMAIN) ); + DPRINTK("PPALLOC - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_PPALLOC) ); + DPRINTK("BASE0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE0) ); + DPRINTK("MAXCNT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT0) ); + DPRINTK("CURRENT0 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT0) ); + DPRINTK("BASE1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_BASE1) ); + DPRINTK("MAXCNT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_MAXCNT1) ); + DPRINTK("CURRENT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT1) ); + + DPRINTK("Buffer source size last used \n"); + for (loop = 0; loop < 5; loop ++) + DPRINTK("%d 0x%x 0x%x %d %d \n", + loop, dma->buffer_queue[loop].source, dma->buffer_queue[loop].size, + dma->buffer_queue[loop].last, dma->buffer_queue[loop].used); + DPRINTK("pause 0x%x 0x%x %d %d \n", + dma->pause_buf.source, dma->pause_buf.size, + dma->pause_buf.last, dma->pause_buf.used); + + DPRINTK("Pause - %d \n", dma->pause); + DPRINTK("xfer_enable - %d \n", dma->xfer_enable); + DPRINTK("total bytes - 0x%x \n", dma->total_bytes); + DPRINTK("total buffer - %d \n", dma->total_buffers); + DPRINTK("new buffers - %d \n", dma->new_buffers); + DPRINTK("current buffer - %d \n", dma->current_buffer); + DPRINTK("last buffer - %d \n", dma->last_buffer); + DPRINTK("used buffers - %d \n", dma->used_buffers); + + DPRINTK("CURRENT1 - 0x%x \n", inl(M2P_reg_base+M2P_OFFSET_CURRENT1) ); + DPRINTK("VIC0IRQSTATUS - 0x%x, VIC0INTENABLE - 0x%x \n", + *(unsigned int *)(VIC0IRQSTATUS), + *(unsigned int *)(VIC0INTENABLE)); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * ep93xx_dma_free + * + * Description: This function will free the dma channel for future requests. + * + * handle: handle for the channel to be freed. + * + ****************************************************************************/ +int +ep93xx_dma_free(int handle) +{ + ep93xx_dma_t *dma; + unsigned int M2M_reg_base, M2P_reg_base, uiCONTROL; + int channel; + + /* + * Get the DMA hw channel # from the handle. + */ + channel = dma_get_channel_from_handle(handle); + + /* + * See if this is a valid handle. + */ + if (channel < 0) { + printk(KERN_ERR "DMA Free: Invalid dma handle.\n"); + return(-EINVAL); + } + + /* + * Get a pointer to the dma instance. + */ + dma = &dma_chan[channel]; + + /* + * Disable the dma channel + */ + if (channel < 10) { + /* + * M2P channel + */ + M2P_reg_base = dma->reg_base; + + uiCONTROL = inl(M2P_reg_base+M2P_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2P_ENABLE; + outl( uiCONTROL, M2P_reg_base+M2P_OFFSET_CONTROL ); + } else { + /* + * M2M channel + */ + M2M_reg_base = dma->reg_base; + + uiCONTROL = inl(M2M_reg_base+M2M_OFFSET_CONTROL); + uiCONTROL &= ~CONTROL_M2M_ENABLE; + outl( uiCONTROL, M2M_reg_base+M2M_OFFSET_CONTROL ); + } + + /* + * Free the interrupt servicing this dma channel + */ + + free_irq(dma->irq, (void *) dma); + + /* + * Decrement the reference count for this instance of the dma interface + */ + dma->ref_count--; + + /* + * Set the transfer and pause state variables to 0 + * (unititialized state). + */ + dma->xfer_enable = 0; + dma->pause = 0; + + /* + * Debugging message. + */ + DPRINTK("Successfully freed dma channel %d\n", channel); + + /* + * Success. + */ + return(0); +} + +/***************************************************************************** + * + * ep93xx_dma_init(void) + * + * Description: This function is called during system initialization to + * setup the interrupt number and register set base address for each DMA + * channel. + * + ****************************************************************************/ +static int __init +ep93xx_dma_init(void) +{ + int channel; + + /* + * Init some values in each dma instance. + */ + for (channel = 0; channel < MAX_EP93XX_DMA_CHANNELS; channel++) { + /* + * IRQ for the specified dma channel. + */ + dma_chan[channel].irq = IRQ_EP93XX_DMAM2P0 + channel; + + /* + * Initial value of the dma channel handle. + */ + dma_chan[channel].last_valid_handle = channel << 28; + + /* + * Give the instance a pointer to the dma channel register + * base. + */ + if (channel < 10) + dma_chan[channel].reg_base = DMAM2PChannelBase[channel]; + else + dma_chan[channel].reg_base = DMAM2MChannelBase[channel - 10]; + + /* + * Initialize the reference count for this channel. + */ + dma_chan[channel].ref_count = 0; + } + + DPRINTK("DMA Interface intitialization complete\n"); + + /* + * Success + */ + return 0; +} + +arch_initcall(ep93xx_dma_init); + +EXPORT_SYMBOL(ep93xx_dma_free); +EXPORT_SYMBOL(ep93xx_dma_request); +EXPORT_SYMBOL(ep93xx_dma_flush); +EXPORT_SYMBOL(ep93xx_dma_pause); +EXPORT_SYMBOL(ep93xx_dma_remove_buffer); +EXPORT_SYMBOL(ep93xx_dma_add_buffer); +EXPORT_SYMBOL(ep93xx_dma_start); +EXPORT_SYMBOL(ep93xx_dma_config); diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/dma_ep93xx.h linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/dma_ep93xx.h --- linux-2.6.25/arch/arm/mach-ep93xx/dma_ep93xx.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/dma_ep93xx.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,199 @@ +/***************************************************************************** + * + * arch/arm/mach-ep93xx/dma_ep93xx.h + * + * DESCRIPTION: 93XX DMA controller API private defintions. + * + * Copyright Cirrus Logic Corporation, 2003. All rights reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + ****************************************************************************/ +#ifndef _EP93XX_DMA_H_ +#define _EP93XX_DMA_H_ + +// as it turns out the ide dma is the biggest dma buffer hog so far +// in case the HDD is "thinking" (seek/buffer flush) +// the continueing r/w DMAs to the HDD will be queued up to up to PRD_ENTRIES entries... +#include +#define MAX_EP93XX_DMA_BUFFERS PRD_ENTRIES + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif + +/***************************************************************************** + * + * DMA buffer structure type. + * + ****************************************************************************/ +typedef struct ep93xx_dma_buffer_s +{ + unsigned int source; /* buffer physical source address. */ + unsigned int dest; /* buffer physical destination address, */ + /* only used with the 2 M2M channels. */ + unsigned int size; /* buffer size in bytes */ + unsigned int last; /* 1 if this is the last buffer */ + /* in this transaction. If 1, */ + /* disable the NFBint so we aren't */ + /* interrupted for another buffer */ + /* when we know there won't be another. */ + unsigned int used; /* This field is set to 1 by the DMA */ + /* interface after the buffer is transferred*/ + int buf_id; /* unique identifyer specified by the */ + /* the driver which requested the dma */ +} ep93xx_dma_buffer_t; + +typedef ep93xx_dma_buffer_t * ep93xx_dma_buffer_p; + +/***************************************************************************** + * + * Instance definition for the DMA interface. + * + ****************************************************************************/ +typedef struct ep9312_dma_s +{ + /* + * This 1 when the instance is in use, and 0 when it's not. + */ + unsigned int ref_count; + + /* + * This is the last valid handle for this instance. When giving out a + * new handle this will be incremented and given out. + */ + int last_valid_handle; + + /* + * device specifies one of the 20 DMA hardware ports this + * DMA channel will service. + */ + ep93xx_dma_dev_t device; + + /* + * DMABufferQueue is the queue of buffer structure pointers which the + * dma channel will use to setup transfers. + */ + ep93xx_dma_buffer_t buffer_queue[MAX_EP93XX_DMA_BUFFERS]; + + /* + * currnt_buffer : This is the buffer currently being transfered on + * this channel. + * last_buffer : This is the last buffer for this transfer. + * Note: current_buffer + 1 is already programmed into the dma + * channel as the next buffer to transfer. Don't write + * over either entry. + */ + int current_buffer; + int last_buffer; + + /* + * The following 3 fields are buffer counters. + * + * iNewBuffers: Buffers in the queue which have not been transfered. + * iUsedBuffers: Buffers in the queue which have have been tranferred, + * and are waiting to be returned. + * iTotalBuffers: Total number of buffers in the queue. + */ + int new_buffers; + int used_buffers; + int total_buffers; + + /* + * uiTotalBytes has the total bytes transfered on the channel since the + * last flush. This value does not include the bytes tranfered in the + * current buffer. A byte count is only added after a complete buffer + * is tranfered. + */ + unsigned int total_bytes; + + /* + * Interrupt number for this channel + */ + unsigned int irq; + + /* + * Indicates whether or not the channel is currently enabled to transfer + * data. + */ + unsigned int xfer_enable; + + /* + * pause indicates if the dma channel was paused by calling the pause + * ioctl. + */ + unsigned int pause; + + /* + * buffer structure used during a pause to capture the current + * address and remaining bytes for the buffer actively being transferred + * on the channel. This buffer will be used to reprogram the dma + * channel upon a resume. + */ + ep93xx_dma_buffer_t pause_buf; + + /* + * DMACallback is a function pointer which the calling application can + * use install a function to. this fuction can be used to notify the + * calling application of an interrupt. + */ + dma_callback callback; + + /* + * User data used as a parameter for the Callback function. The user + * sets up the data and sends it with the callback function. + */ + unsigned int user_data; + + /* + * A string representation of the device attached to the channel. + */ + const char * device_id; + + /* + * The register base address for this dma channel. + */ + unsigned int reg_base; + +} ep93xx_dma_t; + +/***************************************************************************** + * + * DMA macros + * + ****************************************************************************/ +#define DMA_HANDLE_SPECIFIER_MASK 0xF0000000 +#define DMA_CH0_HANDLE_SPECIFIER 0x00000000 +#define DMA_CH1_HANDLE_SPECIFIER 0x10000000 +#define DMA_CH2_HANDLE_SPECIFIER 0x20000000 +#define DMA_CH3_HANDLE_SPECIFIER 0x30000000 +#define DMA_CH4_HANDLE_SPECIFIER 0x40000000 +#define DMA_CH5_HANDLE_SPECIFIER 0x50000000 +#define DMA_CH6_HANDLE_SPECIFIER 0x60000000 +#define DMA_CH7_HANDLE_SPECIFIER 0x70000000 +#define DMA_CH8_HANDLE_SPECIFIER 0x80000000 +#define DMA_CH9_HANDLE_SPECIFIER 0x90000000 +#define DMA_CH10_HANDLE_SPECIFIER 0xA0000000 +#define DMA_CH11_HANDLE_SPECIFIER 0xB0000000 + +#endif // _DMADRV_H_ diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/Kconfig linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/Kconfig --- linux-2.6.25/arch/arm/mach-ep93xx/Kconfig 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/Kconfig 2008-12-08 12:37:17.000000000 -0600 @@ -7,6 +7,26 @@ help Enable kernel support for MaverickCrunch. +config EP93XX_PWM + bool "Support EP93xx PWMs" + help + Say 'Y' here if you want your kernel to support ep93xx pwms. + +config EP93XX_ATOD + bool "Support EP93xx AtoD" + help + Say 'Y' here if you want your kernel to support ep93xx AtoD. + +config PB1014 + bool "Support the PB1014 carrier" + help + Say 'Y' here if you want your kernel to support PB1014 carrier mappings + +config ROWCOL_GPIO + bool "Support rowcol gpio device" + help + Say 'Y' here if you want your kernel to support the SoM-9307M rowcol gpio device + comment "EP93xx Platforms" config MACH_ADSSPHERE @@ -27,12 +47,6 @@ Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9302A Evaluation Board. -config MACH_EDB9307 - bool "Support Cirrus Logic EDB9307" - help - Say 'Y' here if you want your kernel to support the Cirrus - Logic EDB9307 Evaluation Board. - config MACH_EDB9312 bool "Support Cirrus Logic EDB9312" help @@ -51,6 +65,67 @@ Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9315A Evaluation Board. +config MACH_THERMOTRON + bool "Support EMAC Thermotron Custom SBC" + help + Say 'Y' here if you want your kernel to support the EMAC.Inc + Thermotron/Gaia Custom Board based on the EDB9315A. + +config MACH_PPCE7 + bool "Support EMAC.Inc PPC-E7 SBC" + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc PPC-E7 board. + +config MACH_SOM9307M + bool "Support EMAC.Inc SOM-9307M SoM" + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc SOM-9307M SoM. + +config MACH_SOM9307M_SMI + bool "Support EMAC.Inc SOM-9307M SoM with SMI extensions" + depends on MACH_SOM9307M + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc SOM-9307M SoM with SMI extensions. + +config MACH_SOM9307M_SOFTRONICS + bool "Support EMAC.Inc SOM-9307M SoM with Softronics extensions" + depends on MACH_SOM9307M + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc SOM-9307M SoM with Softronics extensions. + +config MACH_SOM9307M_SOM200 + bool "Support EMAC.Inc SOM-9307M SoM with SOM-200ES extensions" + depends on MACH_SOM9307M + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc SOM-9307M SoM with SOM-200ES extensions. + +choice + prompt "NOR Flash size" + depends on MACH_SOM9307M || MACH_PPCE7 || MACH_SOM9307M_SMI + default MACH_EMAC9307_32 + +config MACH_EMAC9307_16 + bool "16MB" + help + Select this configuration for a 16MB + +config MACH_EMAC9307_32 + bool "32MB" + help + Select this configuration for a 32MB + +config MACH_EMAC9307_64 + bool "64MB" + help + Select this configuration for a 64MB + +endchoice + config MACH_GESBC9312 bool "Support Glomation GESBC-9312-sx" help @@ -88,6 +163,35 @@ Say 'Y' here if you want your kernel to support the Technologic Systems TS-72xx board. -endmenu +config MACH_IPAC9302 + bool "Support EMAC.Inc iPAC-9302 SBC" + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc iPAC-9302 board. + +choice + prompt "IPAC9302 Flash size" + depends on MACH_IPAC9302 + default MACH_IPAC9302_16 + + +config MACH_IPAC9302_16 + bool "IPAC9302 16MB" + help + Select this configuration for a 16MB IPAC-9302 +config MACH_IPAC9302_32 + bool "IPAC9302 32MB" + help + Select this configuration for a 32MB IPAC-9302 + +config MACH_IPAC9302_64 + bool "IPAC9302 64MB" + help + Select this configuration for a 64MB IPAC-9302 + +endchoice + +endmenu + endif diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/Makefile linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/Makefile --- linux-2.6.25/arch/arm/mach-ep93xx/Makefile 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/Makefile 2008-09-12 14:50:40.000000000 -0500 @@ -1,7 +1,7 @@ # # Makefile for the linux kernel. # -obj-y := core.o clock.o +obj-y := core.o clock.o dma_ep93xx.o obj-m := obj-n := obj- := @@ -9,10 +9,15 @@ obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB9302) += edb9302.o obj-$(CONFIG_MACH_EDB9302A) += edb9302a.o -obj-$(CONFIG_MACH_EDB9307) += edb9307.o obj-$(CONFIG_MACH_EDB9312) += edb9312.o obj-$(CONFIG_MACH_EDB9315) += edb9315.o obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o +obj-$(CONFIG_MACH_THERMOTRON) += emac-thermotron.o +obj-$(CONFIG_MACH_PPCE7) += emac9307.o +obj-$(CONFIG_MACH_SOM9307M) += emac9307.o obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o obj-$(CONFIG_MACH_MICRO9) += micro9.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o +obj-$(CONFIG_MACH_IPAC9302) += ipac9302.o +obj-$(CONFIG_EP93XX_PWM) += pwm-ep93xx.o +obj-$(CONFIG_EP93XX_ATOD) += atod-ep93xx.o diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/Makefile.boot linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/Makefile.boot --- linux-2.6.25/arch/arm/mach-ep93xx/Makefile.boot 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/Makefile.boot 2008-08-18 14:05:42.000000000 -0500 @@ -1,2 +1 @@ zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 diff -Naur linux-2.6.25/arch/arm/mach-ep93xx/pwm-ep93xx.c linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/pwm-ep93xx.c --- linux-2.6.25/arch/arm/mach-ep93xx/pwm-ep93xx.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/arch/arm/mach-ep93xx/pwm-ep93xx.c 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,149 @@ +/** + * ep93xx PWM interface, + * registers with misc classes if available. + * +*/ + +#include +#include +#include + + +//#define PWM_DEBUG + +#undef PWMDEBUG +#ifdef PWM_DEBUG + #define PWMDEBUG(x...) {printk("%s(): %d ",__PRETTY_FUNCTION__, __LINE__);printk(x);} +#else + #define PWMDEBUG(x...) do { } while (0) +#endif + +#define EP93XX_PWM_SUBCLASS 93 + +//#define get_sclk() (66000000) + +#define get_sclk() (14745600) + +//internal errors +#define SYSCLOCK_UNSUPPORTED -2 + +static inline int us2reg(__u32 *value){ + switch(get_sclk()){ + case 66000000:{ + const __u32 regmax = (0xffff/66); + PWMDEBUG("value in:%x\n",*value); + if(*value>regmax)*value=regmax; + *value*=66; + PWMDEBUG("value out:%x\n",*value); + // pwms seem to do funny things when zeros are written to period or width; + if(*value==0)*value=1; + return 0; + } + case 14745600:{ + const __u32 regmax = ((0xffff*100)/1475); + PWMDEBUG("value in:%x\n",*value); + if(*value>regmax)*value=regmax; + *value*=1475; + *value/=100; + PWMDEBUG("value out:%x\n",*value); + // pwms seem to do funny things when zeros are written to period or width; + if(*value==0)*value=1; + return 0; + } + default:return SYSCLOCK_UNSUPPORTED; + } +} + +static inline int reg2us(__u32 *value){ + switch(get_sclk()){ + case 66000000: + PWMDEBUG("value in:%x\n",*value); + *value/=66; + PWMDEBUG("value out:%x\n",*value); + return 0; + case 14745600: + PWMDEBUG("value in:%x\n",*value); + *value*=100; + *value/=1475; + PWMDEBUG("value out:%x\n",*value); + return 0; + default:return SYSCLOCK_UNSUPPORTED; + } +} + + +static int ep93xx_period_write(struct pwm_s *pwm, pwm_data period){ + if(us2reg(&period)==SYSCLOCK_UNSUPPORTED) + {printk("sysclock unsupported\n");return SYSCLOCK_UNSUPPORTED;} + + PWMDEBUG("period:%x\n",period); + iowrite16((u16)period,pwm->periodus); + + return 0; +} + +static int ep93xx_width_write(struct pwm_s *pwm, pwm_data width){ + if(us2reg(&width)==SYSCLOCK_UNSUPPORTED) + {printk("sysclock unsupported\n");return SYSCLOCK_UNSUPPORTED;} + + PWMDEBUG("widthus:%x\n",width); + iowrite16((u16)width,pwm->widthus); + return 0; +} + +static pwm_data ep93xx_period_read(struct pwm_s *pwm){ + __u32 period = ioread16(pwm->periodus); + + if(reg2us(&period)==SYSCLOCK_UNSUPPORTED) + {printk("sysclock unsupported\n");return SYSCLOCK_UNSUPPORTED;} + + PWMDEBUG("period:%x\n",period); + return (period); +} + +static pwm_data ep93xx_width_read(struct pwm_s *pwm){ + __u32 width = ioread16(pwm->widthus); + + if(reg2us(&width)==SYSCLOCK_UNSUPPORTED) + {printk("sysclock unsupported\n");return SYSCLOCK_UNSUPPORTED;} + + PWMDEBUG("width:%x\n",width); + return (width); +} + +static pwm_data ep93xx_pwm_inv_read(pwm_t *pwm){ + return (ioread16(pwm->control)&(1)); +} + +static int ep93xx_pwm_inv_write(pwm_t *pwm, pwm_data data){ + u16 pwmcontrol = (ioread16(pwm->control)&(~1))|((data)?(1):0); + iowrite16(pwmcontrol,pwm->control); + return 0; +} + + +struct class_device *ep93xx_pwm_device_create(unsigned long base, const char *name){ + pwm_t *pwm = kmalloc(sizeof(pwm_t),GFP_KERNEL); + memset(pwm,0,sizeof(pwm_t)); + pwm->name = name; + pwm->subclass = EP93XX_PWM_SUBCLASS; + + pwm->periodus = (u16 *)base; + pwm->widthus = (u16 *)(base+4); + pwm->control = (u16 *)(base+12); + + iowrite16(1,pwm->control);//invert by default to power up off + iowrite16(1,(u16 *)(base+8));//enable PWM + + pwm->widthus_write = ep93xx_width_write; + pwm->widthus_read = ep93xx_width_read; + pwm->periodus_write = ep93xx_period_write; + pwm->periodus_read = ep93xx_period_read; + pwm->invert_write = ep93xx_pwm_inv_write; + pwm->invert_read = ep93xx_pwm_inv_read; + printk("registering ep93xx pwm device: %s\n",name); + + return pwm_register_class_device(pwm); +} + + diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/dma.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/dma.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/dma.h 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/dma.h 2008-08-18 14:05:42.000000000 -0500 @@ -1,3 +1,246 @@ -/* +/***************************************************************************** * linux/include/asm-arm/arch-ep93xx/dma.h + * + * Copyright (C) 2003 Cirrus Logic + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + ****************************************************************************/ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +/* + * Not using the regular generic DMA interface for ep93xx. + */ +#define MAX_DMA_CHANNELS 0 + +/* + * The ep93xx dma controller has 5 memory to peripheral (TX) channels, 5 + * peripheral to memory (RX) channels and 2 memory to memory channels. + */ +#define MAX_EP93XX_DMA_M2P_CHANNELS 10 +#define MAX_EP93XX_DMA_M2M_CHANNELS 2 + +/* + * The generic arm linux api does not support the ep93xx dma model, therefore + * we use a set of dma support functions written specifically for this dma + * controller. + */ +#define MAX_EP93XX_DMA_CHANNELS (MAX_EP93XX_DMA_M2P_CHANNELS + MAX_EP93XX_DMA_M2M_CHANNELS) + +/***************************************************************************** + * + * Max DMA buffer size + * + ****************************************************************************/ +#define DMA_MAX_BUFFER_BYTES 0xFFFF + +/***************************************************************************** + * + * typedefs + * + ****************************************************************************/ + +/***************************************************************************** + * + * All devices which can use a DMA channel + * + * NOTE: There exist two types of DMA channels, those that transfer + * between an internal peripheral and memory (M2P/P2M), and + * those that transfer between an external peripheral and memory (M2M). + * This becomes a bit confusing when you take into account the fact + * that the M2M channels can also transfer between two specific + * internal peripherals and memory. + * The first 20 enumerated devices use the first type of channel (M2P/ + * P2M). The last six enumerations are specific to the M2M channels. + * + ****************************************************************************/ +typedef enum +{ + /* + * Hardware device options for the 10 M2P/P2M DMA channels. + */ + DMATx_I2S1 = 0x00000000, /* TX peripheral ports can be allocated an */ + DMATx_I2S2 = 0x00000001, /* even numbered DMA channel. */ + DMATx_AAC1 = 0x00000002, + DMATx_AAC2 = 0x00000003, + DMATx_AAC3 = 0x00000004, + DMATx_I2S3 = 0x00000005, + DMATx_UART1 = 0x00000006, + DMATx_UART2 = 0x00000007, + DMATx_UART3 = 0x00000008, + DMATx_IRDA = 0x00000009, + DMARx_I2S1 = 0x0000000A, /* RX perhipheral ports can be allocated an */ + DMARx_I2S2 = 0x0000000B, /* odd numbered DMA channel. */ + DMARx_AAC1 = 0x0000000C, + DMARx_AAC2 = 0x0000000D, + DMARx_AAC3 = 0x0000000E, + DMARx_I2S3 = 0x0000000F, + DMARx_UART1 = 0x00000010, + DMARx_UART2 = 0x00000011, + DMARx_UART3 = 0x00000012, + DMARx_IRDA = 0x00000013, + + /* + * Device options for the 2 M2M DMA channels + */ + DMA_MEMORY = 0x00000014, + DMA_IDE = 0x00000015, + DMARx_SSP = 0x00000016, + DMATx_SSP = 0x00000017, + DMATx_EXT_DREQ = 0x00000018, + DMARx_EXT_DREQ = 0x00000019, + UNDEF = 0x0000001A +} ep93xx_dma_dev_t; + +/***************************************************************************** + * + * Enumerated type used as a parameter for a callback function. + * Indicates the type of interrupt. + * + ****************************************************************************/ +typedef enum +{ + /* + * Common interrupts + */ + STALL, + NFB, + + /* + * Specific to M2P channels + */ + CHERROR, + + /* + * Specific to M2M channels + */ + DONE, + UNDEF_INT +} ep93xx_dma_int_t; + +/***************************************************************************** + * + * Init flag bit defintions for M2P/P2M flags. + * + ****************************************************************************/ + +/* + * Channel error interrupt enable. + */ +#define CHANNEL_ERROR_INT_ENABLE 0x00000001 + +/* + * Determines how the channel state machine behaves in the NEXT state and + * in receipt of a peripheral error. + * 0 -> NEXT -> ON (ignore the peripheral error.) + * 1 -> NEXT -> STALL (effectively disable the channel.) + */ +#define CHANNEL_ABORT 0x00000002 + +/* + * Ignore channel error interrupt. + */ +#define IGNORE_CHANNEL_ERROR 0x00000004 + +/***************************************************************************** + * + * Init flag bit defintions for M2M flags. + * + ****************************************************************************/ + +/* + * Destination address hold. This should be set for IDE write transfers + */ +#define DESTINATION_HOLD 0x0000001 + +/* + * Source Address hold. This should be set for IDE read transfers + */ +#define SOURCE_HOLD 0x0000002 + +/* + * Transfer mode. + * 00 - s/w initiated M2M transfer + * 01 - h/w initiated external peripheral transfer - memory to external + * peripheral/IDE/SSP. + * 10 - h/w initiated external peripheral transfer - external + * peripheral/IDE/SSP to memory. + * 11 - not used. + */ +#define TRANSFER_MODE_MASK 0x000000C +#define TRANSFER_MODE_SHIFT 2 +#define TRANSFER_MODE_SW 0x0000000 +#define TRANSFER_MODE_HW_M2P 0x0000004 +#define TRANSFER_MODE_HW_P2M 0x0000008 + +/* + * Peripheral wait states count. Latency in HCLK cycles needed by the + * peripheral to de-assert its request line once the transfer is + * finished. + * + * IDE Operation Wait States + * -------------- ------------ + * IDE MDMA read 0 + * IDE MDMA write 3 + * IDE UDMA read 1 + * IDE UDMA write 2 */ +#define WAIT_STATES_MASK 0x00007F0 +#define WAIT_STATES_SHIFT 4 +#define WS_IDE_MDMA_READ 0 +#define WS_IDE_MDMA_WRITE 3 +#define WS_IDE_UDMA_READ 1 +#define WS_IDE_UDMA_WRITE 2 + +/***************************************************************************** + * + * Type definition for the callback function + * + ****************************************************************************/ +typedef void (* dma_callback)(ep93xx_dma_int_t dma_int, + ep93xx_dma_dev_t device, + unsigned int user_data); + +/***************************************************************************** + * + * API function prototypes + * + ****************************************************************************/ +extern int ep93xx_dma_request(int * handle, const char *device_id, + ep93xx_dma_dev_t device); +extern int ep93xx_dma_free(int handle); +extern int ep93xx_dma_config(int handle, unsigned int flags_m2p, + unsigned int flags_m2m, + dma_callback callback, unsigned int user_data); +extern int ep93xx_dma_add_buffer(int handle, unsigned int source, + unsigned int dest, unsigned int size, + unsigned int last, unsigned int buf_id); +extern int ep93xx_dma_remove_buffer(int handle, unsigned int * buf_id); +extern int ep93xx_dma_start(int handle, unsigned int channels, + unsigned int * handles); +extern int ep93xx_dma_pause(int handle, unsigned int channels, + unsigned int * handles); +extern int ep93xx_dma_flush(int handle); +extern int ep93xx_dma_queue_full(int handle); +extern int ep93xx_dma_get_position(int handle, unsigned int * buf_id, + unsigned int * total, unsigned int * current_frac); +extern int ep93xx_dma_get_total(int handle); +extern int ep93xx_dma_is_done(int handle); + +#endif /* _ASM_ARCH_DMA_H */ + diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/ep93xx-regs.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/ep93xx-regs.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/ep93xx-regs.h 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/ep93xx-regs.h 2008-08-18 14:05:42.000000000 -0500 @@ -15,17 +15,913 @@ */ #define EP93XX_AHB_PHYS_BASE 0x80000000 -#define EP93XX_AHB_VIRT_BASE 0xfef00000 +#define EP93XX_AHB_VIRT_BASE 0xff000000//0xfef00000 #define EP93XX_AHB_SIZE 0x00100000 + #define EP93XX_APB_PHYS_BASE 0x80800000 -#define EP93XX_APB_VIRT_BASE 0xfed00000 +#define EP93XX_APB_VIRT_BASE 0xff800000//0xfed00000 #define EP93XX_APB_SIZE 0x00200000 -/* AHB peripherals */ +#define IO_BASE_PHYS EP93XX_AHB_PHYS_BASE +#define IO_BASE_VIRT EP93XX_AHB_VIRT_BASE +/* + * We don't map the PCMCIA initially. The PCMCIA driver will use ioremap + * to be able to see it. But besides that PCMCIA will not exist in the + * memory map. + */ +#define PCMCIA_BASE_VIRT 0xD0000000 // Virtual address of PCMCIA +#define PCMCIA_BASE_PHYS 0x40000000 // Physical address of PCMCIA +#define PCMCIA_SIZE 0x10000000 // How much? + + + +/* + * We don't map the PCMCIA initially. The PCMCIA driver will use ioremap + * to be able to see it. But besides that PCMCIA will not exist in the */ +/* SMC register map */ +/* Address Read Location Write Location */ +/* 0x8000.2000 SMCBCR0(Bank config register 0) SMCBCR0(Bank config register 0) */ +/* 0x8000.2004 SMCBCR1(Bank config register 1) SMCBCR1(Bank config register 1) */ +/* 0x8000.2008 SMCBCR2(Bank config register 2) SMCBCR2(Bank config register 2) */ +/* 0x8000.200C SMCBCR3(Bank config register 3) SMCBCR3(Bank config register 3) */ +/* 0x8000.2010 Reserved, RAZ Reserved, RAZ */ +/* 0x8000.2014 Reserved, RAZ Reserved, RAZ */ +/* 0x8000.2018 SMCBCR6(Bank config register 6) SMCBCR6(Bank config register 6) */ +/* 0x8000.201C SMCBCR7(Bank config register 7) SMCBCR7(Bank config register 7) */ +/* 0x8000.2020 PCAttribute Register PCAttribute Register */ +/* 0x8000.2024 PCCommon Register PCCommon Register */ +/* 0x8000.2028 PCIO Register PCIO Register */ +/* 0x8000.202C Reserved, RAZ Reserved, RAZ */ +/* 0x8000.2030 Reserved, RAZ Reserved, RAZ */ +/* 0x8000.2034 Reserved, RAZ Reserved, RAZ */ +/* 0x8000.2038 Reserved, RAZ Reserved, RAZ */ +/* 0x8000.203C Reserved, RAZ Reserved, RAZ */ +/* 0x8000.2040 PCMCIACtrl Register PCMCIACtrl Register */ + +#define SRAM_OFFSET 0x080000 +#define SRAM_BASE (EP93XX_AHB_VIRT_BASE|SRAM_OFFSET) +#define SMCBCR0 (SRAM_BASE+0x00) /* 0x8000.2000 Bank config register 0 */ +#define SMCBCR1 (SRAM_BASE+0x04) /* 0x8000.2004 Bank config register 1 */ +#define SMCBCR2 (SRAM_BASE+0x08) /* 0x8000.2008 Bank config register 2 */ +#define SMCBCR3 (SRAM_BASE+0x0C) /* 0x8000.200C Bank config register 3 */ + /* 0x8000.2010 Reserved, RAZ */ + /* 0x8000.2014 Reserved, RAZ */ +#define SMCBCR6 (SRAM_BASE+0x18) /* 0x8000.2018 Bank config register 6 */ +#define SMCBCR7 (SRAM_BASE+0x1C) /* 0x8000.201C Bank config register 7 */ + +#define SMC_PCAttribute (SRAM_BASE+0x20) /* 0x8000.2020 PCMCIA Attribute Register */ +#define SMC_PCCommon (SRAM_BASE+0x24) /* 0x8000.2024 PCMCIA Common Register */ +#define SMC_PCIO (SRAM_BASE+0x28) /* 0x8000.2028 PCMCIA IO Register */ + /* 0x8000.202C Reserved, RAZ */ + /* 0x8000.2030 Reserved, RAZ */ + /* 0x8000.2034 Reserved, RAZ */ + /* 0x8000.2038 Reserved, RAZ */ + /* 0x8000.203C Reserved, RAZ */ +#define SMC_PCMCIACtrl (SRAM_BASE+0x40) /* 0x8000.2040 PCMCIA control register */ + + + + #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) +// +/* 8000_0000 - 8000_ffff: DMA */ +#define DMA_OFFSET 0x000000 +#define DMA_BASE (EP93XX_DMA_BASE) +#define DMAMP_TX_0_CONTROL (DMA_BASE+0x0000) +#define DMAMP_TX_0_INTERRUPT (DMA_BASE+0x0004) +#define DMAMP_TX_0_PPALLOC (DMA_BASE+0x0008) +#define DMAMP_TX_0_STATUS (DMA_BASE+0x000C) +#define DMAMP_TX_0_REMAIN (DMA_BASE+0x0014) +#define DMAMP_TX_0_MAXCNT0 (DMA_BASE+0x0020) +#define DMAMP_TX_0_BASE0 (DMA_BASE+0x0024) +#define DMAMP_TX_0_CURRENT0 (DMA_BASE+0x0028) +#define DMAMP_TX_0_MAXCNT1 (DMA_BASE+0x0030) +#define DMAMP_TX_0_BASE1 (DMA_BASE+0x0034) +#define DMAMP_TX_0_CURRENT1 (DMA_BASE+0x0038) + +#define DMAMP_RX_1_CONTROL (DMA_BASE+0x0040) +#define DMAMP_RX_1_INTERRUPT (DMA_BASE+0x0044) +#define DMAMP_RX_1_PPALLOC (DMA_BASE+0x0048) +#define DMAMP_RX_1_STATUS (DMA_BASE+0x004C) +#define DMAMP_RX_1_REMAIN (DMA_BASE+0x0054) +#define DMAMP_RX_1_MAXCNT0 (DMA_BASE+0x0060) +#define DMAMP_RX_1_BASE0 (DMA_BASE+0x0064) +#define DMAMP_RX_1_CURRENT0 (DMA_BASE+0x0068) +#define DMAMP_RX_1_MAXCNT1 (DMA_BASE+0x0070) +#define DMAMP_RX_1_BASE1 (DMA_BASE+0x0074) +#define DMAMP_RX_1_CURRENT1 (DMA_BASE+0x0078) + +#define DMAMP_TX_2_CONTROL (DMA_BASE+0x0080) +#define DMAMP_TX_2_INTERRUPT (DMA_BASE+0x0084) +#define DMAMP_TX_2_PPALLOC (DMA_BASE+0x0088) +#define DMAMP_TX_2_STATUS (DMA_BASE+0x008C) +#define DMAMP_TX_2_REMAIN (DMA_BASE+0x0094) +#define DMAMP_TX_2_MAXCNT0 (DMA_BASE+0x00A0) +#define DMAMP_TX_2_BASE0 (DMA_BASE+0x00A4) +#define DMAMP_TX_2_CURRENT0 (DMA_BASE+0x00A8) +#define DMAMP_TX_2_MAXCNT1 (DMA_BASE+0x00B0) +#define DMAMP_TX_2_BASE1 (DMA_BASE+0x00B4) +#define DMAMP_TX_2_CURRENT1 (DMA_BASE+0x00B8) + +#define DMAMP_RX_3_CONTROL (DMA_BASE+0x00C0) +#define DMAMP_RX_3_INTERRUPT (DMA_BASE+0x00C4) +#define DMAMP_RX_3_PPALLOC (DMA_BASE+0x00C8) +#define DMAMP_RX_3_STATUS (DMA_BASE+0x00CC) +#define DMAMP_RX_3_REMAIN (DMA_BASE+0x00D4) +#define DMAMP_RX_3_MAXCNT0 (DMA_BASE+0x00E0) +#define DMAMP_RX_3_BASE0 (DMA_BASE+0x00E4) +#define DMAMP_RX_3_CURRENT0 (DMA_BASE+0x00E8) +#define DMAMP_RX_3_MAXCNT1 (DMA_BASE+0x00F0) +#define DMAMP_RX_3_BASE1 (DMA_BASE+0x00F4) +#define DMAMP_RX_3_CURRENT1 (DMA_BASE+0x00F8) + +#define DMAMM_0_CONTROL (DMA_BASE+0x0100) +#define DMAMM_0_INTERRUPT (DMA_BASE+0x0104) +#define DMAMM_0_STATUS (DMA_BASE+0x010C) +#define DMAMM_0_BCR0 (DMA_BASE+0x0110) +#define DMAMM_0_BCR1 (DMA_BASE+0x0114) +#define DMAMM_0_SAR_BASE0 (DMA_BASE+0x0118) +#define DMAMM_0_SAR_BASE1 (DMA_BASE+0x011C) +#define DMAMM_0_SAR_CURRENT0 (DMA_BASE+0x0124) +#define DMAMM_0_SAR_CURRENT1 (DMA_BASE+0x0128) +#define DMAMM_0_DAR_BASE0 (DMA_BASE+0x012C) +#define DMAMM_0_DAR_BASE1 (DMA_BASE+0x0130) +#define DMAMM_0_DAR_CURRENT0 (DMA_BASE+0x0134) +#define DMAMM_0_DAR_CURRENT1 (DMA_BASE+0x013C) + +#define DMAMM_1_CONTROL (DMA_BASE+0x0140) +#define DMAMM_1_INTERRUPT (DMA_BASE+0x0144) +#define DMAMM_1_STATUS (DMA_BASE+0x014C) +#define DMAMM_1_BCR0 (DMA_BASE+0x0150) +#define DMAMM_1_BCR1 (DMA_BASE+0x0154) +#define DMAMM_1_SAR_BASE0 (DMA_BASE+0x0158) +#define DMAMM_1_SAR_BASE1 (DMA_BASE+0x015C) +#define DMAMM_1_SAR_CURRENT0 (DMA_BASE+0x0164) +#define DMAMM_1_SAR_CURRENT1 (DMA_BASE+0x0168) +#define DMAMM_1_DAR_BASE0 (DMA_BASE+0x016C) +#define DMAMM_1_DAR_BASE1 (DMA_BASE+0x0170) +#define DMAMM_1_DAR_CURRENT0 (DMA_BASE+0x0174) +#define DMAMM_1_DAR_CURRENT1 (DMA_BASE+0x017C) + +#define DMAMP_RX_5_CONTROL (DMA_BASE+0x0200) +#define DMAMP_RX_5_INTERRUPT (DMA_BASE+0x0204) +#define DMAMP_RX_5_PPALLOC (DMA_BASE+0x0208) +#define DMAMP_RX_5_STATUS (DMA_BASE+0x020C) +#define DMAMP_RX_5_REMAIN (DMA_BASE+0x0214) +#define DMAMP_RX_5_MAXCNT0 (DMA_BASE+0x0220) +#define DMAMP_RX_5_BASE0 (DMA_BASE+0x0224) +#define DMAMP_RX_5_CURRENT0 (DMA_BASE+0x0228) +#define DMAMP_RX_5_MAXCNT1 (DMA_BASE+0x0230) +#define DMAMP_RX_5_BASE1 (DMA_BASE+0x0234) +#define DMAMP_RX_5_CURRENT1 (DMA_BASE+0x0238) + +#define DMAMP_TX_4_CONTROL (DMA_BASE+0x0240) +#define DMAMP_TX_4_INTERRUPT (DMA_BASE+0x0244) +#define DMAMP_TX_4_PPALLOC (DMA_BASE+0x0248) +#define DMAMP_TX_4_STATUS (DMA_BASE+0x024C) +#define DMAMP_TX_4_REMAIN (DMA_BASE+0x0254) +#define DMAMP_TX_4_MAXCNT0 (DMA_BASE+0x0260) +#define DMAMP_TX_4_BASE0 (DMA_BASE+0x0264) +#define DMAMP_TX_4_CURRENT0 (DMA_BASE+0x0268) +#define DMAMP_TX_4_MAXCNT1 (DMA_BASE+0x0270) +#define DMAMP_TX_4_BASE1 (DMA_BASE+0x0274) +#define DMAMP_TX_4_CURRENT1 (DMA_BASE+0x0278) + +#define DMAMP_RX_7_CONTROL (DMA_BASE+0x0280) +#define DMAMP_RX_7_INTERRUPT (DMA_BASE+0x0284) +#define DMAMP_RX_7_PPALLOC (DMA_BASE+0x0288) +#define DMAMP_RX_7_STATUS (DMA_BASE+0x028C) +#define DMAMP_RX_7_REMAIN (DMA_BASE+0x0294) +#define DMAMP_RX_7_MAXCNT0 (DMA_BASE+0x02A0) +#define DMAMP_RX_7_BASE0 (DMA_BASE+0x02A4) +#define DMAMP_RX_7_CURRENT0 (DMA_BASE+0x02A8) +#define DMAMP_RX_7_MAXCNT1 (DMA_BASE+0x02B0) +#define DMAMP_RX_7_BASE1 (DMA_BASE+0x02B4) +#define DMAMP_RX_7_CURRENT1 (DMA_BASE+0x02B8) + +#define DMAMP_TX_6_CONTROL (DMA_BASE+0x02C0) +#define DMAMP_TX_6_INTERRUPT (DMA_BASE+0x02C4) +#define DMAMP_TX_6_PPALLOC (DMA_BASE+0x02C8) +#define DMAMP_TX_6_STATUS (DMA_BASE+0x02CC) +#define DMAMP_TX_6_REMAIN (DMA_BASE+0x02D4) +#define DMAMP_TX_6_MAXCNT0 (DMA_BASE+0x02E0) +#define DMAMP_TX_6_BASE0 (DMA_BASE+0x02E4) +#define DMAMP_TX_6_CURRENT0 (DMA_BASE+0x02E8) +#define DMAMP_TX_6_MAXCNT1 (DMA_BASE+0x02F0) +#define DMAMP_TX_6_BASE1 (DMA_BASE+0x02F4) +#define DMAMP_TX_6_CURRENT1 (DMA_BASE+0x02F8) + +#define DMAMP_RX_9_CONTROL (DMA_BASE+0x0300) +#define DMAMP_RX_9_INTERRUPT (DMA_BASE+0x0304) +#define DMAMP_RX_9_PPALLOC (DMA_BASE+0x0308) +#define DMAMP_RX_9_STATUS (DMA_BASE+0x030C) +#define DMAMP_RX_9_REMAIN (DMA_BASE+0x0314) +#define DMAMP_RX_9_MAXCNT0 (DMA_BASE+0x0320) +#define DMAMP_RX_9_BASE0 (DMA_BASE+0x0324) +#define DMAMP_RX_9_CURRENT0 (DMA_BASE+0x0328) +#define DMAMP_RX_9_MAXCNT1 (DMA_BASE+0x0330) +#define DMAMP_RX_9_BASE1 (DMA_BASE+0x0334) +#define DMAMP_RX_9_CURRENT1 (DMA_BASE+0x0338) + +#define DMAMP_TX_8_CONTROL (DMA_BASE+0x0340) +#define DMAMP_TX_8_INTERRUPT (DMA_BASE+0x0344) +#define DMAMP_TX_8_PPALLOC (DMA_BASE+0x0348) +#define DMAMP_TX_8_STATUS (DMA_BASE+0x034C) +#define DMAMP_TX_8_REMAIN (DMA_BASE+0x0354) +#define DMAMP_TX_8_MAXCNT0 (DMA_BASE+0x0360) +#define DMAMP_TX_8_BASE0 (DMA_BASE+0x0364) +#define DMAMP_TX_8_CURRENT0 (DMA_BASE+0x0368) +#define DMAMP_TX_8_MAXCNT1 (DMA_BASE+0x0370) +#define DMAMP_TX_8_BASE1 (DMA_BASE+0x0374) +#define DMAMP_TX_8_CURRENT1 (DMA_BASE+0x0378) + +#define DMA_ARBITRATION (DMA_BASE+0x0380) +#define DMA_INTERRUPT (DMA_BASE+0x03C0) + + +/* + * DMA Register Base addresses and Offsets + */ +#define DMA_M2P_TX_0_BASE DMAMP_TX_0_CONTROL +#define DMA_M2P_RX_1_BASE DMAMP_RX_1_CONTROL +#define DMA_M2P_TX_2_BASE DMAMP_TX_2_CONTROL +#define DMA_M2P_RX_3_BASE DMAMP_RX_3_CONTROL +#define DMA_M2M_0_BASE DMAMM_0_CONTROL +#define DMA_M2M_1_BASE DMAMM_1_CONTROL +#define DMA_M2P_RX_5_BASE DMAMP_RX_5_CONTROL +#define DMA_M2P_TX_4_BASE DMAMP_TX_4_CONTROL +#define DMA_M2P_RX_7_BASE DMAMP_RX_7_CONTROL +#define DMA_M2P_TX_6_BASE DMAMP_TX_6_CONTROL +#define DMA_M2P_RX_9_BASE DMAMP_RX_9_CONTROL +#define DMA_M2P_TX_8_BASE DMAMP_TX_8_CONTROL + +#define M2P_OFFSET_CONTROL 0x0000 +#define M2P_OFFSET_INTERRUPT 0x0004 +#define M2P_OFFSET_PPALLOC 0x0008 +#define M2P_OFFSET_STATUS 0x000C +#define M2P_OFFSET_REMAIN 0x0014 +#define M2P_OFFSET_MAXCNT0 0x0020 +#define M2P_OFFSET_BASE0 0x0024 +#define M2P_OFFSET_CURRENT0 0x0028 +#define M2P_OFFSET_MAXCNT1 0x0030 +#define M2P_OFFSET_BASE1 0x0034 +#define M2P_OFFSET_CURRENT1 0x0038 + +#define M2M_OFFSET_CONTROL 0x0000 +#define M2M_OFFSET_INTERRUPT 0x0004 +#define M2M_OFFSET_STATUS 0x000C +#define M2M_OFFSET_BCR0 0x0010 +#define M2M_OFFSET_BCR1 0x0014 +#define M2M_OFFSET_SAR_BASE0 0x0018 +#define M2M_OFFSET_SAR_BASE1 0x001C +#define M2M_OFFSET_SAR_CURRENT0 0x0024 +#define M2M_OFFSET_SAR_CURRENT1 0x0028 +#define M2M_OFFSET_DAR_BASE0 0x002C +#define M2M_OFFSET_DAR_BASE1 0x0030 +#define M2M_OFFSET_DAR_CURRENT0 0x0034 +#define M2M_OFFSET_DAR_CURRENT1 0x003C + + + +/* 8003_0000 - 8003_ffff: Raster */ +#define RASTER_OFFSET 0x030000 +#define RASTER_BASE (EP93XX_AHB_VIRT_BASE|RASTER_OFFSET) +#define VLINESTOTAL (RASTER_BASE+0x00) +#define VSYNCSTRTSTOP (RASTER_BASE+0x04) +#define VACTIVESTRTSTOP (RASTER_BASE+0x08) +#define VCLKSTRTSTOP (RASTER_BASE+0x0C) +#define HCLKSTOTAL (RASTER_BASE+0x10) +#define HSYNCSTRTSTOP (RASTER_BASE+0x14) +#define HACTIVESTRTSTOP (RASTER_BASE+0x18) +#define HCLKSTRTSTOP (RASTER_BASE+0x1C) +#define BRIGHTNESS (RASTER_BASE+0x20) +#define VIDEOATTRIBS (RASTER_BASE+0x24) +#define VIDSCRNPAGE (RASTER_BASE+0x28) +#define VIDSCRNHPG (RASTER_BASE+0x2C) +#define SCRNLINES (RASTER_BASE+0x30) +#define LINELENGTH (RASTER_BASE+0x34) +#define VLINESTEP (RASTER_BASE+0x38) +#define LINECARRY (RASTER_BASE+0x3C) +#define BLINKRATE (RASTER_BASE+0x40) +#define BLINKMASK (RASTER_BASE+0x44) +#define BLINKPATTRN (RASTER_BASE+0x48) +#define PATTRNMASK (RASTER_BASE+0x4C) +#define BG_OFFSET (RASTER_BASE+0x50) +#define PIXELMODE (RASTER_BASE+0x54) +#define PARLLIFOUT (RASTER_BASE+0x58) +#define PARLLIFIN (RASTER_BASE+0x5C) +#define CURSOR_ADR_START (RASTER_BASE+0x60) +#define CURSOR_ADR_RESET (RASTER_BASE+0x64) +#define CURSORSIZE (RASTER_BASE+0x68) +#define CURSORCOLOR1 (RASTER_BASE+0x6C) +#define CURSORCOLOR2 (RASTER_BASE+0x70) +#define CURSORXYLOC (RASTER_BASE+0x74) +#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78) +#define RASTER_SWLOCK (RASTER_BASE+0x7C) +#define GS_LUT (RASTER_BASE+0x80) +#define RASTER_TCR (RASTER_BASE+0x100) +#define RASTER_TISRA (RASTER_BASE+0x104) +#define RASTER_TISRB (RASTER_BASE+0x108) +#define CURSOR_TISR (RASTER_BASE+0x10C) +#define RASTER_TOCRA (RASTER_BASE+0x110) +#define RASTER_TOCRB (RASTER_BASE+0x114) +#define FIFO_TOCRA (RASTER_BASE+0x118) +#define FIFO_TOCRB (RASTER_BASE+0x11C) +#define BLINK_TISR (RASTER_BASE+0x120) +#define DAC_TISRA (RASTER_BASE+0x124) +#define DAC_TISRB (RASTER_BASE+0x128) +#define SHIFT_TISR (RASTER_BASE+0x12C) +#define DACMUX_TOCRA (RASTER_BASE+0x130) +#define DACMUX_TOCRB (RASTER_BASE+0x134) +#define PELMUX_TOCR (RASTER_BASE+0x138) +#define VIDEO_TOCRA (RASTER_BASE+0x13C) +#define VIDEO_TOCRB (RASTER_BASE+0x140) +#define YCRCB_TOCR (RASTER_BASE+0x144) +#define CURSOR_TOCR (RASTER_BASE+0x148) +#define VIDEO_TOCRC (RASTER_BASE+0x14C) +#define SHIFT_TOCR (RASTER_BASE+0x150) +#define BLINK_TOCR (RASTER_BASE+0x154) +#define RASTER_TCER (RASTER_BASE+0x180) +#define SIGVAL (RASTER_BASE+0x200) +#define SIGCTL (RASTER_BASE+0x204) +#define VSIGSTRTSTOP (RASTER_BASE+0x208) +#define HSIGSTRTSTOP (RASTER_BASE+0x20C) +#define SIGCLR (RASTER_BASE+0x210) +#define ACRATE (RASTER_BASE+0x214) +#define LUTCONT (RASTER_BASE+0x218) +#define VBLANKSTRTSTOP (RASTER_BASE+0x228) +#define HBLANKSTRTSTOP (RASTER_BASE+0x22C) +#define LUT (RASTER_BASE+0x400) +#define CURSORBLINK1 (RASTER_BASE+0x21C) +#define CURSORBLINK2 (RASTER_BASE+0x220) +#define CURSORBLINK (RASTER_BASE+0x224) +#define EOLOFFSET (RASTER_BASE+0x230) +#define FIFOLEVEL (RASTER_BASE+0x234) +#define GS_LUT2 (RASTER_BASE+0x280) +#define GS_LUT3 (RASTER_BASE+0x300) +#define COLOR_LUT (RASTER_BASE+0x400) + +/* 8004_0000 - 8004_ffff: Graphics */ +#define GRAPHICS_OFFSET 0x040000 +#define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE|GRAPHICS_OFFSET) +#define SRCPIXELSTRT (GRAPHICS_BASE+0x00) +#define DESTPIXELSTRT (GRAPHICS_BASE+0x04) +#define BLKSRCSTRT (GRAPHICS_BASE+0x08) +#define BLKDSTSTRT (GRAPHICS_BASE+0x0C) +#define BLKSRCWIDTH (GRAPHICS_BASE+0x10) +#define SRCLINELENGTH (GRAPHICS_BASE+0x14) +#define BLKDESTWIDTH (GRAPHICS_BASE+0x18) +#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C) +#define DESTLINELENGTH (GRAPHICS_BASE+0x20) +#define BLOCKCTRL (GRAPHICS_BASE+0x24) +#define TRANSPATTRN (GRAPHICS_BASE+0x28) +#define BLOCKMASK (GRAPHICS_BASE+0x2C) +#define BACKGROUND (GRAPHICS_BASE+0x30) +#define LINEINC (GRAPHICS_BASE+0x34) +#define LINEINIT (GRAPHICS_BASE+0x38) +#define LINEPATTRN (GRAPHICS_BASE+0x3C) + + +/* 800B_0000 - 800B_FFFF: VIC 0 */ +#define VIC0_OFFSET 0x0B0000 +#define VIC0_BASE (EP93XX_AHB_VIRT_BASE|VIC0_OFFSET) +#define VIC0 (VIC0_BASE+0x000) +#define VIC0IRQSTATUS (VIC0_BASE+0x000) /* R IRQ status register */ +#define VIC0FIQSTATUS (VIC0_BASE+0x004) /* R FIQ status register */ +#define VIC0RAWINTR (VIC0_BASE+0x008) /* R Raw interrupt status register */ +#define VIC0INTSELECT (VIC0_BASE+0x00C) /* R/W Interrupt select register */ +#define VIC0INTENABLE (VIC0_BASE+0x010) /* R/W Interrupt enable register */ +#define VIC0INTENCLEAR (VIC0_BASE+0x014) /* W Interrupt enable clear register */ +#define VIC0SOFTINT (VIC0_BASE+0x018) /* R/W Software interrupt register */ +#define VIC0SOFTINTCLEAR (VIC0_BASE+0x01C) /* R/W Software interrupt clear register */ +#define VIC0PROTECTION (VIC0_BASE+0x020) /* R/W Protection enable register */ +#define VIC0VECTADDR (VIC0_BASE+0x030) /* R/W Vector address register */ +#define VIC0DEFVECTADDR (VIC0_BASE+0x034) /* R/W Default vector address register */ +#define VIC0VECTADDR00 (VIC0_BASE+0x100) /* R/W Vector address 00 register */ +#define VIC0VECTADDR01 (VIC0_BASE+0x104) /* R/W Vector address 01 register */ +#define VIC0VECTADDR02 (VIC0_BASE+0x108) /* R/W Vector address 02 register */ +#define VIC0VECTADDR03 (VIC0_BASE+0x10C) /* R/W Vector address 03 register */ +#define VIC0VECTADDR04 (VIC0_BASE+0x110) /* R/W Vector address 04 register */ +#define VIC0VECTADDR05 (VIC0_BASE+0x114) /* R/W Vector address 05 register */ +#define VIC0VECTADDR06 (VIC0_BASE+0x118) /* R/W Vector address 06 register */ +#define VIC0VECTADDR07 (VIC0_BASE+0x11C) /* R/W Vector address 07 register */ +#define VIC0VECTADDR08 (VIC0_BASE+0x120) /* R/W Vector address 08 register */ +#define VIC0VECTADDR09 (VIC0_BASE+0x124) /* R/W Vector address 09 register */ +#define VIC0VECTADDR10 (VIC0_BASE+0x128) /* R/W Vector address 10 register */ +#define VIC0VECTADDR11 (VIC0_BASE+0x12C) /* R/W Vector address 11 register */ +#define VIC0VECTADDR12 (VIC0_BASE+0x130) /* R/W Vector address 12 register */ +#define VIC0VECTADDR13 (VIC0_BASE+0x134) /* R/W Vector address 13 register */ +#define VIC0VECTADDR14 (VIC0_BASE+0x138) /* R/W Vector address 14 register */ +#define VIC0VECTADDR15 (VIC0_BASE+0x13C) /* R/W Vector address 15 register */ +#define VIC0VECTCNTL00 (VIC0_BASE+0x200) /* R/W Vector control 00 register */ +#define VIC0VECTCNTL01 (VIC0_BASE+0x204) /* R/W Vector control 01 register */ +#define VIC0VECTCNTL02 (VIC0_BASE+0x208) /* R/W Vector control 02 register */ +#define VIC0VECTCNTL03 (VIC0_BASE+0x20C) /* R/W Vector control 03 register */ +#define VIC0VECTCNTL04 (VIC0_BASE+0x210) /* R/W Vector control 04 register */ +#define VIC0VECTCNTL05 (VIC0_BASE+0x214) /* R/W Vector control 05 register */ +#define VIC0VECTCNTL06 (VIC0_BASE+0x218) /* R/W Vector control 06 register */ +#define VIC0VECTCNTL07 (VIC0_BASE+0x21C) /* R/W Vector control 07 register */ +#define VIC0VECTCNTL08 (VIC0_BASE+0x220) /* R/W Vector control 08 register */ +#define VIC0VECTCNTL09 (VIC0_BASE+0x224) /* R/W Vector control 09 register */ +#define VIC0VECTCNTL10 (VIC0_BASE+0x228) /* R/W Vector control 10 register */ +#define VIC0VECTCNTL11 (VIC0_BASE+0x22C) /* R/W Vector control 11 register */ +#define VIC0VECTCNTL12 (VIC0_BASE+0x230) /* R/W Vector control 12 register */ +#define VIC0VECTCNTL13 (VIC0_BASE+0x234) /* R/W Vector control 13 register */ +#define VIC0VECTCNTL14 (VIC0_BASE+0x238) /* R/W Vector control 14 register */ +#define VIC0VECTCNTL15 (VIC0_BASE+0x23C) /* R/W Vector control 15 register */ +#define VIC0ITCR (VIC0_BASE+0x300) /* R/W Test control register */ +#define VIC0ITIP1 (VIC0_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN)*/ +#define VIC0ITIP2 (VIC0_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ +#define VIC0ITOP1 (VIC0_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ +#define VIC0ITOP2 (VIC0_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ +#define VIC0PERIPHID0 (VIC0_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ +#define VIC0PERIPHID1 (VIC0_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ +#define VIC0PERIPHID2 (VIC0_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ +#define VIC0PERIPHID3 (VIC0_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ + + +/* 800C_0000 - 800C_FFFF: VIC 0 */ +#define VIC1_OFFSET 0x0C0000 +#define VIC1_BASE (EP93XX_AHB_VIRT_BASE|VIC1_OFFSET) +#define VIC1 (VIC1_BASE+0x000) +#define VIC1IRQSTATUS (VIC1_BASE+0x000) /* R IRQ status register */ +#define VIC1FIQSTATUS (VIC1_BASE+0x004) /* R FIQ status register */ +#define VIC1RAWINTR (VIC1_BASE+0x008) /* R Raw interrupt status register */ +#define VIC1INTSELECT (VIC1_BASE+0x00C) /* R/W Interrupt select register */ +#define VIC1INTENABLE (VIC1_BASE+0x010) /* R/W Interrupt enable register */ +#define VIC1INTENCLEAR (VIC1_BASE+0x014) /* W Interrupt enable clear register */ +#define VIC1SOFTINT (VIC1_BASE+0x018) /* R/W Software interrupt register */ +#define VIC1SOFTINTCLEAR (VIC1_BASE+0x01C) /* R/W Software interrupt clear register */ +#define VIC1PROTECTION (VIC1_BASE+0x020) /* R/W Protection enable register */ +#define VIC1VECTADDR (VIC1_BASE+0x030) /* R/W Vector address register */ +#define VIC1DEFVECTADDR (VIC1_BASE+0x034) /* R/W Default vector address register */ +#define VIC1VECTADDR00 (VIC1_BASE+0x100) /* R/W Vector address 00 register */ +#define VIC1VECTADDR01 (VIC1_BASE+0x104) /* R/W Vector address 01 register */ +#define VIC1VECTADDR02 (VIC1_BASE+0x108) /* R/W Vector address 02 register */ +#define VIC1VECTADDR03 (VIC1_BASE+0x10C) /* R/W Vector address 03 register */ +#define VIC1VECTADDR04 (VIC1_BASE+0x110) /* R/W Vector address 04 register */ +#define VIC1VECTADDR05 (VIC1_BASE+0x114) /* R/W Vector address 05 register */ +#define VIC1VECTADDR06 (VIC1_BASE+0x118) /* R/W Vector address 06 register */ +#define VIC1VECTADDR07 (VIC1_BASE+0x11C) /* R/W Vector address 07 register */ +#define VIC1VECTADDR08 (VIC1_BASE+0x120) /* R/W Vector address 08 register */ +#define VIC1VECTADDR09 (VIC1_BASE+0x124) /* R/W Vector address 09 register */ +#define VIC1VECTADDR10 (VIC1_BASE+0x128) /* R/W Vector address 10 register */ +#define VIC1VECTADDR11 (VIC1_BASE+0x12C) /* R/W Vector address 11 register */ +#define VIC1VECTADDR12 (VIC1_BASE+0x130) /* R/W Vector address 12 register */ +#define VIC1VECTADDR13 (VIC1_BASE+0x134) /* R/W Vector address 13 register */ +#define VIC1VECTADDR14 (VIC1_BASE+0x138) /* R/W Vector address 14 register */ +#define VIC1VECTADDR15 (VIC1_BASE+0x13C) /* R/W Vector address 15 register */ +#define VIC1VECTCNTL00 (VIC1_BASE+0x200) /* R/W Vector control 00 register */ +#define VIC1VECTCNTL01 (VIC1_BASE+0x204) /* R/W Vector control 01 register */ +#define VIC1VECTCNTL02 (VIC1_BASE+0x208) /* R/W Vector control 02 register */ +#define VIC1VECTCNTL03 (VIC1_BASE+0x20C) /* R/W Vector control 03 register */ +#define VIC1VECTCNTL04 (VIC1_BASE+0x210) /* R/W Vector control 04 register */ +#define VIC1VECTCNTL05 (VIC1_BASE+0x214) /* R/W Vector control 05 register */ +#define VIC1VECTCNTL06 (VIC1_BASE+0x218) /* R/W Vector control 06 register */ +#define VIC1VECTCNTL07 (VIC1_BASE+0x21C) /* R/W Vector control 07 register */ +#define VIC1VECTCNTL08 (VIC1_BASE+0x220) /* R/W Vector control 08 register */ +#define VIC1VECTCNTL09 (VIC1_BASE+0x224) /* R/W Vector control 09 register */ +#define VIC1VECTCNTL10 (VIC1_BASE+0x228) /* R/W Vector control 10 register */ +#define VIC1VECTCNTL11 (VIC1_BASE+0x22C) /* R/W Vector control 11 register */ +#define VIC1VECTCNTL12 (VIC1_BASE+0x230) /* R/W Vector control 12 register */ +#define VIC1VECTCNTL13 (VIC1_BASE+0x234) /* R/W Vector control 13 register */ +#define VIC1VECTCNTL14 (VIC1_BASE+0x238) /* R/W Vector control 14 register */ +#define VIC1VECTCNTL15 (VIC1_BASE+0x23C) /* R/W Vector control 15 register */ +#define VIC1ITCR (VIC1_BASE+0x300) /* R/W Test control register */ +#define VIC1ITIP1 (VIC1_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN)*/ +#define VIC1ITIP2 (VIC1_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ +#define VIC1ITOP1 (VIC1_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ +#define VIC1ITOP2 (VIC1_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ +#define VIC1PERIPHID0 (VIC1_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ +#define VIC1PERIPHID1 (VIC1_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ +#define VIC1PERIPHID2 (VIC1_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ +#define VIC1PERIPHID3 (VIC1_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ + + +/////////////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////APB///////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* 8081_0000 - 8081_ffff: Timers */ +#define TIMERS_OFFSET 0x010000 +#define TIMERS_BASE (EP93XX_APB_VIRT_BASE|TIMERS_OFFSET) + +#define TIMER1LOAD (TIMERS_BASE+0x00) +#define TIMER1VALUE (TIMERS_BASE+0x04) +#define TIMER1CONTROL (TIMERS_BASE+0x08) +#define TIMER1CLEAR (TIMERS_BASE+0x0C) +#define TIMER1TEST (TIMERS_BASE+0x10) + +#define TIMER2LOAD (TIMERS_BASE+0x20) +#define TIMER2VALUE (TIMERS_BASE+0x24) +#define TIMER2CONTROL (TIMERS_BASE+0x28) +#define TIMER2CLEAR (TIMERS_BASE+0x2C) +#define TIMER2TEST (TIMERS_BASE+0x30) + +#define TIMER3LOAD (TIMERS_BASE+0x80) +#define TIMER3VALUE (TIMERS_BASE+0x84) +#define TIMER3CONTROL (TIMERS_BASE+0x88) +#define TIMER3CLEAR (TIMERS_BASE+0x8C) +#define TIMER3TEST (TIMERS_BASE+0x90) + +#define TTIMERBZCONT (TIMERS_BASE+0x40) + +#define TIMER4VALUELOW (TIMERS_BASE+0x60) +#define TIMER4VALUEHIGH (TIMERS_BASE+0x64) + + +/* 8082_0000 - 8082_ffff: I2S */ +#define I2S_OFFSET 0x020000 +#define I2S_BASE (EP93XX_APB_VIRT_BASE|I2S_OFFSET) +#define I2S_PHYS_BASE (EP93XX_APB_PHYS_BASE + I2S_OFFSET) + + + +#define I2STxClkCfg (I2S_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */ +#define I2SRxClkCfg (I2S_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */ +#define I2SGlSts (I2S_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. */ +#define I2SGlCtrl (I2S_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */ + +#define I2STX0Lft (I2S_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */ +#define I2STX0Rt (I2S_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */ +#define I2STX1Lft (I2S_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */ +#define I2STX1Rt (I2S_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */ +#define I2STX2Lft (I2S_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */ +#define I2STX2Rt (I2S_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */ + +#define I2STXLinCtrlData (I2S_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */ +#define I2STXCtrl (I2S_BASE+0x2C) /* 8082.002C R/W TX Control register */ +#define I2STXWrdLen (I2S_BASE+0x30) /* 8082.0030 R/W TX Word Length */ +#define I2STX0En (I2S_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */ +#define I2STX1En (I2S_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */ +#define I2STX2En (I2S_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */ + +#define I2SRX0Lft (I2S_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */ +#define I2SRX0Rt (I2S_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */ +#define I2SRX1Lft (I2S_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */ +#define I2SRX1Rt (I2S_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */ +#define I2SRX2Lft (I2S_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */ +#define I2SRX2Rt (I2S_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */ + +#define I2SRXLinCtrlData (I2S_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */ +#define I2SRXCtrl (I2S_BASE+0x5C) /* 8082.005C R/W RX Control register */ +#define I2SRXWrdLen (I2S_BASE+0x60) /* 8082.0060 R/W RX Word Length */ +#define I2SRX0En (I2S_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */ +#define I2SRX1En (I2S_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */ +#define I2SRX2En (I2S_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable */ + + +#define EP93XX_GPIO_A_DDR (EP93XX_GPIO_REG(0x10)) +#define EP93XX_GPIO_A_DR (EP93XX_GPIO_REG(0x00)) + +#define EP93XX_GPIO_B_DDR (EP93XX_GPIO_REG(0x14)) +#define EP93XX_GPIO_B_DR (EP93XX_GPIO_REG(0x04)) + +#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) +#define EP93XX_SPI_BASE_PHYS (EP93XX_APB_PHYS_BASE + 0x000a0000) +#define EP93XX_SPI_REG(x) (EP93XX_SPI_BASE + (x)) +#define EP93XX_SPI_CR0 (EP93XX_SPI_REG(0)) +#define EP93XX_SPI_CR1 (EP93XX_SPI_REG(4)) +#define EP93XX_SPI_DR (EP93XX_SPI_REG(8)) +#define EP93XX_SPI_SR (EP93XX_SPI_REG(0x0C)) +#define EP93XX_SPI_CPSR (EP93XX_SPI_REG(0x10)) +#define EP93XX_SPI_IIR (EP93XX_SPI_REG(0x14)) +#define EP93XX_SPI_FIFO_SIZE (8) + +/* 8084_0000 - 8084_ffff: GPIO */ +#define GPIO_OFFSET 0x040000 +#define GPIO_BASE (EP93XX_APB_VIRT_BASE|GPIO_OFFSET) +#define GPIO_PADR (GPIO_BASE+0x00) +#define GPIO_PBDR (GPIO_BASE+0x04) +#define GPIO_PCDR (GPIO_BASE+0x08) +#define GPIO_PDDR (GPIO_BASE+0x0C) +#define GPIO_PADDR (GPIO_BASE+0x10) +#define GPIO_PBDDR (GPIO_BASE+0x14) +#define GPIO_PCDDR (GPIO_BASE+0x18) +#define GPIO_PDDDR (GPIO_BASE+0x1C) +#define GPIO_PEDR (GPIO_BASE+0x20) +#define GPIO_PEDDR (GPIO_BASE+0x24) +// #define 0x8084.0028 Reserved +// #define 0x8084.002C Reserved +#define GPIO_PFDR (GPIO_BASE+0x30) +#define GPIO_PFDDR (GPIO_BASE+0x34) +#define GPIO_PGDR (GPIO_BASE+0x38) +#define GPIO_PGDDR (GPIO_BASE+0x3C) +#define GPIO_PHDR (GPIO_BASE+0x40) +#define GPIO_PHDDR (GPIO_BASE+0x44) +// #define 0x8084.0048 RAZ RAZ +#define GPIO_FINTTYPE1 (GPIO_BASE+0x4C) +#define GPIO_FINTTYPE2 (GPIO_BASE+0x50) +#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_FINTEN (GPIO_BASE+0x58) +#define GPIO_INTSTATUSF (GPIO_BASE+0x5C) +#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60) +#define GPIO_FDB (GPIO_BASE+0x64) +#define GPIO_PAPINDR (GPIO_BASE+0x68) +#define GPIO_PBPINDR (GPIO_BASE+0x6C) +#define GPIO_PCPINDR (GPIO_BASE+0x70) +#define GPIO_PDPINDR (GPIO_BASE+0x74) +#define GPIO_PEPINDR (GPIO_BASE+0x78) +#define GPIO_PFPINDR (GPIO_BASE+0x7C) +#define GPIO_PGPINDR (GPIO_BASE+0x80) +#define GPIO_PHPINDR (GPIO_BASE+0x84) +#define GPIO_AINTTYPE1 (GPIO_BASE+0x90) +#define GPIO_AINTTYPE2 (GPIO_BASE+0x94) +#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_AINTEN (GPIO_BASE+0x9C) +#define GPIO_INTSTATUSA (GPIO_BASE+0xA0) +#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4) +#define GPIO_ADB (GPIO_BASE+0xA8) +#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC) +#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0) +#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_BINTEN (GPIO_BASE+0xB8) +#define GPIO_INTSTATUSB (GPIO_BASE+0xBC) +#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0) +#define GPIO_BDB (GPIO_BASE+0xC4) +#define GPIO_EEDRIVE (GPIO_BASE+0xC8) +//#define Reserved (GPIO_BASE+0xCC) +#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */ +#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */ +#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */ +#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */ +#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */ +#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */ +#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */ +#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */ +#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */ +#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */ + + +/* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */ +#define AC97_OFFSET 0x080000 +#define AC97_BASE (EP93XX_APB_VIRT_BASE|AC97_OFFSET) +#define EP93XX_AC97_PHY_BASE (EP93XX_APB_PHYS_BASE|AC97_OFFSET) +#define AC97DR1 (AC97_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */ +#define AC97RXCR1 (AC97_BASE+0x04) /* 8088.0004 R/W Control register for receive */ +#define AC97TXCR1 (AC97_BASE+0x08) /* 8088.0008 R/W Control register for transmit */ +#define AC97SR1 (AC97_BASE+0x0C) /* 8088.000C R Status register */ +#define AC97RISR1 (AC97_BASE+0x10) /* 8088.0010 R Raw interrupt status register */ +#define AC97ISR1 (AC97_BASE+0x14) /* 8088.0014 R Interrupt Status */ +#define AC97IE1 (AC97_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */ + /* 8088.001C Reserved - RAZ */ +#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ +#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */ +#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ +#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */ +#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ +#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */ +#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ + /* 8088.003C Reserved - RAZ */ +#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ +#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */ +#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ +#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */ +#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ +#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */ +#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ + /* 8088.005C Reserved - RAZ */ +#define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ +#define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */ +#define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ +#define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */ +#define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ +#define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */ +#define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ + /* 8088.003C Reserved - RAZ */ +#define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ +#define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */ +#define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ +#define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */ +#define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ +#define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */ +#define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ + /* 8088.005C Reserved - RAZ */ +#define AC97DR4 (AC97_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */ +#define AC97RXCR4 (AC97_BASE+0x64) /* 8088.0064 R/W Control register for receive */ +#define AC97TXCR4 (AC97_BASE+0x68) /* 8088.0068 R/W Control register for transmit */ +#define AC97SR4 (AC97_BASE+0x6C) /* 8088.006C R Status register */ +#define AC97RISR4 (AC97_BASE+0x70) /* 8088.0070 R Raw interrupt status register */ +#define AC97ISR4 (AC97_BASE+0x74) /* 8088.0074 R Interrupt Status */ +#define AC97IE4 (AC97_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */ + /* 8088.007C Reserved - RAZ */ +#define AC97S1DATA (AC97_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */ +#define AC97S2DATA (AC97_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */ +#define AC97S12DATA (AC97_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */ +#define AC97RGIS (AC97_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register*/ +#define AC97GIS (AC97_BASE+0x90) /* 8088.0090 R Global interrupt status register */ +#define AC97IM (AC97_BASE+0x94) /* 8088.0094 R/W Interrupt mask register */ +#define AC97EOI (AC97_BASE+0x98) /* 8088.0098 W Interrupt clear register */ +#define AC97GCR (AC97_BASE+0x9C) /* 8088.009C R/W Main Control register */ +#define AC97RESET (AC97_BASE+0xA0) /* 8088.00A0 R/W RESET control register. */ +#define AC97SYNC (AC97_BASE+0xA4) /* 8088.00A4 R/W SYNC control register. */ +#define AC97GCIS (AC97_BASE+0xA8) /* 8088.00A8 R Global chan FIFO int status register */ + + +/* 808A_0000 - 808A_ffff: SSP - (SPI) */ +#define SSP_OFFSET 0x0A0000 +#define SSP_BASE (EP93XX_APB_VIRT_BASE|SSP_OFFSET) +#define SSPCR0 (SSP_BASE+0x00) +#define SSPCR1 (SSP_BASE+0x04) +#define SSPDR (SSP_BASE+0x08) +#define SSPSR (SSP_BASE+0x0c) +#define SSPCPSR (SSP_BASE+0x10) +#define SSPIIR (SSP_BASE+0x14) + + +/*808B_0000 - 808B_ffff: IrDA */ +#define IRDA_OFFSET 0x0B0000 +#define IRDA_BASE (EP93XX_APB_VIRT_BASE|IRDA_OFFSET) +#define IrEnable (IRDA_BASE+0x00) +#define IrCtrl (IRDA_BASE+0x04) +#define IrAdrMatchVal (IRDA_BASE+0x08) +#define IrFlag (IRDA_BASE+0x0C) +#define IrData (IRDA_BASE+0x10) +#define IrDataTail1 (IRDA_BASE+0x14) +#define IrDataTail2 (IRDA_BASE+0x18) +#define IrDataTail3 (IRDA_BASE+0x1c) +#define IrRIB (IRDA_BASE+0x20) +#define IrTR0 (IRDA_BASE+0x24) +#define IrDMACR (IRDA_BASE+0x28) +#define SIRTR0 (IRDA_BASE+0x30) +#define MISR (IRDA_BASE+0x80) +#define MIMR (IRDA_BASE+0x84) +#define MIIR (IRDA_BASE+0x88) +#define FISR (IRDA_BASE+0x180) +#define FIMR (IRDA_BASE+0x184) +#define FIIR (IRDA_BASE+0x188) + + +/* 808C_0000 - 808C_ffff: UART1 */ +#define UART1_OFFSET 0x0C0000 +#define UART1_BASE (EP93XX_APB_VIRT_BASE|UART1_OFFSET) +#define UART1_BASE_VIRT (EP93XX_APB_PHYS_BASE|UART1_OFFSET) +#define UART1DR (UART1_BASE+0x000) +#define UART1RSR (UART1_BASE+0x004) +#define UART1ECR (UART1_BASE+0x004) +#define UART1CR_H (UART1_BASE+0x008) +#define UART1CR_M (UART1_BASE+0x00C) +#define UART1CR_L (UART1_BASE+0x010) +#define UART1CR (UART1_BASE+0x014) +#define UART1FR (UART1_BASE+0x018) +#define UART1IIR (UART1_BASE+0x01C) +#define UART1ICR (UART1_BASE+0x01C) +#define UART1ILPR (UART1_BASE+0x020) +#define UART1DMACR (UART1_BASE+0x028) +#define UART1TMR (UART1_BASE+0x084) +#define UART1MCR (UART1_BASE+0x100) +#define UART1MSR (UART1_BASE+0x104) +#define UART1TCR (UART1_BASE+0x108) +#define UART1TISR (UART1_BASE+0x10C) +#define UART1TOCR (UART1_BASE+0x110) +#define HDLC1CR (UART1_BASE+0x20c) +#define HDLC1AMV (UART1_BASE+0x210) +#define HDLC1AMSK (UART1_BASE+0x214) +#define HDLC1RIB (UART1_BASE+0x218) +#define HDLC1SR (UART1_BASE+0x21c) + +/* Offsets to the various UART registers */ +#define UARTDR 0x0000 +#define UARTRSR 0x0004 +#define UARTECR 0x0004 +#define UARTCR_H 0x0008 +#define UARTCR_M 0x000C +#define UARTCR_L 0x0010 +#define UARTCR 0x0014 +#define UARTFR 0x0018 +#define UARTIIR 0x001C +#define UARTICR 0x001C +#define UARTMCR 0x0100 +#define UARTMSR 0x0104 + +/* 808d_0000 - 808d_ffff: UART2 */ +#define UART2_OFFSET 0x0D0000 +#define UART2_BASE (EP93XX_APB_VIRT_BASE|UART2_OFFSET) +#define UART2_BASE_VIRT (EP93XX_APB_PHYS_BASE|UART2_OFFSET) +#define UART2DR (UART2_BASE+0x00) +#define UART2RSR (UART2_BASE+0x04) /* Read */ +#define UART2ECR (UART2_BASE+0x04) /* Write */ +#define UART2CR_H (UART2_BASE+0x08) +#define UART2CR_M (UART2_BASE+0x0C) +#define UART2CR_L (UART2_BASE+0x10) +#define UART2CR (UART2_BASE+0x14) +#define UART2FR (UART2_BASE+0x18) +#define UART2IIR (UART2_BASE+0x1C) /* Read */ +#define UART2ICR (UART2_BASE+0x1C) /* Write */ +#define UART2ILPR (UART2_BASE+0x20) +#define UART2DMACR (UART2_BASE+0x28) +#define UART2TMR (UART2_BASE+0x84) + + +/* 808e_0000 - 808e_ffff: UART3 */ +#define UART3_OFFSET 0x0E0000 +#define UART3_BASE (EP93XX_APB_VIRT_BASE|UART3_OFFSET) +#define UART3_BASE_VIRT (EP93XX_APB_PHYS_BASE|UART3_OFFSET) +#define UART3DR (UART3_BASE+0x00) +#define UART3RSR (UART3_BASE+0x04) /* Read */ +#define UART3ECR (UART3_BASE+0x04) /* Write */ +#define UART3CR_H (UART3_BASE+0x08) +#define UART3CR_M (UART3_BASE+0x0C) +#define UART3CR_L (UART3_BASE+0x10) +#define UART3CR (UART3_BASE+0x14) +#define UART3FR (UART3_BASE+0x18) +#define UART3IIR (UART3_BASE+0x1C) /* Read */ +#define UART3ICR (UART3_BASE+0x1C) /* Write */ +#define UART3ILPR (UART3_BASE+0x20) +#define UART3DMACR (UART3_BASE+0x28) +#define UART3TCR (UART3_BASE+0x80) +#define UART3TISR (UART3_BASE+0x88) +#define UART3TOCR (UART3_BASE+0x8C) +#define UART3TMR (UART3_BASE+0x84) +#define UART3MCR (UART3_BASE+0x100) /* Modem Control Reg */ +#define UART3MSR (UART3_BASE+0x104) /* Modem Status Reg */ + +#define UART3HDLCCR (UART3_BASE+0x20C) /* HDLC Registers */ +#define UART3HDLCAMV (UART3_BASE+0x210) /* HDLC Registers */ +#define UART3HDLCAMSK (UART3_BASE+0x214) /* HDLC Registers */ +#define UART3HDLCCRIB (UART3_BASE+0x218) /* HDLC Registers */ +#define UART3HDLCSR (UART3_BASE+0x21C) /* HDLC Registers */ + +/* 808f_0000 - 808f_ffff: KEY Matrix */ +#define KEY_OFFSET 0x0F0000 +#define KEY_BASE (EP93XX_APB_VIRT_BASE|KEY_OFFSET) +#define SCANINIT (KEY_BASE+0x00) +#define KEY_DIAG (KEY_BASE+0x04) +#define KEY_REG (KEY_BASE+0x08) +#define KEY_TCR (KEY_BASE+0x10) +#define KEY_TISR (KEY_BASE+0x14) +#define KEY_TOCR (KEY_BASE+0x18) + + +#define TOUCH_OFFSET 0x100000 +#define TOUCH_BASE (EP93XX_APB_VIRT_BASE|TOUCH_OFFSET) +#define TSSetup (TOUCH_BASE+0x00) /* R/W touchscreen controller setup control register. */ +#define TSXYMaxMin (TOUCH_BASE+0x04) /* R/W touchscreen controller max/min register. */ +#define TSXYResult (TOUCH_BASE+0x08) /* R touchscreen controller result register. */ +#define TSDischarge (TOUCH_BASE+0x0C) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSXSample (TOUCH_BASE+0x10) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSYSample (TOUCH_BASE+0x14) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSDirect (TOUCH_BASE+0x18) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSDetect (TOUCH_BASE+0x1C) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSSWLock (TOUCH_BASE+0x20) /* NA R/W touchscreen software lock register. */ +#define TSSetup2 (TOUCH_BASE+0x24) /* R/W touchscreen setup control register #2. */ + + +/* 8093_0000 - 8093_ffff: CSC/Syscon PLL, clock control, & misc. stuff */ +#define SYSCON_OFFSET 0x130000 +#define SYSCON_BASE ((EP93XX_APB_VIRT_BASE)|SYSCON_OFFSET) +#define SYSCON_PWRSR (SYSCON_BASE+0x0000) +#define SYSCON_PWRCNT (SYSCON_BASE+0x0004) +#define SYSCON_HALT (SYSCON_BASE+0x0008) +#define SYSCON_STBY (SYSCON_BASE+0x000c) +#define SYSCON_BLEOI (SYSCON_BASE+0x0010) +#define SYSCON_MCEOI (SYSCON_BASE+0x0014) +#define SYSCON_TEOI (SYSCON_BASE+0x0018) +#define SYSCON_STFCLR (SYSCON_BASE+0x001c) +#define SYSCON_CLKSET1 (SYSCON_BASE+0x0020) +#define SYSCON_CLKSET2 (SYSCON_BASE+0x0024) +#define SYSCON_RESV00 (SYSCON_BASE+0x0028) +#define SYSCON_RESV01 (SYSCON_BASE+0x002c) +#define SYSCON_RESV02 (SYSCON_BASE+0x0030) +#define SYSCON_RESV03 (SYSCON_BASE+0x0034) +#define SYSCON_RESV04 (SYSCON_BASE+0x0038) +#define SYSCON_RESV05 (SYSCON_BASE+0x003c) +#define SYSCON_SCRREG0 (SYSCON_BASE+0x0040) +#define SYSCON_SCRREG1 (SYSCON_BASE+0x0044) +#define SYSCON_CLKTEST (SYSCON_BASE+0x0048) +#define SYSCON_USBRESET (SYSCON_BASE+0x004c) +#define SYSCON_APBWAIT (SYSCON_BASE+0x0050) +#define SYSCON_BMAR (SYSCON_BASE+0x0054) +#define SYSCON_BOOTCLR (SYSCON_BASE+0x0058) +#define SYSCON_DEVCFG (SYSCON_BASE+0x0080) +#define SYSCON_VIDDIV (SYSCON_BASE+0x0084) +#define SYSCON_MIRDIV (SYSCON_BASE+0x0088) +#define SYSCON_I2SDIV (SYSCON_BASE+0x008C) +#define SYSCON_KTDIV (SYSCON_BASE+0x0090) +#define SYSCON_CHIPID (SYSCON_BASE+0x0094) +#define SYSCON_TSTCR (SYSCON_BASE+0x0098) +#define SYSCON_SYSCFG (SYSCON_BASE+0x009C) +#define SYSCON_SWLOCK (SYSCON_BASE+0x00C0) + +#define SYSCON_DEVCFG_KEYS 0x00000002 +#define SYSCON_DEVCFG_RasOnP3 0x00000010 +#define SYSCON_DEVCFG_GONK 0x08000000 + +#define SYSCON_KTDIV_KEN 0x00008000 + + + + + + + + + + + +// #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) @@ -33,8 +929,11 @@ #define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) #define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) +#define EP93XX_RASTER_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00030000) #define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) +#define EP93XX_GRAPHICS_ACCEL_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00040000 + #define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) @@ -43,7 +942,141 @@ #define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) #define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) +#define EP93XX_IDE_REG(x) (EP93XX_IDE_BASE + (x)) +#define EP93XX_IDE_CTRL EP93XX_IDE_REG(0x0000) +#define EP93XX_IDE_CFG EP93XX_IDE_REG(0x0004) +#define EP93XX_IDE_DATAOUT EP93XX_IDE_REG(0x0010) +#define EP93XX_IDE_DATAIN EP93XX_IDE_REG(0x0014) + +#define EP93XX_IDE_CTRL_CS0n (1L << 0) +#define EP93XX_IDE_CTRL_CS1n (1L << 1) +#define EP93XX_IDE_CTRL_DA_MASK 0x1C +#define EP93XX_IDE_CTRL_DA(x) ((x << 2) & EP93XX_IDE_CTRL_DA_MASK) +#define EP93XX_IDE_CTRL_DA_CS_MASK (EP93XX_IDE_CTRL_DA_MASK | EP93XX_IDE_CTRL_CS0n | EP93XX_IDE_CTRL_CS1n) +#define EP93XX_IDE_CTRL_DA_CS(x) (((x)) & EP93XX_IDE_CTRL_DA_CS_MASK) +#define EP93XX_IDE_CTRL_DIORn (1L << 5) +#define EP93XX_IDE_CTRL_DIOWn (1L << 6) +#define EP93XX_IDE_CTRL_DASPn (1L << 7) +#define EP93XX_IDE_CTRL_DMARQ (1L << 8) +#define EP93XX_IDE_CTRL_INTRQ (1L << 9) +#define EP93XX_IDE_CTRL_IORDY (1L << 10) + +#define EP93XX_IDE_CFG_IDEEN (1L << 0) +#define EP93XX_IDE_CFG_PIO (1L << 1) +#define EP93XX_IDE_CFG_MDMA (1L << 2) +#define EP93XX_IDE_CFG_UDMA (1L << 3) +#define EP93XX_IDE_CFG_MODE(x) ((x & 0x0F) << 4) +#define EP93XX_IDE_CFG_WST(x) ((x & 0x03) << 8) + + + +/* Olde IDE DMA defines */ +/* 800A_0000 - 800A_ffff: IDE Interface */ +#define IDE_OFFSET 0x0a0000 +#define IDE_BASE (EP93XX_AHB_VIRT_BASE|IDE_OFFSET) +#define IDECR (IDE_BASE+0x00) +#define IDECFG (IDE_BASE+0x04) +#define IDEMDMAOP (IDE_BASE+0x08) +#define IDEUDMAOP (IDE_BASE+0x0C) +#define IDEDATAOUT (IDE_BASE+0x10) +#define IDEDATAIN (IDE_BASE+0x14) +#define IDEMDMADATAOUT (IDE_BASE+0x18) +#define IDEMDMADATAIN (IDE_BASE+0x1C) +#define IDEUDMADATAOUT (IDE_BASE+0x20) +#define IDEUDMADATAIN (IDE_BASE+0x24) +#define IDEUDMASTATUS (IDE_BASE+0x28) +#define IDEUDMADEBUG (IDE_BASE+0x2C) +#define IDEUDMAWFST (IDE_BASE+0x30) +#define IDEUDMARFST (IDE_BASE+0x34) + +/***************************************************************************** + * + * Bit definitions for use with assembly code for the ide control register. + * + ****************************************************************************/ +#define IDECtrl_CS0n 0x00000001 +#define IDECtrl_CS1n 0x00000002 +#define IDECtrl_DA_MASK 0x0000001c +#define IDECtrl_DA_SHIFT 2 +#define IDECtrl_DIORn 0x00000020 +#define IDECtrl_DIOWn 0x00000040 +#define IDECtrl_DASPn 0x00000080 +#define IDECtrl_DMARQ 0x00000100 +#define IDECtrl_INTRQ 0x00000200 +#define IDECtrl_IORDY 0x00000400 + +#define IDECfg_IDEEN 0x00000001 +#define IDECfg_PIO 0x00000002 +#define IDECfg_MDMA 0x00000004 +#define IDECfg_UDMA 0x00000008 +#define IDECfg_MODE_MASK 0x000000f0 +#define IDECfg_MODE_SHIFT 4 +#define IDECfg_WST_MASK 0x00000300 +#define IDECfg_WST_SHIFT 8 + +#define IDEMDMAOp_MEN 0x00000001 +#define IDEMDMAOp_RWOP 0x00000002 + +#define IDEUDMAOp_UEN 0x00000001 +#define IDEUDMAOp_RWOP 0x00000002 + +#define IDEUDMASts_CS0n 0x00000001 +#define IDEUDMASts_CS1n 0x00000002 +#define IDEUDMASts_DA_MASK 0x0000001c +#define IDEUDMASts_DA_SHIFT 2 +#define IDEUDMASts_HSHD 0x00000020 +#define IDEUDMASts_STOP 0x00000040 +#define IDEUDMASts_DM 0x00000080 +#define IDEUDMASts_DDOE 0x00000100 +#define IDEUDMASts_DMARQ 0x00000200 +#define IDEUDMASts_DSDD 0x00000400 +#define IDEUDMASts_DMAide 0x00010000 +#define IDEUDMASts_INTide 0x00020000 +#define IDEUDMASts_SBUSY 0x00040000 +#define IDEUDMASts_NDO 0x01000000 +#define IDEUDMASts_NDI 0x02000000 +#define IDEUDMASts_N4X 0x04000000 + +#define IDEUDMADebug_RWOE 0x00000001 +#define IDEUDMADebug_RWPTR 0x00000002 +#define IDEUDMADebug_RWDR 0x00000004 +#define IDEUDMADebug_RROE 0x00000008 +#define IDEUDMADebug_RRPTR 0x00000010 +#define IDEUDMADebug_RRDR 0x00000020 + +#define IDEUDMAWrBufSts_HPTR_MASK 0x0000000f +#define IDEUDMAWrBufSts_HPTR_SHIFT 0 +#define IDEUDMAWrBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMAWrBufSts_TPTR_SHIFT 4 +#define IDEUDMAWrBufSts_EMPTY 0x00000100 +#define IDEUDMAWrBufSts_HOM 0x00000200 +#define IDEUDMAWrBufSts_NFULL 0x00000400 +#define IDEUDMAWrBufSts_FULL 0x00000800 +#define IDEUDMAWrBufSts_CRC_MASK 0xffff0000 +#define IDEUDMAWrBufSts_CRC_SHIFT 16 + +#define IDEUDMARdBufSts_HPTR_MASK 0x0000000f +#define IDEUDMARdBufSts_HPTR_SHIFT 0 +#define IDEUDMARdBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMARdBufSts_TPTR_SHIFT 4 +#define IDEUDMARdBufSts_EMPTY 0x00000100 +#define IDEUDMARdBufSts_HOM 0x00000200 +#define IDEUDMARdBufSts_NFULL 0x00000400 +#define IDEUDMARdBufSts_FULL 0x00000800 +#define IDEUDMARdBufSts_CRC_MASK 0xffff0000 +#define IDEUDMARdBufSts_CRC_SHIFT 16 + + + + + + + + + + +/*----------------------------------old-------------------------------*/ #define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) #define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) @@ -73,21 +1106,26 @@ #define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) -#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) -#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) -#define EP93XX_GPIO_F_INT_ACK EP93XX_GPIO_REG(0x54) -#define EP93XX_GPIO_F_INT_ENABLE EP93XX_GPIO_REG(0x58) -#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) #define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90) #define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94) #define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) #define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c) #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_A_INT_DEBOUNCE EP93XX_GPIO_REG(0xa8) #define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac) #define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0) #define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4) #define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) +#define EP93XX_GPIO_B_INT_DEBOUNCE EP93XX_GPIO_REG(0xc4) + +#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) +#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) +#define EP93XX_GPIO_F_INT_ACK EP93XX_GPIO_REG(0x54) +#define EP93XX_GPIO_F_INT_ENABLE EP93XX_GPIO_REG(0x58) +#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) + +/*-------------------------------------------------------------------------------*/ #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) @@ -121,10 +1159,15 @@ #define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) +#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) +#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 + +#define EP93XX_SYSCON_BMAR EP93XX_SYSCON_REG(0x54) +#define EP93XX_SYSCON_CHIPID EP93XX_SYSCON_REG(0x94) #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/ep93xx_util.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/ep93xx_util.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/ep93xx_util.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/ep93xx_util.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,15 @@ +#ifndef EP93XX_UTIL_H_ +#define EP93XX_UTIL_H_ + +#define KEY (0xAA) + +static inline void EP93XX_SYSUNLOCK(void){ + iowrite32(KEY,(void *)EP93XX_SYSCON_SWLOCK); +} + +static inline void EP93XX_DEVCFG_WRITE(u32 x) { + EP93XX_SYSUNLOCK(); + iowrite32(x,(void *)EP93XX_SYSCON_DEVICE_CONFIG); +} + +#endif /*EP93XX_UTIL_H_*/ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/gpio.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/gpio.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/gpio.h 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/gpio.h 2008-08-18 14:05:42.000000000 -0500 @@ -5,6 +5,16 @@ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H +#define GPIO_IN 0 +#define GPIO_OUT 1 + +#define EP93XX_GPIO_LOW 0 +#define EP93XX_GPIO_HIGH 1 + +extern void gpio_line_config(int line, int direction); +extern int gpio_line_get(int line); +extern void gpio_line_set(int line, int value); + /* GPIO port A. */ #define EP93XX_GPIO_LINE_A(x) ((x) + 0) #define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/hardware.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/hardware.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/hardware.h 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/hardware.h 2008-08-18 14:05:42.000000000 -0500 @@ -3,6 +3,17 @@ */ #include "ep93xx-regs.h" +#include "regs_touch.h" +#include "regs_syscon.h" +#include "regs_raster.h" + +#include "regs_irda.h" +#include "regs_ide.h" +#include "regs_dma.h" +#include "regs_ac97.h" +#include "regs_uart.h" +#include "regs_smc.h" +#include "regs_spi.h" #define pcibios_assign_all_busses() 0 @@ -10,3 +21,8 @@ #include "gesbc9312.h" #include "ts72xx.h" + +#ifndef MSECS_TO_JIFFIES +#define MSECS_TO_JIFFIES(ms) (((ms)*HZ+999)/1000) +#endif + diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/irqs.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/irqs.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/irqs.h 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/irqs.h 2008-08-18 14:05:42.000000000 -0500 @@ -34,6 +34,7 @@ #define IRQ_EP93XX_UART3TX 28 #define IRQ_EP93XX_KEY 29 #define IRQ_EP93XX_TOUCH 30 +#define IRQ_EP93XX_GRAPHICS 31 #define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc #define IRQ_EP93XX_EXT0 32 @@ -67,6 +68,12 @@ #define IRQ_EP93XX_SAI 60 #define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff +/* + * Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and + * F0..F7 to 80..87. + */ +#define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f)) + #define NR_EP93XX_IRQS (64 + 24) #define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/memory.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/memory.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/memory.h 2008-04-16 21:49:44.000000000 -0500 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/memory.h 2008-08-18 14:05:42.000000000 -0500 @@ -5,7 +5,9 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H +#ifndef CONFIG_RUNTIME_PHYS_OFFSET #define PHYS_OFFSET UL(0x00000000) +#endif #define __bus_to_virt(x) __phys_to_virt(x) #define __virt_to_bus(x) __virt_to_phys(x) diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_ac97.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_ac97.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_ac97.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_ac97.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,180 @@ +/*============================================================================= + * FILE: regs_ac97.h + * + * DESCRIPTION: Ac'97 Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + *============================================================================= + */ +#ifndef _REGS_AC97_H_ +#define _REGS_AC97_H_ + +//----------------------------------------------------------------------------- +// Bit definitionses +//----------------------------------------------------------------------------- +#define AC97ISR_RIS 8 +#define AC97ISR_TIS 4 +#define AC97ISR_RTIS 2 +#define AC97ISR_TCIS 1 + +#define AC97RGIS_SLOT1TXCOMPLETE 0x01 +#define AC97RGIS_SLOT2RXVALID 0x02 +#define AC97RGIS_GPIOTXCOMPLETE 0x04 +#define AC97RGIS_GPIOINTRX 0x08 +#define AC97RGIS_RWIS 0x10 +#define AC97RGIS_CODECREADY 0x20 +#define AC97RGIS_SLOT2TXCOMPLETE 0x40 + +#define AC97SR_RXFE 0x0001 +#define AC97SR_TXFE 0x0002 +#define AC97SR_RXFF 0x0004 +#define AC97SR_TXFF 0x0008 +#define AC97SR_TXBUSY 0x0010 +#define AC97SR_RXOE 0x0020 +#define AC97SR_TXUE 0x0040 + +#define AC97GSR_IFE 0x1 +#define AC97GSR_LOOP 0x2 +#define AC97GSR_OVERRIDECODECREADY 0x4 + +#define AC97RESET_TIMEDRESET 0x1 +#define AC97RESET_FORCEDRESET 0x2 +#define AC97RESET_EFORCER 0x4 + +#define AC97RXCR_REN 0x1 + +#define AC97TXCR_TEN 0x1 + + +//**************************************************************************** +// +// The Ac97 Codec registers, accessable through the Ac-link. +// These are not controller registers and are not memory mapped. +// Includes registers specific to CS4202 (Beavis). +// +//**************************************************************************** +#define AC97_REG_OFFSET_MASK 0x0000007E + +#define AC97_00_RESET 0x00000000 +#define AC97_02_MASTER_VOL 0x00000002 +#define AC97_04_HEADPHONE_VOL 0x00000004 +#define AC97_06_MONO_VOL 0x00000006 +#define AC97_08_TONE 0x00000008 +#define AC97_0A_PC_BEEP_VOL 0x0000000A +#define AC97_0C_PHONE_VOL 0x0000000C +#define AC97_0E_MIC_VOL 0x0000000E +#define AC97_10_LINE_IN_VOL 0x00000010 +#define AC97_12_CD_VOL 0x00000012 +#define AC97_14_VIDEO_VOL 0x00000014 +#define AC97_16_AUX_VOL 0x00000016 +#define AC97_18_PCM_OUT_VOL 0x00000018 +#define AC97_1A_RECORD_SELECT 0x0000001A +#define AC97_1C_RECORD_GAIN 0x0000001C +#define AC97_1E_RESERVED_1E 0x0000001E +#define AC97_20_GENERAL_PURPOSE 0x00000020 +#define AC97_22_3D_CONTROL 0x00000022 +#define AC97_24_MODEM_RATE 0x00000024 +#define AC97_26_POWERDOWN 0x00000026 +#define AC97_28_EXT_AUDIO_ID 0x00000028 +#define AC97_2A_EXT_AUDIO_POWER 0x0000002A +#define AC97_2C_PCM_FRONT_DAC_RATE 0x0000002C +#define AC97_2E_PCM_SURR_DAC_RATE 0x0000002E +#define AC97_30_PCM_LFE_DAC_RATE 0x00000030 +#define AC97_32_PCM_LR_ADC_RATE 0x00000032 +#define AC97_34_MIC_ADC_RATE 0x00000034 +#define AC97_36_6CH_VOL_C_LFE 0x00000036 +#define AC97_38_6CH_VOL_SURROUND 0x00000038 +#define AC97_3A_SPDIF_CONTROL 0x0000003A +#define AC97_3C_EXT_MODEM_ID 0x0000003C +#define AC97_3E_EXT_MODEM_POWER 0x0000003E +#define AC97_40_LINE1_CODEC_RATE 0x00000040 +#define AC97_42_LINE2_CODEC_RATE 0x00000042 +#define AC97_44_HANDSET_CODEC_RATE 0x00000044 +#define AC97_46_LINE1_CODEC_LEVEL 0x00000046 +#define AC97_48_LINE2_CODEC_LEVEL 0x00000048 +#define AC97_4A_HANDSET_CODEC_LEVEL 0x0000004A +#define AC97_4C_GPIO_PIN_CONFIG 0x0000004C +#define AC97_4E_GPIO_PIN_TYPE 0x0000004E +#define AC97_50_GPIO_PIN_STICKY 0x00000050 +#define AC97_52_GPIO_PIN_WAKEUP 0x00000052 +#define AC97_54_GPIO_PIN_STATUS 0x00000054 +#define AC97_56_RESERVED 0x00000056 +#define AC97_58_RESERVED 0x00000058 +#define AC97_5A_CRYSTAL_REV_N_FAB_ID 0x0000005A +#define AC97_5C_TEST_AND_MISC_CTRL 0x0000005C +#define AC97_5E_AC_MODE 0x0000005E +#define AC97_60_MISC_CRYSTAL_CONTROL 0x00000060 +#define AC97_62_VENDOR_RESERVED 0x00000062 +#define AC97_64_DAC_SRC_PHASE_INCR 0x00000064 +#define AC97_66_ADC_SRC_PHASE_INCR 0x00000066 +#define AC97_68_RESERVED_68 0x00000068 +#define AC97_6A_SERIAL_PORT_CONTROL 0x0000006A +#define AC97_6C_VENDOR_RESERVED 0x0000006C +#define AC97_6E_VENDOR_RESERVED 0x0000006E +#define AC97_70_BDI_CONFIG 0x00000070 +#define AC97_72_BDI_WAKEUP 0x00000072 +#define AC97_74_VENDOR_RESERVED 0x00000074 +#define AC97_76_CAL_ADDRESS 0x00000076 +#define AC97_78_CAL_DATA 0x00000078 +#define AC97_7A_VENDOR_RESERVED 0x0000007A +#define AC97_7C_VENDOR_ID1 0x0000007C +#define AC97_7E_VENDOR_ID2 0x0000007E + + +#ifndef __ASSEMBLY__ + +// +// enum type for use with reg AC97_RECORD_SELECT +// +typedef enum{ + RECORD_MIC = 0x0000, + RECORD_CD = 0x0101, + RECORD_VIDEO_IN = 0x0202, + RECORD_AUX_IN = 0x0303, + RECORD_LINE_IN = 0x0404, + RECORD_STEREO_MIX = 0x0505, + RECORD_MONO_MIX = 0x0606, + RECORD_PHONE_IN = 0x0707 +} Ac97RecordSources; + +#endif /* __ASSEMBLY__ */ + +// +// Sample rates supported directly in AC97_PCM_FRONT_DAC_RATE and +// AC97_PCM_LR_ADC_RATE. +// +#define Ac97_Fs_8000 0x1f40 +#define Ac97_Fs_11025 0x2b11 +#define Ac97_Fs_16000 0x3e80 +#define Ac97_Fs_22050 0x5622 +#define Ac97_Fs_32000 0x7d00 +#define Ac97_Fs_44100 0xac44 +#define Ac97_Fs_48000 0xbb80 + +// +// RSIZE and TSIZE in AC97RXCR and AC97TXCR +// +#define Ac97_SIZE_20 2 +#define Ac97_SIZE_18 1 +#define Ac97_SIZE_16 0 +#define Ac97_SIZE_12 3 + +//============================================================================= +//============================================================================= + + +#endif /* _REGS_AC97_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_dma.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_dma.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_dma.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_dma.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,276 @@ +/***************************************************************************** + * + * linux/include/asm-arm/arch-ep93xx/regs_dma.h + * + * Register definitions for the ep93xx dma channel registers. + * + * Copyright (C) 2003 Cirrus Logic + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + ****************************************************************************/ +#ifndef _REGS_DMA_H_ +#define _REGS_DMA_H_ + +/***************************************************************************** + * 0x8000.0000 -> 0x8000.003C M2P Channel 0 Registers (Tx) + * 0x8000.0040 -> 0x8000.007C M2P Channel 1 Registers (Rx) + * 0x8000.0080 -> 0x8000.00BC M2P Channel 2 Registers (Tx) + * 0x8000.00C0 -> 0x8000.00FC M2P Channel 3 Registers (Rx) + * 0x8000.0100 -> 0x8000.013C M2M Channel 0 Registers + * 0x8000.0140 -> 0x8000.017C M2M Channel 1 Registers + * 0x8000.0180 -> 0x8000.01BC Not Used + * 0x8000.01C0 -> 0x8000.01FC Not Used + * 0x8000.0200 -> 0x8000.023C M2P Channel 5 Registers (Rx) + * 0x8000.0240 -> 0x8000.027C M2P Channel 4 Registers (Tx) + * 0x8000.0280 -> 0x8000.02BC M2P Channel 7 Registers (Rx) + * 0x8000.02C0 -> 0x8000.02FC M2P Channel 6 Registers (Tx) + * 0x8000.0300 -> 0x8000.033C M2P Channel 9 Registers (Rx) + * 0x8000.0340 -> 0x8000.037C M2P Channel 8 Registers (Tx) + * 0x8000.0380 DMA Channel Arbitration register + * 0x8000.03C0 DMA Global Interrupt register + * 0x8000.03C4 -> 0x8000.03FC Not Used + * + * + * Internal M2P/P2M Channel Register Map + * + * Offset Name Access Bits Reset Value + * 0x00 CONTROL R/W 6 0 + * 0x04 INTERRUPT R/W TC* 3 0 + * 0x08 PPALLOC R/W 4 channel dependant + * (see reg description) + * 0x0C STATUS RO 8 0 + * 0x10 reserved + * 0x14 REMAIN RO 16 0 + * 0X18 Reserved + * 0X1C Reserved + * 0x20 MAXCNT0 R/W 16 0 + * 0x24 BASE0 R/W 32 0 + * 0x28 CURRENT0 RO 32 0 + * 0x2C Reserved + * 0x30 MAXCNT1 R/W 16 0 + * 0x34 BASE1 R/W 32 0 + * 0X38 CURRENT1 RO 32 0 + * 0X3C Reserved + * + * M2M Channel Register Map + * Offset Name Access Bits Reset Value + * + * 0x00 CONTROL R/W 22 0 + * 0x04 INTERRUPT R/W TC* 3 0 + * 0x08 Reserved + * 0x0C STATUS R/W TC* 14 0 + * 0x10 BCR0 R/W 16 0 + * 0x14 BCR1 R/W 16 0 + * 0x18 SAR_BASE0 R/W 32 0 + * 0x1C SAR_BASE1 R/W 32 0 + * 0x20 Reserved + * 0x24 SAR_CURRENT0 RO 32 0 + * 0x28 SAR_CURRENT1 RO 32 0 + * 0x2C DAR_BASE0 R/W 32 0 + * 0x30 DAR_BASE1 R/W 32 0 + * 0x34 DAR_CURRENT0 RO 32 0 + * 0X38 Reserved + * 0X3C DAR_CURRENT1 RO 32 0 + * * Write this location once to clear the bit (see + * Interrupt/Status register description for which bits + * this rule applies to). + * + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +/* + * DMA Register Base addresses + */ +static unsigned int const DMAM2PChannelBase[10] = +{ + DMA_M2P_TX_0_BASE, + DMA_M2P_RX_1_BASE, + DMA_M2P_TX_2_BASE, + DMA_M2P_RX_3_BASE, + DMA_M2P_TX_4_BASE, + DMA_M2P_RX_5_BASE, + DMA_M2P_TX_6_BASE, + DMA_M2P_RX_7_BASE, + DMA_M2P_TX_8_BASE, + DMA_M2P_RX_9_BASE +}; + +static unsigned int const DMAM2MChannelBase[2] = +{ + DMA_M2M_0_BASE, + DMA_M2M_1_BASE +}; + +#endif /* __ASSEMBLY__ */ + +/*----------------------------------------------------------------------------------*/ +/* M2P Registers */ +/*----------------------------------------------------------------------------------*/ +/* + * M2P CONTROL register bit defines + */ +#define CONTROL_M2P_STALLINTEN 0x00000001 /* Enables the STALL interrupt */ +#define CONTROL_M2P_NFBINTEN 0x00000002 /* Enables the NFB interrupt */ +#define CONTROL_M2P_CHERRORINTEN 0x00000008 /* Enables the ChError interrupt*/ +#define CONTROL_M2P_ENABLE 0x00000010 /* Enables the channel */ +#define CONTROL_M2P_ABRT 0x00000020 /* Determines how DMA behaves in*/ + /* NEXT state with peripheral */ + /* error */ + /* 0: NEXT -> ON, ignore error */ + /* 1: NEXT -> STALL, disable ch.*/ +#define CONTROL_M2P_ICE 0x00000040 /* Ignore Channel Error */ + +/* + * M2P INTERRUPT register bit defines + */ +#define INTERRUPT_M2P_STALLINT 0x00000001 /* Indicates channel stalled. */ +#define INTERRUPT_M2P_NFBINT 0x00000002 /* Indicates channel is hungry. */ +#define INTERRUPT_M2P_CHERRORINT 0x00000008 /* Peripheral detects error */ + + +/* + * STATUS register bit defines + */ +#define STATUS_M2P_STALL 0x00000001 /* A '1' indicates channel is */ + /* stalled */ +#define STATUS_M2P_NFB 0x00000002 /* A '1' indicates channel has moved*/ + /* from NEXT state to ON state, but */ + /* waiting for next buffer to be */ + /* programmed. */ +#define STATUS_M2P_CHERROR 0x00000008 /* Enables the ChError interrupt */ +#define STATUS_M2P_CURRENT_MASK 0x00000030 /* Current state of the FSM */ +#define STATUS_M2P_CURRENT_SHIFT 4 +#define STATUS_M2P_NEXTBUFFER 0x00000040 /* Informs the int handler after an */ + /* NFB int which pair of maxcnt and */ + /* base regs to update. */ +#define STATUS_M2P_BYTES_MASK 0x0000f800 /* number of valid DMA data */ +#define STATUS_M2P_BYTES_SHIFT 7 /* currently in */ + /* packer/unpacker */ + +#define STATUS_M2P_DMA_NO_BUF 0x00000000 +#define STATUS_M2P_DMA_BUF_ON 0x00000010 +#define STATUS_M2P_DMA_BUF_NEXT 0x00000020 + +/* + * Register masks to mask off reserved bits after reading register. + */ +#define M2P_MASK_PPALLOC 0x0000000f +#define M2P_MASK_REMAIN 0x0000ffff +#define M2P_MASK_MAXCNT0 0x0000ffff +#define M2P_MASK_BASE0 0xffffffff +#define M2P_MASK_CURRENT0 0xffffffff +#define M2P_MASK_MAXCNT1 0x0000ffff +#define M2P_MASK_BASE1 0xffffffff +#define M2P_MASK_CURRENT1 0xffffffff + + +/*----------------------------------------------------------------------------------*/ +/* M2M Registers */ +/*----------------------------------------------------------------------------------*/ + +#define CONTROL_M2M_STALLINTEN 0x00000001 /* Enables the STALL interrupt */ +#define CONTROL_M2M_SCT 0x00000002 /* Source Copy Transfer. Setup a */ + /* block transfer from 1 memory source */ + /* location. */ +#define CONTROL_M2M_DONEINTEN 0x00000004 /* Enables the DONE interrupt which */ + /* indicates if the xfer completed */ + /* successfully */ +#define CONTROL_M2M_ENABLE 0x00000008 /* Enables the channel */ +#define CONTROL_M2M_START 0x00000010 /* Initiates the xfer. 'software trigger' */ +#define CONTROL_M2M_BWC_MASK 0x000001e0 /* Bandwidth control. Indicate number of */ +#define CONTROL_M2M_BWC_SHIFT 5 /* bytes in a transfer. */ +#define CONTROL_M2M_PW_MASK 0x00000600 /* Peripheral width. Used for xfers */ +#define CONTROL_M2M_PW_SHIFT 9 /* between memory and external peripheral. */ + /* 00: byte, 01: halfword, 10: word. */ +#define CONTROL_M2M_DAH 0x00000800 /* Destination Address Hold */ +#define CONTROL_M2M_SAH 0x00001000 /* Source Address Hold */ +#define CONTROL_M2M_TM_MASK 0x00006000 /* Transfer Mode. 00: sw triggered, */ +#define CONTROL_M2M_TM_SHIFT 13 /* 01: hw initiated M2P, 01: hw initiated P2M */ +#define CONTROL_M2M_ETDP_MASK 0x00018000 /* End-of-Transfer/Terminal Count pin */ +#define CONTROL_M2M_ETDP_SHIFT 15 /* direction and polarity. */ +#define CONTROL_M2M_DACKP 0x00020000 /* DMA acknowledge pin polarity */ + +#define CONTROL_M2M_DREQP_MASK 0x00180000 /* DMA request pin polarity. must be set */ +#define CONTROL_M2M_DREQP_SHIFT 19 /* before enable bit. */ +#define CONTROL_M2M_NFBINTEN 0x00200000 /* Enables generation of the NFB interrupt. */ +#define CONTROL_M2M_RSS_MASK 0x00c00000 /* Request source selection: */ +#define CONTROL_M2M_RSS_SHIFT 22 /* 000 - External DReq[0] */ + /* 001 - External DReq[1] */ + /* 01X - Internal SSPRx */ + /* 10X - Internal SSPTx */ + /* 11X - Internal IDE */ +#define CONTROL_M2M_NO_HDSK 0x01000000 /* No handshake. When set the peripheral doesn't */ + /* require the regular handshake protocal. Must */ + /* be set for SSP and IDE operations, optional */ + /* for external peripherals. */ +#define CONTROL_M2M_PWSC_MASK 0xfe000000 /* Peripheral wait states count. Gives the latency */ +#define CONTROL_M2M_PWSC_SHIFT 25 /* (in PCLK cycles) needed by the peripheral to */ + /* deassert its' request once the M2M xfer w/ DMA */ + /* is complete. */ + +/* + * M2M INTERRUPT register bit defines + */ +#define INTERRUPT_M2M_STALLINT 0x00000001 /* Stall interrupt indicates channel stalled. */ +#define INTERRUPT_M2M_DONEINT 0x00000002 /* Transaction done. */ +#define INTERRUPT_M2M_NFBINT 0x00000004 /* Next frame buffer interrupt indicates */ + /* channel requires a new buffer */ + + + +/* + * M2M STATUS register bit defines + */ +#define STATUS_M2M_STALL 0x00000001 /* A '1' indicates channel is stalled */ +#define STATUS_M2M_CURRENTSTATE_MASK 0x0000003e /* Indicates state of M2M Channel control */ +#define STATUS_M2M_CURRENTSTATE_SHIFT 1 /* FSM (0-2): */ + /* 000 - IDLE, 001 - STALL, 010 - MEM_RD, */ + /* 011 - MEM_WR, 100 - BWC_WAIT */ + /* and M2M buffer FSM (3-2): */ + /* 00 - NO_BUF, 01 - BUF_ON, 10 - BUF_NEXT */ +#define STATUS_M2M_DONE 0x00000040 /* Transfer completed successfully if 1. */ +#define STATUS_M2M_TCS_MASK 0x00000180 /* Terminal Count status. Indicates whether or */ +#define STATUS_M2M_TCS_SHIFT 7 /* or not the actual byte count reached */ + /* programmed limit for buffer descriptor */ +#define STATUS_M2M_EOTS_MASK 0x00000600 /* End-of-Transfer status for buffer */ +#define STATUS_M2M_EOTS_SHIFT 9 +#define STATUS_M2M_NFB 0x00000800 /* A '1' indicates channel has moved */ + /* from NEXT state to ON state, but the next */ + /* byte count reg for next buffer has not been */ + /* programmed yet. */ +#define STATUS_M2M_NB 0x00001000 /* NextBuffer status. Informs NFB service */ + /* routine, after NFB int, which pair of buffer */ + /* descriptor registers is free to update. */ +#define STATUS_M2M_DREQS 0x00002000 /* DREQ status. Reflects the status of the */ + /* synchronized external peripherals DMA */ + /* request signal. */ + +/* + * Register masks to mask off reserved bits after reading register. + */ +#define M2M_MASK_BCR0 0x0000ffff +#define M2M_MASK_BCR1 0x0000ffff +#define M2M_MASK_SAR_BASE0 0xffffffff +#define M2M_MASK_SAR_BASE1 0xffffffff +#define M2M_MASK_SAR_CURRENT0 0xffffffff +#define M2M_MASK_SAR_CURRENT1 0xffffffff +#define M2M_MASK_DAR_BASE0 0xffffffff +#define M2M_MASK_DAR_BASE1 0xffffffff +#define M2M_MASK_DAR_CURRENT0 0xffffffff +#define M2M_MASK_DAR_CURRENT1 0xffffffff + + +#endif /* _REGS_DMA_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_i2s.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_i2s.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_i2s.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_i2s.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,97 @@ +/*============================================================================= + * + * FILE: reg_i2s.h + * + * DESCRIPTION: ep93xx I2S Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + *============================================================================= + */ +#ifndef _REG_I2S_H_ +#define _REG_I2S_H_ + +// +// I2STXClkCfg bits +// +#define i2s_txcc_trls 0x00000001 +#define i2s_txcc_tckp 0x00000002 +#define i2s_txcc_trel 0x00000004 +#define i2s_txcc_mstr 0x00000008 +#define i2s_txcc_nbcg 0x00000010 + +#define i2s_txcc_bcr_32x 0x00000020 +#define i2s_txcc_bcr_64x 0x00000040 +#define i2s_txcc_bcr_128x 0x00000060 + +// +// I2SRxClkCfg bits +// +#define i2s_rxcc_rrls 0x00000001 +#define i2s_rxcc_rckp 0x00000002 +#define i2s_rxcc_rrel 0x00000004 +#define i2s_rxcc_mstr 0x00000008 +#define i2s_rxcc_nbcg 0x00000010 + +#define i2s_rxcc_bcr_32x 0x00000020 +#define i2s_rxcc_bcr_64x 0x00000040 +#define i2s_rxcc_bcr_128x 0x00000060 + +// +// I2SGlSts bits +// +#define TX0_UNDERFLOW 0x00000001 +#define TX1_UNDERFLOW 0x00000002 +#define TX2_UNDERFLOW 0x00000004 + +#define RX0_OVERFLOW 0x00000008 +#define RX1_OVERFLOW 0x00000010 +#define RX2_OVERFLOW 0x00000020 + +#define TX0_OVERFLOW 0x00000040 +#define TX1_OVERFLOW 0x00000080 +#define TX2_OVERFLOW 0x00000100 + +#define RX0_UNDERFLOW 0x00000200 +#define RX1_UNDERFLOW 0x00000400 +#define RX2_UNDERFLOW 0x00000800 + +#define TX0_FIFO_FULL 0x00001000 +#define TX0_FIFO_EMPTY 0x00002000 +#define TX0_FIFO_HALF_EMPTY 0x00004000 + +#define RX0_FIFO_FULL 0x00008000 +#define RX0_FIFO_EMPTY 0x00010000 +#define RX0_FIFO_HALF_FULL 0x00020000 + +#define TX1_FIFO_FULL 0x00040000 +#define TX1_FIFO_EMPTY 0x00080000 +#define TX1_FIFO_HALF_EMPTY 0x00100000 + +#define RX1_FIFO_FULL 0x00200000 +#define RX1_FIFO_EMPTY 0x00400000 +#define RX1_FIFO_HALF_FULL 0x00800000 + +#define TX2_FIFO_FULL 0x01000000 +#define TX2_FIFO_EMPTY 0x02000000 +#define TX2_FIFO_HALF_EMPTY 0x04000000 + +#define RX2_FIFO_FULL 0x08000000 +#define RX2_FIFO_EMPTY 0x10000000 +#define RX2_FIFO_HALF_FULL 0x20000000 + +#endif // _REG_I2S_H_ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_ide.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_ide.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_ide.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_ide.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,105 @@ +/***************************************************************************** + * + * linux/include/asm-arm/arch-ep93xx/regs_ide.h + * + * Register definitions for the ep93xx ide registers. + * + * Copyright (C) 2003 Cirrus Logic + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + * + ****************************************************************************/ +#ifndef _REGS_IDE_H_ +#define _REGS_IDE_H_ + +/***************************************************************************** + * + * Bit definitions for use with assembly code for the ide control register. + * + ****************************************************************************/ +#define IDECtrl_CS0n 0x00000001 +#define IDECtrl_CS1n 0x00000002 +#define IDECtrl_DA_MASK 0x0000001c +#define IDECtrl_DA_SHIFT 2 +#define IDECtrl_DIORn 0x00000020 +#define IDECtrl_DIOWn 0x00000040 +#define IDECtrl_DASPn 0x00000080 +#define IDECtrl_DMARQ 0x00000100 +#define IDECtrl_INTRQ 0x00000200 +#define IDECtrl_IORDY 0x00000400 + +#define IDECfg_IDEEN 0x00000001 +#define IDECfg_PIO 0x00000002 +#define IDECfg_MDMA 0x00000004 +#define IDECfg_UDMA 0x00000008 +#define IDECfg_MODE_MASK 0x000000f0 +#define IDECfg_MODE_SHIFT 4 +#define IDECfg_WST_MASK 0x00000300 +#define IDECfg_WST_SHIFT 8 + +#define IDEMDMAOp_MEN 0x00000001 +#define IDEMDMAOp_RWOP 0x00000002 + +#define IDEUDMAOp_UEN 0x00000001 +#define IDEUDMAOp_RWOP 0x00000002 + +#define IDEUDMASts_CS0n 0x00000001 +#define IDEUDMASts_CS1n 0x00000002 +#define IDEUDMASts_DA_MASK 0x0000001c +#define IDEUDMASts_DA_SHIFT 2 +#define IDEUDMASts_HSHD 0x00000020 +#define IDEUDMASts_STOP 0x00000040 +#define IDEUDMASts_DM 0x00000080 +#define IDEUDMASts_DDOE 0x00000100 +#define IDEUDMASts_DMARQ 0x00000200 +#define IDEUDMASts_DSDD 0x00000400 +#define IDEUDMASts_DMAide 0x00010000 +#define IDEUDMASts_INTide 0x00020000 +#define IDEUDMASts_SBUSY 0x00040000 +#define IDEUDMASts_NDO 0x01000000 +#define IDEUDMASts_NDI 0x02000000 +#define IDEUDMASts_N4X 0x04000000 + +#define IDEUDMADebug_RWOE 0x00000001 +#define IDEUDMADebug_RWPTR 0x00000002 +#define IDEUDMADebug_RWDR 0x00000004 +#define IDEUDMADebug_RROE 0x00000008 +#define IDEUDMADebug_RRPTR 0x00000010 +#define IDEUDMADebug_RRDR 0x00000020 + +#define IDEUDMAWrBufSts_HPTR_MASK 0x0000000f +#define IDEUDMAWrBufSts_HPTR_SHIFT 0 +#define IDEUDMAWrBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMAWrBufSts_TPTR_SHIFT 4 +#define IDEUDMAWrBufSts_EMPTY 0x00000100 +#define IDEUDMAWrBufSts_HOM 0x00000200 +#define IDEUDMAWrBufSts_NFULL 0x00000400 +#define IDEUDMAWrBufSts_FULL 0x00000800 +#define IDEUDMAWrBufSts_CRC_MASK 0xffff0000 +#define IDEUDMAWrBufSts_CRC_SHIFT 16 + +#define IDEUDMARdBufSts_HPTR_MASK 0x0000000f +#define IDEUDMARdBufSts_HPTR_SHIFT 0 +#define IDEUDMARdBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMARdBufSts_TPTR_SHIFT 4 +#define IDEUDMARdBufSts_EMPTY 0x00000100 +#define IDEUDMARdBufSts_HOM 0x00000200 +#define IDEUDMARdBufSts_NFULL 0x00000400 +#define IDEUDMARdBufSts_FULL 0x00000800 +#define IDEUDMARdBufSts_CRC_MASK 0xffff0000 +#define IDEUDMARdBufSts_CRC_SHIFT 16 + +#endif /* _REGS_IDE_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_irda.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_irda.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_irda.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_irda.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,24 @@ +/*======================================================================= + * + * FILE: regs_irda.h + * + * DESCRIPTION: IrDA Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + *======================================================================= + */ +#ifndef _REGS_IRDA_H_ +#define _REGS_IRDA_H_ + +/* Bit definitions */ + +#define IrEnable_EN_NONE 0x00 +#define IrEnable_EN_SIR 0x01 +#define IrEnable_EN_MIR 0x02 +#define IrEnable_EN_FIR 0x03 +#define IrEnable_LBM 0x04 +#define IrEnable_MD 0x08 +#define IrEnable_FD 0x10 + +#endif /* _REGS_IRDA_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_raster.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_raster.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_raster.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_raster.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,347 @@ +/*============================================================================= + * + * FILE: regs_raster.h + * + * DESCRIPTION: ep93xx Raster Engine Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + *============================================================================= + */ +#ifndef _REGS_RASTER_H_ +#define _REGS_RASTER_H_ + +//----------------------------------------------------------------------------- +// VLINESTOTAL Register Definitions +//----------------------------------------------------------------------------- +#define VLINESTOTAL_MASK 0x000007ff + +//----------------------------------------------------------------------------- +// VSYNCSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VSYNCSTRTSTOP_STRT_MASK 0x07ff0000 +#define VSYNCSTRTSTOP_STRT_SHIFT 0 +#define VSYNCSTRTSTOP_STOP_MASK 0x000007ff +#define VSYNCSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// VACTIVESTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VACTIVESTRTSTOP_STRT_MASK 0x07ff0000 +#define VACTIVESTRTSTOP_STRT_SHIFT 0 +#define VACTIVESTRTSTOP_STOP_MASK 0x000007ff +#define VACTIVESTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// VCLKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VCLKSTRTSTOP_STRT_MASK 0x07ff0000 +#define VCLKSTRTSTOP_STRT_SHIFT 0 +#define VCLKSTRTSTOP_STOP_MASK 0x000007ff +#define VCLKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// VBLANKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VBLANKSTRTSTOP_STRT_MASK 0x07ff0000 +#define VBLANKSTRTSTOP_STRT_SHIFT 0 +#define VBLANKSTRTSTOP_STOP_MASK 0x000007ff +#define VBLANKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// HSYNCSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HSYNCSTRTSTOP_STRT_MASK 0x07ff0000 +#define HSYNCSTRTSTOP_STRT_SHIFT 0 +#define HSYNCSTRTSTOP_STOP_MASK 0x000007ff +#define HSYNCSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// HACTIVESTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HACTIVESTRTSTOP_STRT_MASK 0x07ff0000 +#define HACTIVESTRTSTOP_STRT_SHIFT 0 +#define HACTIVESTRTSTOP_STOP_MASK 0x000007ff +#define HACTIVESTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// HCLKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HCLKSTRTSTOP_STRT_MASK 0x07ff0000 +#define HCLKSTRTSTOP_STRT_SHIFT 0 +#define HCLKSTRTSTOP_STOP_MASK 0x000007ff +#define HCLKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// BRIGHTNESS Register Definitions +//----------------------------------------------------------------------------- +#define BRIGHTNESS_MASK 0x0000ffff +#define BRIGHTNESS_CNT_MASK 0x000000ff +#define BRIGHTNESS_CNT_SHIFT 0 +#define BRIGHTNESS_CMP_MASK 0x0000ff00 +#define BRIGHTNESS_CMP_SHIFT 8 + +//----------------------------------------------------------------------------- +// VIDEOATTRIBS Register Definitions +//----------------------------------------------------------------------------- +#define VIDEOATTRIBS_MASK 0x001fffff +#define VIDEOATTRIBS_EN 0x00000001 +#define VIDEOATTRIBS_PCLKEN 0x00000002 +#define VIDEOATTRIBS_SYNCEN 0x00000004 +#define VIDEOATTRIBS_DATAEN 0x00000008 +#define VIDEOATTRIBS_CSYNC 0x00000010 +#define VIDEOATTRIBS_VCPOL 0x00000020 +#define VIDEOATTRIBS_HSPOL 0x00000040 +#define VIDEOATTRIBS_BLKPOL 0x00000080 +#define VIDEOATTRIBS_INVCLK 0x00000100 +#define VIDEOATTRIBS_ACEN 0x00000200 +#define VIDEOATTRIBS_LCDEN 0x00000400 +#define VIDEOATTRIBS_CCIREN 0x00001000 +#define VIDEOATTRIBS_PIFEN 0x00002000 +#define VIDEOATTRIBS_INTEN 0x00004000 +#define VIDEOATTRIBS_INT 0x00008000 +#define VIDEOATTRIBS_INTRLC 0x00010000 +#define VIDEOATTRIBS_EQUSER 0x00020000 +#define VIDEOATTRIBS_DHORZ 0x00040000 +#define VIDEOATTRIBS_DVERT 0x00080000 +#define VIDEOATTRIBS_BKPXD 0x00100000 + +#define VIDEOATTRIBS_SDSEL_MASK 0x00600000 +#define VIDEOATTRIBS_SDSEL_SHIFT 21 + +//----------------------------------------------------------------------------- +// HBLANKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HBLANKSTRTSTOP_STRT_MASK 0x07ff0000 +#define HBLANKSTRTSTOP_STRT_SHIFT 0 +#define HBLANKSTRTSTOP_STOP_MASK 0x000007ff +#define HBLANKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// LINECARRY Register Definitions +//----------------------------------------------------------------------------- +#define LINECARRY_LCARY_MASK 0x000007ff +#define LINECARRY_LCARY_SHIFT 0 + +//----------------------------------------------------------------------------- +// BLINKRATE Register Definitons +//----------------------------------------------------------------------------- +#define BLINKRATE_MASK 0x000000ff + +//----------------------------------------------------------------------------- +// BLINKMASK Register Definitons +//----------------------------------------------------------------------------- +#define BLINKMASK_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// VIDSCRNPAGE Register Definitons +//----------------------------------------------------------------------------- +#define VIDSCRNPAGE_PAGE_MASK 0x0ffffffc + +//----------------------------------------------------------------------------- +// VIDSCRNHPG Register Definitons +//----------------------------------------------------------------------------- +#define VIDSCRNHPG_MASK 0x0ffffffc + +//----------------------------------------------------------------------------- +// SCRNLINES Register Definitons +//----------------------------------------------------------------------------- +#define SCRNLINES_MASK 0x000007ff + +//----------------------------------------------------------------------------- +// LINELENGTH Register Definitons +//----------------------------------------------------------------------------- +#define LINELENGTH_MASK 0x000007ff + +//----------------------------------------------------------------------------- +// VLINESTEP Register Definitons +//----------------------------------------------------------------------------- +#define VLINESTEP_MASK 0x00000fff + +//----------------------------------------------------------------------------- +// RASTER_SWLOCK Register Definitons +//----------------------------------------------------------------------------- +#define RASTER_SWLOCK_MASK_WR 0xff +#define RASTER_SWLOCK_MASK_R 0x1 +#define RASTER_SWLOCK_VALUE 0xaa + +//----------------------------------------------------------------------------- +// LUTCONT Register Definitions +//----------------------------------------------------------------------------- +#define LUTCONT_MASK 0x00000003 +#define LUTCONT_SWTCH 0x00000001 +#define LUTCONT_STAT 0x00000002 +#define LUTCONT_RAM0 0 +#define LUTCONT_RAM1 1 + +//----------------------------------------------------------------------------- +// CURSORBLINK1 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORBLINK1_MASK 0x00ffffff +//----------------------------------------------------------------------------- +// CURSORBLINK2 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORBLINK2_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// CURSORBLINK Register Definitions +//----------------------------------------------------------------------------- +#define CURSORBLINK_MASK 0x000001ff +#define CURSORBLINK_RATE_MASK 0x000000ff +#define CURSORBLINK_RATE_SHIFT 0 +#define CURSORBLINK_EN 0x00000100 + +//----------------------------------------------------------------------------- +// BLINKPATRN Register Definitions +//----------------------------------------------------------------------------- +#define BLINKPATRN_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// PATRNMASK Register Definitions +//----------------------------------------------------------------------------- +#define PATRNMASK_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// BG_OFFSET Register Definitions +//----------------------------------------------------------------------------- +#define BG_OFFSET_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// PIXELMODE Register Definitions +//----------------------------------------------------------------------------- +#define PIXELMODE_P_MASK 0x00000007 +#define PIXELMODE_P_MUX_DISABLE 0x00000000 +#define PIXELMODE_P_4BPP 0x00000001 +#define PIXELMODE_P_8BPP 0x00000002 +#define PIXELMODE_P_16BPP 0x00000004 +#define PIXELMODE_P_24BPP 0x00000006 +#define PIXELMODE_P_32BPP 0x00000007 + +#define PIXELMODE_S_MASK 0x00000038 +#define PIXELMODE_S_1PPC 0x00000000 +#define PIXELMODE_S_1PPCMAPPED 0x00000008 +#define PIXELMODE_S_2PPC 0x00000010 +#define PIXELMODE_S_4PPC 0x00000018 +#define PIXELMODE_S_8PPC 0x00000020 +#define PIXELMODE_S_223PPC 0x00000028 +#define PIXELMODE_S_DS223PPC 0x00000030 +#define PIXELMODE_S_UNDEF 0x00000038 + +#define PIXELMODE_M_MASK 0x000003c0 +#define PIXELMODE_M_NOBLINK 0x00000000 +#define PIXELMODE_M_ANDBLINK 0x00000040 +#define PIXELMODE_M_ORBLINK 0x00000080 +#define PIXELMODE_M_XORBLINK 0x000000c0 +#define PIXELMODE_M_BGBLINK 0x00000100 +#define PIXELMODE_M_OFFSINGBLINK 0x00000140 +#define PIXELMODE_M_OFF888BLINK 0x00000180 +#define PIXELMODE_M_DIMBLINK 0x00000300 +#define PIXELMODE_M_BRTBLINK 0x00000340 +#define PIXELMODE_M_DIM888BLINK 0x00000380 +#define PIXELMODE_M_BRT888BLINK 0x000003c0 + +#define PIXELMODE_C_MASK 0x00003c00 +#define PIXELMODE_C_LUT 0x00000000 +#define PIXELMODE_C_888 0x00001000 +#define PIXELMODE_C_565 0x00001400 +#define PIXELMODE_C_555 0x00001800 +#define PIXELMODE_C_GSLUT 0x00002000 + +#define PIXELMODE_DSCAN 0x00004000 +#define PIXELMODE_TRBSW 0x00008000 + +//----------------------------------------------------------------------------- +//PARLLIFOUT Register Defintions +//----------------------------------------------------------------------------- +#define PARLLIFOUT_DAT_MASK 0x0000000f +#define PARLLIFOUT_DAT_SHIFT 0 +#define PARLLIFOUT_RD 0x00000010 + +//----------------------------------------------------------------------------- +//PARLLIFIN Register Defintions +//----------------------------------------------------------------------------- +#define PARLLIFIN_DAT_MASK 0x0000000f +#define PARLLIFIN_DAT_SHIFT 0 +#define PARLLIFIN_CNT_MASK 0x000f0000 +#define PARLLIFIN_CNT_SHIFT 16 +#define PARLLIFIN_ESTRT_MASK 0x00f00000 +#define PARLLIFIN_ESTRT_SHIFT 20 + +//----------------------------------------------------------------------------- +// CURSORADRSTART Register Defintions +//----------------------------------------------------------------------------- +#define CURSOR_ADR_START_MASK 0xfffffffc + +//----------------------------------------------------------------------------- +// CURSORADRSTART Register Defintions +//----------------------------------------------------------------------------- +#define CURSOR_ADR_RESET_MASK 0xfffffffc + +//----------------------------------------------------------------------------- +// CURSORCOLOR1 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORCOLOR1_MASK 0x00ffffff +//----------------------------------------------------------------------------- +// CURSORCOLOR2 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORCOLOR2_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// CURSORXYLOC Register Definitions +//----------------------------------------------------------------------------- +#define CURSORXYLOC_MASK 0x07ff87ff +#define CURSORXYLOC_XLOC_MASK 0x000007ff +#define CURSORXYLOC_XLOC_SHIFT 0 +#define CURSORXYLOC_CEN 0x00008000 +#define CURSORXYLOC_YLOC_MASK 0x07ff0000 +#define CURSORXYLOC_YLOC_SHIFT 16 + +//----------------------------------------------------------------------------- +// CURSOR_DSCAN_LH_YLOC Register Definitions +//----------------------------------------------------------------------------- +#define CURSOR_DSCAN_LH_YLOC_MASK 0x000087ff + +#define CURSOR_DSCAN_LH_YLOC_YLOC_MASK 0x000007ff +#define CURSOR_DSCAN_LH_YLOC_YLOC_SHIFT 0 +#define CURSOR_DSCAN_LH_YLOC_CLHEN 0x00008000 + +//----------------------------------------------------------------------------- +// CURSORSIZE Register Definitions +//----------------------------------------------------------------------------- +#define CURSORSIZE_MASK 0x0000ffff + +#define CURSORSIZE_CWID_MASK 0x00000003 +#define CURSORSIZE_CWID_SHIFT 0 +#define CURSORSIZE_CWID_1_WORD 0 +#define CURSORSIZE_CWID_2_WORD 1 +#define CURSORSIZE_CWID_3_WORD 2 +#define CURSORSIZE_CWID_4_WORD 3 + +#define CURSORSIZE_CLINS_MASK 0x000000fc +#define CURSORSIZE_CLINS_SHIFT 2 + +#define CURSORSIZE_CSTEP_MASK 0x00000300 +#define CURSORSIZE_CSTEP_SHIFT 8 +#define CURSORSIZE_CSTEP_1_WORD 0 +#define CURSORSIZE_CSTEP_2_WORD 1 +#define CURSORSIZE_CSTEP_3_WORD 2 +#define CURSORSIZE_CSTEP_4_WORD 3 + +#define CURSORSIZE_DLNS_MASK 0x0000fc00 +#define CURSORSIZE_DLNS_SHIFT 10 + +#endif /* _REGS_RASTER_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_smc.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_smc.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_smc.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_smc.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,57 @@ +/*======================================================================= + * + * FILE: regs_smc.h + * + * DESCRIPTION: Static Memory Controller/PCMCIA Register Definition + * + * Copyright Cirrus Logic, 2001-2004 + * + *======================================================================= + */ +#ifndef _REGS_SMC_H_ +#define _REGS_SMC_H_ + +/* Bit definitions */ + +// +// Bit fields for SMCBCR? +// +#define SMCBCR_IDCY_MASK 0x0000000f +#define SMCBCR_WST1_MASK 0x000003e0 +#define SMCBCR_RBLE 0x00000400 +#define SMCBCR_WST2_MASK 0x0000f800 +#define SMCBCR_WPERR 0x02000000 +#define SMCBCR_WP 0x04000000 +#define SMCBCR_PME 0x08000000 +#define SMCBCR_MW_MASK 0x30000000 +#define SMCBCR_MW_8 0x00000000 +#define SMCBCR_MW_16 0x10000000 +#define SMCBCR_MW_32 0x20000000 +#define SMCBCR_EBIBRKDIS 0x40000000 +#define SMCBCR_IDCY_SHIFT 0 +#define SMCBCR_WST1_SHIFT 5 +#define SMCBCR_WST2_SHIFT 11 +#define SMCBCR_MW_SHIFT 28 + +// +// Bit field for SMC_PCAttribute, SMC_PCCommon, and SMC_PCIO +// +#define PCCONFIG_ADDRESSTIME_MASK 0x000000FF +#define PCCONFIG_HOLDTIME_MASK 0x00000F00 +#define PCCONFIG_ACCESSTIME_MASK 0x00FF0000 +#define PCCONFIG_MW_8BIT 0x00000000 +#define PCCONFIG_MW_16BIT 0x80000000 +#define PCCONFIG_ADDRESSTIME_SHIFT 0 +#define PCCONFIG_HOLDTIME_SHIFT 8 +#define PCCONFIG_ACCESSTIME_SHIFT 16 + +// +// Bit field for SMC_PCMCIACtrl +// +#define PCCONT_PC1EN 0x00000001 +#define PCCONT_PC2EN 0x00000002 +#define PCCONT_PC1RST 0x00000004 +#define PCCONT_WEN 0x00000010 + + +#endif /* _REGS_SMC_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_spi.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_spi.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_spi.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_spi.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,87 @@ +/*======================================================================= + * + * FILE: regs_spi.h + * + * DESCRIPTION: SSP Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + *======================================================================= + */ + +#ifndef _REGS_SSP_H_ +#define _REGS_SSP_H_ + +//----------------------------------------------------------------------------- +// Bits in SSPCR0 +//----------------------------------------------------------------------------- +#define SSPCR0_DSS_MASK 0x0000000f +#define SSPCR0_DSS_4BIT 0x00000003 +#define SSPCR0_DSS_5BIT 0x00000004 +#define SSPCR0_DSS_6BIT 0x00000005 +#define SSPCR0_DSS_7BIT 0x00000006 +#define SSPCR0_DSS_8BIT 0x00000007 +#define SSPCR0_DSS_9BIT 0x00000008 +#define SSPCR0_DSS_10BIT 0x00000009 +#define SSPCR0_DSS_11BIT 0x0000000a +#define SSPCR0_DSS_12BIT 0x0000000b +#define SSPCR0_DSS_13BIT 0x0000000c +#define SSPCR0_DSS_14BIT 0x0000000d +#define SSPCR0_DSS_15BIT 0x0000000e +#define SSPCR0_DSS_16BIT 0x0000000f + +//----------------------------------------------------------------------------- +// Bits in SSPCR1 +//----------------------------------------------------------------------------- +#define SSPC1_RIE 0x00000001 +#define SSPC1_TIE 0x00000002 +#define SSPC1_RORIE 0x00000004 +#define SSPC1_LBM 0x00000008 +#define SSPC1_SSE 0x00000010 +#define SSPC1_MS 0x00000020 +#define SSPC1_SOD 0x00000040 + +#define SSPCR0_DSS_SHIFT 0 +#define SSPCR0_FRF_MASK 0x00000030 +#define SSPCR0_FRF_SHIFT 4 +#define SSPCR0_FRF_MOTOROLA (0 << SSPCR0_FRF_SHIFT) +#define SSPCR0_FRF_TI (1 << SSPCR0_FRF_SHIFT) +#define SSPCR0_FRF_NI (2 << SSPCR0_FRF_SHIFT) +#define SSPCR0_SPO 0x00000040 +#define SSPCR0_SPH 0x00000080 +#define SSPCR0_SCR_MASK 0x0000ff00 +#define SSPCR0_SCR_SHIFT 8 + +//----------------------------------------------------------------------------- +// Bits in SSPSR +//----------------------------------------------------------------------------- +#define SSPSR_TFE 0x00000001 // TX FIFO is empty +#define SSPSR_TNF 0x00000002 // TX FIFO is not full +#define SSPSR_RNE 0x00000004 // RX FIFO is not empty +#define SSPSR_RFF 0x00000008 // RX FIFO is full +#define SSPSR_BSY 0x00000010 // SSP is busy + +//----------------------------------------------------------------------------- +// Bits in SSPIIR +//----------------------------------------------------------------------------- +#define SSPIIR_RIS 0x00000001 // RX FIFO IRQ status +#define SSPIIR_TIS 0x00000002 // TX FIFO is not full +#define SSPIIR_RORIS 0x00000004 // RX FIFO is full + +//============================================================================= +//============================================================================= + +#endif /* _REGS_SSP_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_syscon.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_syscon.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_syscon.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_syscon.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,286 @@ +/*============================================================================= + * + * FILE: reg_syscon.h + * + * DESCRIPTION: ep93xx Syscon Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + *============================================================================= + */ +#ifndef _REGS_SYSCON_H_ +#define _REGS_SYSCON_H_ + +//============================================================================= +#ifndef __ASSEMBLY__ + +#define SysconSetLocked(registername,value) \ + { \ + local_irq_disable(); \ + outl( 0xAA, EP93XX_SYSCON_SWLOCK); \ + outl( value, registername); \ + local_irq_enable(); \ + } + +#endif /* Not __ASSEMBLY__ */ +//============================================================================= + +//----------------------------------------------------------------------------- +// SYSCON_CLKSET1 +//----------------------------------------------------------------------------- +#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0 +#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f +#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5 +#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0 +#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11 +#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800 +#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16 +#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000 +#define SYSCON_CLKSET1_PCLKDIV_SHIFT 18 +#define SYSCON_CLKSET1_PCLKDIV_MASK 0x000c0000 +#define SYSCON_CLKSET1_HCLKDIV_SHIFT 20 +#define SYSCON_CLKSET1_HCLKDIV_MASK 0x00700000 +#define SYSCON_CLKSET1_nBYP1 0x00800000 +#define SYSCON_CLKSET1_SMCROM 0x01000000 +#define SYSCON_CLKSET1_FCLKDIV_SHIFT 25 +#define SYSCON_CLKSET1_FCLKDIV_MASK 0x0e000000 + +#define SYSCON_CLKSET1_HSEL 0x00000001 +#define SYSCON_CLKSET1_PLL1_EXCLKSEL 0x00000002 + +#define SYSCON_CLKSET1_PLL1_P_MASK 0x0000007C +#define SYSCON_CLKSET1_PLL1_P_SHIFT 2 + +#define SYSCON_CLKSET1_PLL1_M1_MASK 0x00000780 +#define SYSCON_CLKSET1_PLL1_M1_SHIFT 7 +#define SYSCON_CLKSET1_PLL1_M2_MASK 0x0000F800 +#define SYSCON_CLKSET1_PLL1_M2_SHIFT 11 +#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000 +#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16 +#define SYSCON_CLKSET1_PCLK_DIV_MASK 0x000C0000 +#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 +#define SYSCON_CLKSET1_HCLK_DIV_MASK 0x00700000 +#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 +#define SYSCON_CLKSET1_SMCROM 0x01000000 +#define SYSCON_CLKSET1_FCLK_DIV_MASK 0x0E000000 +#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 + +#define SYSCON_CLKSET2_PLL2_EN 0x00000001 +#define SYSCON_CLKSET2_PLL2EXCLKSEL 0x00000002 +#define SYSCON_CLKSET2_PLL2_P_MASK 0x0000007C +#define SYSCON_CLKSET2_PLL2_P_SHIFT 2 +#define SYSCON_CLKSET2_PLL2_M2_MASK 0x00000F80 +#define SYSCON_CLKSET2_PLL2_M2_SHIFT 7 +#define SYSCON_CLKSET2_PLL2_M1_MASK 0x0001F000 +#define SYSCON_CLKSET2_PLL2_M1 12 +#define SYSCON_CLKSET2_PLL2_PS_MASK 0x000C0000 +#define SYSCON_CLKSET2_PLL2_PS_SHIFT 18 +#define SYSCON_CLKSET2_USBDIV_MASK 0xF0000000 +#define SYSCON_CLKSET2_USBDIV_SHIFT 28 + +//----------------------------------------------------------------------------- +// DEV_CFG Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_DEVCFG_SHena 0x00000001 +#define SYSCON_DEVCFG_KEYS 0x00000002 +#define SYSCON_DEVCFG_ADCPD 0x00000004 +#define SYSCON_DEVCFG_RAS 0x00000008 +#define SYSCON_DEVCFG_RASonP3 0x00000010 +#define SYSCON_DEVCFG_TTIC 0x00000020 +#define SYSCON_DEVCFG_I2SonAC97 0x00000040 +#define SYSCON_DEVCFG_I2SonSSP 0x00000080 +#define SYSCON_DEVCFG_EonIDE 0x00000100 +#define SYSCON_DEVCFG_PonG 0x00000200 +#define SYSCON_DEVCFG_GonIDE 0x00000400 +#define SYSCON_DEVCFG_HonIDE 0x00000800 +#define SYSCON_DEVCFG_HC1CEN 0x00001000 +#define SYSCON_DEVCFG_HC1IN 0x00002000 +#define SYSCON_DEVCFG_HC3CEN 0x00004000 +#define SYSCON_DEVCFG_HC3IN 0x00008000 +#define SYSCON_DEVCFG_TIN 0x00020000 +#define SYSCON_DEVCFG_U1EN 0x00040000 +#define SYSCON_DEVCFG_EXVC 0x00080000 +#define SYSCON_DEVCFG_U2EN 0x00100000 +#define SYSCON_DEVCFG_A1onG 0x00200000 +#define SYSCON_DEVCFG_A2onG 0x00400000 +#define SYSCON_DEVCFG_CPENA 0x00800000 +#define SYSCON_DEVCFG_U3EN 0x01000000 +#define SYSCON_DEVCFG_MonG 0x02000000 +#define SYSCON_DEVCFG_TonG 0x04000000 +#define SYSCON_DEVCFG_GonK 0x08000000 +#define SYSCON_DEVCFG_IonU2 0x10000000 +#define SYSCON_DEVCFG_D0onG 0x20000000 +#define SYSCON_DEVCFG_D1onG 0x40000000 +#define SYSCON_DEVCFG_SWRST 0x80000000 + +//----------------------------------------------------------------------------- +// VIDDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_VIDDIV_VDIV_MASK 0x0000007f +#define SYSCON_VIDDIV_VDIV_SHIFT 0 +#define SYSCON_VIDDIV_PDIV_MASK 0x00000300 +#define SYSCON_VIDDIV_PDIV_SHIFT 8 +#define SYSCON_VIDDIV_PSEL 0x00002000 +#define SYSCON_VIDDIV_ESEL 0x00004000 +#define SYSCON_VIDDIV_VENA 0x00008000 + +//----------------------------------------------------------------------------- +// MIRDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_MIRDIV_MDIV_MASK 0x0000003f +#define SYSCON_MIRDIV_MDIV_SHIFT 0 +#define SYSCON_MIRDIV_PDIV_MASK 0x00000300 +#define SYSCON_MIRDIV_PDIV_SHIFT 8 +#define SYSCON_MIRDIV_PSEL 0x00002000 +#define SYSCON_MIRDIV_ESEL 0x00004000 +#define SYSCON_MIRDIV_MENA 0x00008000 + +//----------------------------------------------------------------------------- +// I2SDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_I2SDIV_MDIV_MASK 0x0000007f +#define SYSCON_I2SDIV_MDIV_SHIFT 0 +#define SYSCON_I2SDIV_PDIV_MASK 0x00000300 +#define SYSCON_I2SDIV_PDIV_SHIFT 8 +#define SYSCON_I2SDIV_PSEL 0x00002000 +#define SYSCON_I2SDIV_ESEL 0x00004000 +#define SYSCON_I2SDIV_MENA 0x00008000 +#define SYSCON_I2SDIV_SDIV 0x00010000 +#define SYSCON_I2SDIV_LRDIV_MASK 0x00060000 +#define SYSCON_I2SDIV_LRDIV_SHIFT 17 +#define SYSCON_I2SDIV_SPOL 0x00080000 +#define SYSCON_I2SDIV_DROP 0x00100000 +#define SYSCON_I2SDIV_ORIDE 0x20000000 +#define SYSCON_I2SDIV_SLAVE 0x40000000 +#define SYSCON_I2SDIV_SENA 0x80000000 + +#define SYSCON_I2SDIV_PDIV_OFF 0x00000000 +#define SYSCON_I2SDIV_PDIV_2 0x00000100 +#define SYSCON_I2SDIV_PDIV_25 0x00000200 +#define SYSCON_I2SDIV_PDIV_3 0x00000300 + +#define SYSCON_I2SDIV_LRDIV_32 0x00000000 +#define SYSCON_I2SDIV_LRDIV_64 0x00020000 +#define SYSCON_I2SDIV_LRDIV_128 0x00040000 + +//----------------------------------------------------------------------------- +// KTDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_KTDIV_KDIV 0x00000001 +#define SYSCON_KTDIV_KEN 0x00008000 +#define SYSCON_KTDIV_ADIV 0x00010000 +#define SYSCON_KTDIV_TSEN 0x80000000 + +//----------------------------------------------------------------------------- +// CHIPID Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_CHIPID_ID_MASK 0x0000ffff +#define SYSCON_CHIPID_ID_SHIFT 0 +#define SYSCON_CHIPID_PKID 0x00010000 +#define SYSCON_CHIPID_BND 0x00040000 +#define SYSCON_CHIPID_FAB_MASK 0x0e000000 +#define SYSCON_CHIPID_FAB_SHIFT 25 +#define SYSCON_CHIPID_REV_MASK 0xf0000000 +#define SYSCON_CHIPID_REV_SHIFT 28 + +//----------------------------------------------------------------------------- +// TESTCR Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_TESTCR_TMODE_MASK 0x000000ff +#define SYSCON_TESTCR_TMODE_SHIFT 0 +#define SYSCON_TESTCR_BONDO 0x00000100 +#define SYSCON_TESTCR_PACKO 0x00000800 +#define SYSCON_TESTCR_ETOM 0x00002000 +#define SYSCON_TESTCR_TOM 0x00004000 +#define SYSCON_TESTCR_OVR 0x00008000 +#define SYSCON_TESTCR_TonIDE 0x00010000 +#define SYSCON_TESTCR_RonG 0x00020000 + +//----------------------------------------------------------------------------- +// SYSCFG Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_SYSCFG_LCSn1 0x00000001 +#define SYSCON_SYSCFG_LCSn2 0x00000002 +#define SYSCON_SYSCFG_LCSn3 0x00000004 +#define SYSCON_SYSCFG_LEECK 0x00000008 +#define SYSCON_SYSCFG_LEEDA 0x00000010 +#define SYSCON_SYSCFG_LASDO 0x00000020 +#define SYSCON_SYSCFG_LCSn6 0x00000040 +#define SYSCON_SYSCFG_LCSn7 0x00000080 +#define SYSCON_SYSCFG_SBOOT 0x00000100 +#define SYSCON_SYSCFG_FAB_MASK 0x0e000000 +#define SYSCON_SYSCFG_FAB_SHIFT 25 +#define SYSCON_SYSCFG_REV_MASK 0xf0000000 +#define SYSCON_SYSCFG_REV_SHIFT 28 + + +//----------------------------------------------------------------------------- +// PWRSR Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_PWRSR_CHIPMAN_MASK 0xFF000000 +#define SYSCON_PWRSR_CHIPMAN_SHIFT 24 +#define SYSCON_PWRSR_CHIPID_MASK 0x00FF0000 +#define SYSCON_PWRSR_CHIPID_SHIFT 16 +#define SYSCON_PWRSR_WDTFLG 0x00008000 +#define SYSCON_PWRSR_CLDFLG 0x00002000 +#define SYSCON_PWRSR_TEST_RESET 0x00001000 +#define SYSCON_PWRSR_RSTFLG 0x00000800 +#define SYSCON_PWRSR_SWRESET 0x00000400 +#define SYSCON_PWRSR_PLL2_LOCKREG 0x00000200 +#define SYSCON_PWRSR_PLL2_LOCK 0x00000100 +#define SYSCON_PWRSR_PLL1_LOCKREG 0x00000080 +#define SYSCON_PWRSR_PLL1_LOCK 0x00000040 +#define SYSCON_PWRSR_RTCDIV 0x0000003F + +//----------------------------------------------------------------------------- +// PWRCNT Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_PWRCNT_FIREN 0x80000000 +#define SYSCON_PWRCNT_UARTBAUD 0x20000000 +#define SYSCON_PWRCNT_USHEN 0x10000000 +#define SYSCON_PWRCNT_DMA_M2MCH1 0x08000000 +#define SYSCON_PWRCNT_DMA_M2MCH0 0x04000000 +#define SYSCON_PWRCNT_DMA_M2PCH8 0x02000000 +#define SYSCON_PWRCNT_DMA_M2PCH9 0x01000000 +#define SYSCON_PWRCNT_DMA_M2PCH6 0x00800000 +#define SYSCON_PWRCNT_DMA_M2PCH7 0x00400000 +#define SYSCON_PWRCNT_DMA_M2PCH4 0x00200000 +#define SYSCON_PWRCNT_DMA_M2PCH5 0x00100000 +#define SYSCON_PWRCNT_DMA_M2PCH2 0x00080000 +#define SYSCON_PWRCNT_DMA_M2PCH3 0x00040000 +#define SYSCON_PWRCNT_DMA_M2PCH0 0x00020000 +#define SYSCON_PWRCNT_DMA_M2PCH1 0x00010000 + +//----------------------------------------------------------------------------- +// BMAR Register Defines +//----------------------------------------------------------------------------- +#define BMAR_PRIORD_00 0x00000000 +#define BMAR_PRIORD_01 0x00000001 +#define BMAR_PRIORD_02 0x00000002 +#define BMAR_PRIORD_03 0x00000003 +#define BMAR_PRI_CORE 0x00000008 +#define BMAR_DMA_ENIRQ 0x00000010 +#define BMAR_DMA_ENFIQ 0x00000020 +#define BMAR_USB_ENIRQ 0x00000040 +#define BMAR_USB_ENFIQ 0x00000080 +#define BMAR_MAC_ENIRQ 0x00000100 +#define BMAR_MAC_ENFIQ 0x00000200 +#define BMAR_GRAPHICS_ENIRQ 0x00000400 +#define BMAR_GRAPHICS_ENFIQ 0x00000800 + + +#endif // _REGS_SYSCON_H_ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_touch.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_touch.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_touch.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_touch.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,95 @@ +/*============================================================================= + * + * FILE: regs_touch.h + * + * DESCRIPTION: Analog Touchscreen Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + *============================================================================= + */ +#ifndef _REGS_TOUCH_H_ +#define _REGS_TOUCH_H_ + +/* + *----------------------------------------------------------------------------- + * Individual bit #defines + *----------------------------------------------------------------------------- + */ +#define TSSETUP_SDLY_MASK 0x000003FF +#define TSSETUP_SDLY_SHIFT 0 +#define TSSETUP_NSMP_4 0x00000000 +#define TSSETUP_NSMP_8 0x00000400 +#define TSSETUP_NSMP_16 0x00000800 +#define TSSETUP_NSMP_32 0x00000C00 +#define TSSETUP_NSMP_MASK 0x00000C00 +#define TSSETUP_DEV_4 0x00000000 +#define TSSETUP_DEV_8 0x00001000 +#define TSSETUP_DEV_12 0x00002000 +#define TSSETUP_DEV_16 0x00003000 +#define TSSETUP_DEV_24 0x00004000 +#define TSSETUP_DEV_32 0x00005000 +#define TSSETUP_DEV_64 0x00006000 +#define TSSETUP_DEV_128 0x00007000 +#define TSSETUP_ENABLE 0x00008000 +#define TSSETUP_DLY_MASK 0x03FF0000 +#define TSSETUP_DLY_SHIFT 16 +#define TSSETUP_TDTCT 0x80000000 + +#define TSMAXMIN_XMIN_MASK 0x000000FF +#define TSMAXMIN_XMIN_SHIFT 0 +#define TSMAXMIN_YMIN_MASK 0x0000FF00 +#define TSMAXMIN_YMIN_SHIFT 8 +#define TSMAXMIN_XMAX_MASK 0x00FF0000 +#define TSMAXMIN_XMAX_SHIFT 16 +#define TSMAXMIN_YMAX_MASK 0xFF000000 +#define TSMAXMIN_YMAX_SHIFT 24 + +#define TSXYRESULT_X_MASK 0x00000FFF +#define TSXYRESULT_X_SHIFT 0 +#define TSXYRESULT_AD_MASK 0x0000FFFF +#define TSXYRESULT_AD_SHIFT 0 +#define TSXYRESULT_Y_MASK 0x0FFF0000 +#define TSXYRESULT_Y_SHIFT 16 +#define TSXYRESULT_SDR 0x80000000 + +#define TSX_SAMPLE_MASK 0x00003FFF +#define TSX_SAMPLE_SHIFT 0x00 +#define TSY_SAMPLE_MASK 0x3FFF0000 +#define TSY_SAMPLE_SHIFT 0x10 + +#define TSSETUP2_TINT 0x00000001 +#define TSSETUP2_NICOR 0x00000002 +#define TSSETUP2_PINT 0x00000004 +#define TSSETUP2_PENSTS 0x00000008 +#define TSSETUP2_PINTEN 0x00000010 +#define TSSETUP2_DEVINT 0x00000020 +#define TSSETUP2_DINTEN 0x00000040 +#define TSSETUP2_DTMEN 0x00000080 +#define TSSETUP2_DISDEV 0x00000100 +#define TSSETUP2_NSIGND 0x00000200 +#define TSSETUP2_S28EN 0x00000400 +#define TSSETUP2_RINTEN 0x00000800 + +#define TSXYRESULT_SDR 0x80000000 + +/* + *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- + */ + + +#endif /* _REGS_TOUCH_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/regs_uart.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_uart.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/regs_uart.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/regs_uart.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,91 @@ +/* + * File: linux/include/asm-arm/arch-ep93xx/regs_uart.h + * + * Copyright (C) 2003 Cirrus Logic, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _REGS_UART_H_ +#define _REGS_UART_H_ + +//----------------------------------------------------------------------------- +// Bits in UARTRSR +//----------------------------------------------------------------------------- +#define UARTRSR_FE 0x00000001 // Framing error +#define UARTRSR_PE 0x00000002 // Parity error +#define UARTRSR_BE 0x00000004 // Break error +#define UARTRSR_OE 0x00000008 // Overrun error +#define UARTRSR_ANY 0x0000000f // Any error + +//----------------------------------------------------------------------------- +// Bits in UARTCR - UART1CR, UART2CR, or UART3CR +//----------------------------------------------------------------------------- +#define UARTLCR_H_BRK 0x00000001 +#define UARTLCR_H_PEN 0x00000002 +#define UARTLCR_H_EPS 0x00000004 +#define UARTLCR_H_STP2 0x00000008 +#define UARTLCR_H_FEN 0x00000010 +#define UARTLCR_H_WLEN 0x00000060 +#define UARTLCR_H_WLEN_8 0x00000060 +#define UARTLCR_H_WLEN_7 0x00000040 +#define UARTLCR_H_WLEN_6 0x00000020 +#define UARTLCR_H_WLEN_5 0x00000000 + +//----------------------------------------------------------------------------- +// Bits in UARTFR - UART1FR, UART2FR, or UART3FR +//----------------------------------------------------------------------------- +#define UARTFR_RSR_ERRORS 0x0000000F +#define UARTFR_CTS 0x00000001 +#define UARTFR_DSR 0x00000002 +#define UARTFR_DCD 0x00000004 +#define UARTFR_BUSY 0x00000008 +#define UARTFR_RXFE 0x00000010 +#define UARTFR_TXFF 0x00000020 +#define UARTFR_RXFF 0x00000040 +#define UARTFR_TXFE 0x00000080 +#define UARTFR_TMSK (UARTFR_TXFF | UARTFR_BUSY) +#define UARTFR_MODEM_ANY (UARTFR_CTS | UARTFR_DSR | UARTFR_DCD) + +//----------------------------------------------------------------------------- +// Bits in UARTIIR +//----------------------------------------------------------------------------- +#define UARTIIR_MIS 0x00000001 +#define UARTIIR_RIS 0x00000002 +#define UARTIIR_TIS 0x00000004 +#define UARTIIR_RTIS 0x00000008 + +//----------------------------------------------------------------------------- +// Bits in UARTCR +//----------------------------------------------------------------------------- +#define UARTCR_UARTEN 0x00000001 +#define UARTCR_MSIE 0x00000008 +#define UARTCR_RIE 0x00000010 +#define UARTCR_TIE 0x00000020 +#define UARTCR_RTIE 0x00000040 +#define UARTCR_LBE 0x00000080 + +//----------------------------------------------------------------------------- +// Bits in UARTMCR +//----------------------------------------------------------------------------- +#define UARTMCR_DTR 0x00000001 +#define UARTMCR_RTS 0x00000002 +#define UARTMCR_OUT1 0x00000004 +#define UARTMCR_OUT2 0x00000008 +#define UARTMCR_LOOP 0x00000010 + +//============================================================================= +//============================================================================= +#endif /* _REGS_UART_H_ */ diff -Naur linux-2.6.25/include/asm-arm/arch-ep93xx/ssp.h linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/ssp.h --- linux-2.6.25/include/asm-arm/arch-ep93xx/ssp.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/arch-ep93xx/ssp.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,32 @@ +/* + * + * FILE: ssp.h + * + * DESCRIPTION: SSP Interface Driver Module implementation + * + * Copyright Cirrus Logic Corporation, 2001-2003. All rights reserved + * + */ +#ifndef _SSP_DRV_H_ +#define _SSP_DRV_H_ + +typedef enum +{ + PS2_KEYBOARD = 0, + I2S_CODEC = 1, + SERIAL_FLASH = 2 +} SSPDeviceType; + +typedef void (*SSPDataCallback)(unsigned int Data); + +typedef struct _SSP_DRIVER_API +{ + int (*Open)(SSPDeviceType Device, SSPDataCallback Callback); + int (*Read)(int Handle, unsigned int Addr, unsigned int *pValue); + int (*Write)(int Handle, unsigned int Addr, unsigned int Value); + int (*Close)(int Handle); +} SSP_DRIVER_API; + +extern SSP_DRIVER_API *SSPDriver; + +#endif /* _SSP_DRV_H_ */ diff -Naur linux-2.6.25/include/asm-arm/mach/ep93xx_pwm.h linux-2.6.25.ep93xx/include/asm-arm/mach/ep93xx_pwm.h --- linux-2.6.25/include/asm-arm/mach/ep93xx_pwm.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.25.ep93xx/include/asm-arm/mach/ep93xx_pwm.h 2008-08-18 14:05:42.000000000 -0500 @@ -0,0 +1,7 @@ +#ifndef EP93XX_PWM_H_ +#define EP93XX_PWM_H_ +#include + +struct class_device *ep93xx_pwm_device_create(unsigned long base, const char *name); + +#endif /*EP93XX_PWM_H_*/