**************************************************************
*Generate the 200k clock on the SoM-9260M
*NZG
*09/17/2007
*EMAC.Inc
**************************************************************
diff -uprN linux-2.6.20-at92_e1.1/arch/arm/mach-at91rm9200/board-som9260m.c linux-2.6.20-at92/arch/arm/mach-at91rm9200/board-som9260m.c
--- linux-2.6.20-at92_e1.1/arch/arm/mach-at91rm9200/board-som9260m.c	2007-09-17 11:27:07.000000000 -0400
+++ linux-2.6.20-at92/arch/arm/mach-at91rm9200/board-som9260m.c	2007-09-15 14:45:00.000000000 -0400
@@ -312,9 +312,66 @@ static inline void cs4_setup(void){
 	at91_set_A_periph(AT91_PIN_PC8, 1);	
 }
 
+/**
+ * creates the 200k clock in using timer1 outputB
+ * TODO: move regdefs to a more appropriate general header
+ * NOTES: hard coded clock values could be more flexibly done through the clock registery, 
+ * but it would require some 
+ * fixed point math, which will be put off for a full PWM implementation
+ * at which point it's methods will replace this code block.
+ */
+#include <asm/arch/at91_tc.h>
+#define AT91SAM9260_TC1_CCR	(AT91SAM9260_BASE_TC1 + AT91_TC_CCR)
+#define AT91SAM9260_TC1_CMR	(AT91SAM9260_BASE_TC1 + AT91_TC_CMR)
+#define AT91SAM9260_TC1_RB	(AT91SAM9260_BASE_TC1 + AT91_TC_RB)
+#define AT91SAM9260_TC1_RC	(AT91SAM9260_BASE_TC1 + AT91_TC_RC)
+
+#define MCLK (25000000)
+
+#define at91_tc_read(reg)		__raw_readl(reg)
+#define at91_tc_write(reg, val)	__raw_writel((val), reg)
+
+static inline void set200kclock(void){
+	struct clk *tc1_clk = clk_get(NULL, "tc1_clk");
+	unsigned long tc1 = (unsigned long)ioremap(AT91SAM9260_BASE_TC1,SZ_16K);
+	
+	clk_enable(tc1_clk);//enable tc1 clock in the pmc
+	
+	printk("pre AT91_TC_CMR = %x\n",at91_tc_read(tc1 + AT91_TC_CMR));
+	
+	printk("tc1 = %x\n",tc1);
+	
+	//if(tc1)
+	//tc1 setup for waveform on TCIOB1
+	at91_tc_write((tc1 + AT91_TC_CMR),
+			AT91_TC_TIMER_CLOCK1|
+			AT91_TC_WAVE|
+			AT91_TC_EEVT_XC0|
+			AT91_TC_WAVESEL_UP_AUTO|
+			AT91_TC_BCPB_TOGGLE
+			);
+	//else printk("tc1 is NULL");
+
+	//set the frequency
+	at91_tc_write((tc1 + AT91_TC_RC),(MCLK/200000));
+	
+	//set RB to < RC for toggle (50% duty)
+	at91_tc_write((tc1 + AT91_TC_RB),((MCLK/200000)/2));
+	
+	//reset and start the timer
+	at91_tc_write((tc1 + AT91_TC_CCR),AT91_TC_CLKEN|AT91_TC_SWTRG);
+	
+	//enable timer functionality on PC7, TIOB1 
+	at91_set_A_periph(AT91_PIN_PC7, 1);		
+	
+	printk("post AT91_TC_CMR = %xl\n",at91_sys_read(tc1 + AT91_TC_CMR));
+
+}
+
 static inline void at91_add_device_ecoreex4(void){
 	printk("at91_add_device_ecoreex4\n");
 	cs4_setup();
+	set200kclock();
 	platform_device_register(&som9260m_ecoreex_device);
 }