diff -urN -x CVS linux-2.6.20/arch/arm/boot/compressed/head.S linux-2.6.20-AT91/arch/arm/boot/compressed/head.S --- linux-2.6.20/arch/arm/boot/compressed/head.S 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/boot/compressed/head.S 2007-07-12 14:20:46.000000000 -0500 @@ -156,6 +156,11 @@ .text adr r0, LC0 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} +#ifdef CONFIG_RUNTIME_PHYS_OFFSET + and r10, pc, #0xf0000000 @ fix up zreladdr + add r4, r4, r10 +#endif + subs r0, r0, r1 @ calculate the delta offset @ if delta is zero, we are diff -urN -x CVS linux-2.6.20/arch/arm/boot/compressed/Makefile linux-2.6.20-AT91/arch/arm/boot/compressed/Makefile --- linux-2.6.20/arch/arm/boot/compressed/Makefile 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/boot/compressed/Makefile 2007-07-12 14:20:46.000000000 -0500 @@ -78,13 +78,10 @@ EXTRA_CFLAGS := -fpic EXTRA_AFLAGS := -# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via -# linker symbols. We only define initrd_phys and params_phys if the -# machine class defined the corresponding makefile variable. +# Supply ZRELADDR and PARAMS_PHYS to the decompressor via linker +# symbols. We only define params_phys if the machine class defined +# the corresponding makefile variable. LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR) -ifneq ($(INITRD_PHYS),) -LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS) -endif ifneq ($(PARAMS_PHYS),) LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS) endif diff -urN -x CVS linux-2.6.20/arch/arm/Kconfig linux-2.6.20-AT91/arch/arm/Kconfig --- linux-2.6.20/arch/arm/Kconfig 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/Kconfig 2007-07-12 14:20:45.000000000 -0500 @@ -113,6 +113,9 @@ help The base address of exception vectors. +config RUNTIME_PHYS_OFFSET + bool + source "init/Kconfig" menu "System Type" @@ -187,6 +190,7 @@ bool "EP93xx-based" select ARM_AMBA select ARM_VIC + select RUNTIME_PHYS_OFFSET help This enables support for the Cirrus EP93xx series of CPUs. @@ -930,6 +934,8 @@ source "drivers/input/Kconfig" +source "drivers/ioex/Kconfig" + source "drivers/char/Kconfig" source "drivers/i2c/Kconfig" diff -urN -x CVS linux-2.6.20/arch/arm/kernel/head.S linux-2.6.20-AT91/arch/arm/kernel/head.S --- linux-2.6.20/arch/arm/kernel/head.S 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/kernel/head.S 2007-07-12 14:20:45.000000000 -0500 @@ -43,8 +43,8 @@ .globl swapper_pg_dir .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 - .macro pgtbl, rd - ldr \rd, =(KERNEL_RAM_PADDR - 0x4000) + .macro pgtbl, rd, phys_offset + add \rd, \phys_offset, #(TEXT_OFFSET - 0x4000) .endm #ifdef CONFIG_XIP_KERNEL @@ -206,10 +206,22 @@ * Returns: * r0, r3, r6, r7 corrupted * r4 = physical page table address + * r5 = PHYS_OFFSET */ .type __create_page_tables, %function __create_page_tables: - pgtbl r4 @ page table address +#ifdef CONFIG_RUNTIME_PHYS_OFFSET + adr r5, stext + sub r5, r5, #TEXT_OFFSET @ r5 = phys_offset + + ldr r4, =(phys_offset - PAGE_OFFSET) + add r4, r4, r5 + str r5, [r4] @ save phys_offset +#else + mov r5, #PHYS_OFFSET @ r5 = phys_offset +#endif + + pgtbl r4, r5 @ r4 = page table address /* * Clear the 16K level 1 swapper page table @@ -255,8 +267,7 @@ * Then map first 1MB of ram in case it contains our boot params. */ add r0, r4, #PAGE_OFFSET >> 18 - orr r6, r7, #(PHYS_OFFSET & 0xff000000) - orr r6, r6, #(PHYS_OFFSET & 0x00e00000) + orr r6, r7, r5 str r6, [r0] #ifdef CONFIG_XIP_KERNEL diff -urN -x CVS linux-2.6.20/arch/arm/kernel/setup.c linux-2.6.20-AT91/arch/arm/kernel/setup.c --- linux-2.6.20/arch/arm/kernel/setup.c 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/kernel/setup.c 2007-07-12 14:20:45.000000000 -0500 @@ -59,6 +59,16 @@ extern int root_mountflags; extern void _stext, _text, _etext, __data_start, _edata, _end; +#ifdef CONFIG_RUNTIME_PHYS_OFFSET +/* + * The assignment is here solely to prevent this variable from ending + * up in bss. As the early startup code writes to it, we don't want it + * to be zeroed again later. + */ +unsigned long phys_offset = 0xdeadbeef; +EXPORT_SYMBOL(phys_offset); +#endif + unsigned int processor_id; unsigned int __machine_arch_type; EXPORT_SYMBOL(__machine_arch_type); @@ -749,7 +759,7 @@ { tag_size(tag_core), ATAG_CORE }, { 1, PAGE_SIZE, 0xff }, { tag_size(tag_mem32), ATAG_MEM }, - { MEM_SIZE, PHYS_OFFSET }, + { MEM_SIZE, 0 }, { 0, ATAG_NONE } }; @@ -770,6 +780,8 @@ struct machine_desc *mdesc; char *from = default_command_line; + init_tags.mem.start = PHYS_OFFSET; + setup_processor(); mdesc = setup_machine(machine_arch_type); machine_name = mdesc->name; diff -urN -x CVS linux-2.6.20/arch/arm/mach-at91rm9200/board-sam9260ek.c linux-2.6.20-AT91/arch/arm/mach-at91rm9200/board-sam9260ek.c --- linux-2.6.20/arch/arm/mach-at91rm9200/board-sam9260ek.c 2007-07-13 11:48:43.000000000 -0500 +++ linux-2.6.20-AT91/arch/arm/mach-at91rm9200/board-sam9260ek.c 2007-07-13 08:02:37.000000000 -0500 @@ -193,15 +193,25 @@ */ static struct mtd_partition __initdata ek_nand_partition[] = { { - .name = "Partition 1", + .name = "Boot Partition", .offset = 0, - .size = 256 * 1024, + .size = 64 * 2 * 1024, }, { - .name = "Partition 2", - .offset = 256 * 1024, - .size = MTDPART_SIZ_FULL, + .name = "UBoot Partition", + .offset = 64 * 2 * 1024, + .size = 64 * 14 * 1024, }, + { + .name = "Kernel Partition", + .offset = 64 * 16 * 1024, + .size = 64 * 48 * 1024, + }, + { + .name = "Disk Partition", + .offset = 64 * 64 * 1024, + .size = 64 * 256 * 1024, + }, }; static struct mtd_partition *nand_partitions(int size, int *num_partitions) diff -urN -x CVS linux-2.6.20/arch/arm/mach-at91rm9200/board-sam9260ek.c~ linux-2.6.20-AT91/arch/arm/mach-at91rm9200/board-sam9260ek.c~ --- linux-2.6.20/arch/arm/mach-at91rm9200/board-sam9260ek.c~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/mach-at91rm9200/board-sam9260ek.c~ 2007-07-12 14:43:37.000000000 -0500 @@ -0,0 +1,268 @@ +/* + * linux/arch/arm/mach-at91rm9200/board-sam9260ek.c + * + * Copyright (C) 2005 SAN People + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "generic.h" + + +/* + * Serial port configuration. + * 0 .. 5 = USART0 .. USART5 + * 6 = DBGU + */ +static struct at91_uart_config __initdata ek_uart_config = { + .console_tty = 0, /* ttyS0 */ + .nr_tty = 3, + .tty_map = { 6, 0, 1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */ +}; + +static void __init ek_map_io(void) +{ + /* Initialize processor: 18.432 MHz crystal */ + at91sam9260_initialize(18432000); + + /* Setup the serial ports and console */ + at91_init_serial(&ek_uart_config); +} + +static void __init ek_init_irq(void) +{ + at91sam9260_init_interrupts(NULL); +} + + +/* + * USB Host port + */ +static struct at91_usbh_data __initdata ek_usbh_data = { + .ports = 2, +}; + +/* + * USB Device port + */ +static struct at91_udc_data __initdata ek_udc_data = { + .vbus_pin = AT91_PIN_PC5, + .pullup_pin = 0, /* pull-up driven by UDC */ +}; + + +/* + * AT73C213 + */ +#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) +static struct atmel_at73c213_data at73c213_data; + +static u64 ssc_dmamask = 0xffffffffUL; +static struct resource ssc_resource[] = { + [0] = { + .start = AT91SAM9260_BASE_SSC, + .end = AT91SAM9260_BASE_SSC + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91SAM9260_ID_SSC, + .end = AT91SAM9260_ID_SSC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device at91sam9260_ssc_device = { + .name = "atmel_ssc_at73c213", + .id = -1, + .dev = { + .dma_mask = &ssc_dmamask, + .coherent_dma_mask = 0xffffffff, + .platform_data = &at73c213_data, + }, + .resource = ssc_resource, + .num_resources = ARRAY_SIZE(ssc_resource), +}; +void __init at91_add_device_ssc_at73c213(void) +{ + struct clk *at73_clk; + struct clk *ssc_clk; + struct clk *parent_clk; + + /* Set SSC1 IO */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* TK0 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* TF0 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* TD0 */ + + /* AT73C213 MCK Clock */ + at91_set_B_periph(AT91_PIN_PC1, 0); /* PCK0 */ + + at73_clk = clk_get(NULL, "pck0"); + parent_clk = clk_get(NULL, "plla"); + clk_set_parent(at73_clk, parent_clk); + clk_set_rate(at73_clk, 12416000); + clk_enable(at73_clk); + + ssc_clk = clk_get(NULL, "ssc_clk"); + clk_enable(ssc_clk); + + at73c213_data.ssc_div = 32; + at73c213_data.at73_mck = at73_clk; + + platform_device_register(&at91sam9260_ssc_device); +} +#else + void __init at91_add_device_ssc_at73c213(void) {} +#endif + +/* + * SPI devices. + */ +static struct spi_board_info ek_spi_devices[] = { +#if !defined(CONFIG_MMC_AT91) + { /* DataFlash chip */ + .modalias = "mtd_dataflash", + .chip_select = 1, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD) + { /* DataFlash card */ + .modalias = "mtd_dataflash", + .chip_select = 0, + .max_speed_hz = 15 * 1000 * 1000, + .bus_num = 0, + }, +#endif +#endif +#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) + { /* AT73C213 DAC */ + .modalias = "at73c213", + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .bus_num = 1, + }, +#endif +}; + + +/* + * MACB Ethernet device + */ +static struct __initdata at91_eth_data ek_macb_data = { + .phy_irq_pin = AT91_PIN_PA7, + .is_rmii = 1, +}; + + +/* + * NAND flash + */ +static struct mtd_partition __initdata ek_nand_partition[] = { + { + .name = "Partition 1", + .offset = 0, + .size = 2 * 1024 * 1024, + }, + { + .name = "Partition 2", + .offset = 2 * 1024 * 1024, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct mtd_partition *nand_partitions(int size, int *num_partitions) +{ + *num_partitions = ARRAY_SIZE(ek_nand_partition); + return ek_nand_partition; +} + +static struct at91_nand_data __initdata ek_nand_data = { + .ale = 21, + .cle = 22, +// .det_pin = ... not connected + .rdy_pin = AT91_PIN_PC13, + .enable_pin = AT91_PIN_PC14, + .partition_info = nand_partitions, +#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + + +/* + * MCI (SD/MMC) + */ +static struct at91_mmc_data __initdata ek_mmc_data = { + .slot_b = 1, + .wire4 = 1, +// .det_pin = ... not connected +// .wp_pin = ... not connected +// .vcc_pin = ... not connected +}; + +static void __init ek_board_init(void) +{ + /* Serial */ + at91_add_device_serial(); + /* USB Host */ + at91_add_device_usbh(&ek_usbh_data); + /* USB Device */ + at91_add_device_udc(&ek_udc_data); + /* SPI */ + at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); + /* NAND */ + at91_add_device_nand(&ek_nand_data); + /* Ethernet */ + at91_add_device_eth(&ek_macb_data); + /* MMC */ + at91_add_device_mmc(0, &ek_mmc_data); + /* AT73C213 & SSC port */ + at91_add_device_ssc_at73c213(); +} + +MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") + /* Maintainer: Atmel */ + .phys_io = AT91_BASE_SYS, + .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, + .boot_params = AT91_SDRAM_BASE + 0x100, + .timer = &at91sam926x_timer, + .map_io = ek_map_io, + .init_irq = ek_init_irq, + .init_machine = ek_board_init, +MACHINE_END diff -urN -x CVS linux-2.6.20/arch/arm/mach-ep93xx/ipac9302.c linux-2.6.20-AT91/arch/arm/mach-ep93xx/ipac9302.c --- linux-2.6.20/arch/arm/mach-ep93xx/ipac9302.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/mach-ep93xx/ipac9302.c 2007-07-12 14:20:45.000000000 -0500 @@ -0,0 +1,165 @@ +/* + * arch/arm/mach-ep93xx/ipac9302.c + * EMAC.Inc iPAC-9302 Support. + * + * Copyright (C) 2007 EMAC.Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/************************************************************ + * Flash Device + * Flash platform device used by the MTD platform driver + */ + +static struct physmap_flash_data ipac9302_flash_data = { + .width = 2, +}; + +static struct resource ipac9302_flash_resource = { + .start = 0x60000000, + .end = 0x60ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ipac9302_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ipac9302_flash_data, + }, + .num_resources = 1, + .resource = &ipac9302_flash_resource, +}; + +/************************************************************ + * Ethernet Device + * Ethernet platform device used bye the ep93xx ethernet platform driver + */ + +static struct ep93xx_eth_data ipac9302_eth_data = { + .phy_id = 1, +}; + +static struct resource ipac9302_eth_resource[] = { + { + .start = EP93XX_ETHERNET_PHYS_BASE, + .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_EP93XX_ETHERNET, + .end = IRQ_EP93XX_ETHERNET, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device ipac9302_eth_device = { + .name = "ep93xx-eth", + .id = -1, + .dev = { + .platform_data = &ipac9302_eth_data, + }, + .num_resources = 2, + .resource = ipac9302_eth_resource, +}; + +/************************************************************ + * IOEX Device + * Onboard EMAC I/O core platform device used by the ecoreex driver + */ +#define CS0_START ((unsigned long)0x10000) +#define CS0_END ((unsigned long)0xFFFFFFF) +#define CS0_LEN ((unsigned long)(CS0_END-CS0_START+1)) +#define CPLDKEY 0xF + +static struct ecoreex_data ipac9302_ecoreex_data = { + .key_offset = CPLDKEY, +}; + +static struct resource ipac9302_ecoreex_resource = { + .start = CS0_START, + .end = CS0_END, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ipac9302_ecoreex_device = { + .name = "ecoreex", + .id = -1, + .dev = { + .platform_data = &ipac9302_ecoreex_data, + }, + .num_resources = 1, + .resource = &ipac9302_ecoreex_resource, +}; + +/************************************************************ + * ep93xx pwm1 initialization routine (generic) + * TODO:move routines to generic ep93xx code. + */ +#define KEY (0xAA) +#define PONG (0x200) + +static inline void EP93XX_SYSUNLOCK(void){iowrite32(KEY,(void *)EP93XX_SYSCON_SWLOCK);} + +static void ep93xx_pwm1_enable(void){ + u32 devicecfg = ioread32((void *)EP93XX_SYSCON_DEVICE_CONFIG); + devicecfg|=PONG; + EP93XX_SYSUNLOCK(); + iowrite32(devicecfg,(void *)EP93XX_SYSCON_DEVICE_CONFIG); +} + +static inline void ep93xx_pwm_map(int num, const char *name){ + pwm_declare(); + ep93xx_pwm_device_create(EP93XX_PWM(num),name); +} + + + +/************************************************************ + * Linux Board initialization routine + */ +static void __init ipac9302_init_machine(void){ + ep93xx_init_devices(); + platform_device_register(&ipac9302_flash); + memcpy(ipac9302_eth_data.dev_addr,(void *)(EP93XX_ETHERNET_BASE + 0x50), 6); + platform_device_register(&ipac9302_eth_device); + platform_device_register(&ipac9302_ecoreex_device); + +#ifdef CONFIG_EP93XX_PWM + ep93xx_pwm1_enable(); + ep93xx_pwm_map(1,"ep93xx_pwm1"); +#endif +} + + +/************************************************************ + * standard mach structure for the iPac board + */ +MACHINE_START(IPAC9302, "EMAC.Inc iPac 9302 SBC") + .phys_io = EP93XX_APB_PHYS_BASE, + .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0xc0000100, + .map_io = ep93xx_map_io, + .init_irq = ep93xx_init_irq, + .timer = &ep93xx_timer, + .init_machine = ipac9302_init_machine, +MACHINE_END diff -urN -x CVS linux-2.6.20/arch/arm/mach-ep93xx/Kconfig linux-2.6.20-AT91/arch/arm/mach-ep93xx/Kconfig --- linux-2.6.20/arch/arm/mach-ep93xx/Kconfig 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/mach-ep93xx/Kconfig 2007-07-12 14:20:45.000000000 -0500 @@ -57,6 +57,11 @@ Say 'Y' here if you want your kernel to support the Technologic Systems TS-72xx board. +config MACH_IPAC9302 + bool "Support EMAC.Inc iPAC-9302 SBC" + help + Say 'Y' here if you want your kernel to support the + EMAC.Inc iPAC-9302 board. endmenu endif diff -urN -x CVS linux-2.6.20/arch/arm/mach-ep93xx/Kconfig.orig linux-2.6.20-AT91/arch/arm/mach-ep93xx/Kconfig.orig --- linux-2.6.20/arch/arm/mach-ep93xx/Kconfig.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/mach-ep93xx/Kconfig.orig 2007-07-12 14:20:45.000000000 -0500 @@ -0,0 +1,62 @@ +if ARCH_EP93XX + +menu "Cirrus EP93xx Implementation Options" + +config CRUNCH + bool "Support for MaverickCrunch" + help + Enable kernel support for MaverickCrunch. + +comment "EP93xx Platforms" + +config MACH_ADSSPHERE + bool "Support ADS Sphere" + help + Say 'Y' here if you want your kernel to support the ADS + Sphere board. + +config MACH_EDB9302 + bool "Support Cirrus Logic EDB9302" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9302 Evaluation Board. + +config MACH_EDB9302A + bool "Support Cirrus Logic EDB9302A" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9302A Evaluation Board. + +config MACH_EDB9312 + bool "Support Cirrus Logic EDB9312" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9312 Evaluation Board. + +config MACH_EDB9315 + bool "Support Cirrus Logic EDB9315" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9315 Evaluation Board. + +config MACH_EDB9315A + bool "Support Cirrus Logic EDB9315A" + help + Say 'Y' here if you want your kernel to support the Cirrus + Logic EDB9315A Evaluation Board. + +config MACH_GESBC9312 + bool "Support Glomation GESBC-9312-sx" + help + Say 'Y' here if you want your kernel to support the Glomation + GESBC-9312-sx board. + +config MACH_TS72XX + bool "Support Technologic Systems TS-72xx SBC" + help + Say 'Y' here if you want your kernel to support the + Technologic Systems TS-72xx board. + +endmenu + +endif diff -urN -x CVS linux-2.6.20/arch/arm/mach-ep93xx/Makefile linux-2.6.20-AT91/arch/arm/mach-ep93xx/Makefile --- linux-2.6.20/arch/arm/mach-ep93xx/Makefile 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/mach-ep93xx/Makefile 2007-07-12 14:20:45.000000000 -0500 @@ -14,3 +14,4 @@ obj-$(CONFIG_MACH_EDB9315A) += edb9315a.o obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o +obj-$(CONFIG_MACH_IPAC9302) += ipac9302.o \ No newline at end of file diff -urN -x CVS linux-2.6.20/arch/arm/mach-ep93xx/Makefile.boot linux-2.6.20-AT91/arch/arm/mach-ep93xx/Makefile.boot --- linux-2.6.20/arch/arm/mach-ep93xx/Makefile.boot 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/mach-ep93xx/Makefile.boot 2007-07-12 14:20:45.000000000 -0500 @@ -1,2 +1 @@ zreladdr-y := 0x00008000 -params_phys-y := 0x00000100 diff -urN -x CVS linux-2.6.20/arch/arm/tools/mach-types linux-2.6.20-AT91/arch/arm/tools/mach-types --- linux-2.6.20/arch/arm/tools/mach-types 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/arch/arm/tools/mach-types 2007-07-12 14:20:45.000000000 -0500 @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Tue Jan 16 16:52:56 2007 +# Last update: Tue Mar 6 16:46:14 2007 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1196,7 +1196,6 @@ ia_cpu_9200_2 MACH_IA_CPU_9200_2 IA_CPU_9200_2 1185 dimmrm9200 MACH_DIMMRM9200 DIMMRM9200 1186 pm9261 MACH_PM9261 PM9261 1187 -mx21 MACH_MX21 MX21 1188 ml7304 MACH_ML7304 ML7304 1189 ucp250 MACH_UCP250 UCP250 1190 intboard MACH_INTBOARD INTBOARD 1191 @@ -1242,3 +1241,45 @@ tecon_tmezon MACH_TECON_TMEZON TECON_TMEZON 1231 zylonite MACH_ZYLONITE ZYLONITE 1233 gene1270 MACH_GENE1270 GENE1270 1234 +zir2412 MACH_ZIR2412 ZIR2412 1235 +mx31lite MACH_MX31LITE MX31LITE 1236 +t700wx MACH_T700WX T700WX 1237 +vf100 MACH_VF100 VF100 1238 +nsb2 MACH_NSB2 NSB2 1239 +nxhmi_bb MACH_NXHMI_BB NXHMI_BB 1240 +nxhmi_re MACH_NXHMI_RE NXHMI_RE 1241 +n4100pro MACH_N4100PRO N4100PRO 1242 +sam9260 MACH_SAM9260 SAM9260 1243 +omap_treo600 MACH_OMAP_TREO600 OMAP_TREO600 1244 +indy2410 MACH_INDY2410 INDY2410 1245 +nelt_a MACH_NELT_A NELT_A 1246 +n311 MACH_N311 N311 1248 +at91sam9260vgk MACH_AT91SAM9260VGK AT91SAM9260VGK 1249 +at91leppe MACH_AT91LEPPE AT91LEPPE 1250 +at91lepccn MACH_AT91LEPCCN AT91LEPCCN 1251 +apc7100 MACH_APC7100 APC7100 1252 +stargazer MACH_STARGAZER STARGAZER 1253 +sonata MACH_SONATA SONATA 1254 +schmoogie MACH_SCHMOOGIE SCHMOOGIE 1255 +aztool MACH_AZTOOL AZTOOL 1256 +mioa701 MACH_MIOA701 MIOA701 1257 +sxni9260 MACH_SXNI9260 SXNI9260 1258 +mxc27520evb MACH_MXC27520EVB MXC27520EVB 1259 +armadillo5x0 MACH_ARMADILLO5X0 ARMADILLO5X0 1260 +mb9260 MACH_MB9260 MB9260 1261 +mb9263 MACH_MB9263 MB9263 1262 +ipac9302 MACH_IPAC9302 IPAC9302 1263 +cc9p9360js MACH_CC9P9360JS CC9P9360JS 1264 +gallium MACH_GALLIUM GALLIUM 1265 +msc2410 MACH_MSC2410 MSC2410 1266 +ghi270 MACH_GHI270 GHI270 1267 +davinci_leonardo MACH_DAVINCI_LEONARDO DAVINCI_LEONARDO 1268 +oiab MACH_OIAB OIAB 1269 +smdk6400 MACH_SMDK6400 SMDK6400 1270 +nokia_n800 MACH_NOKIA_N800 NOKIA_N800 1271 +greenphone MACH_GREENPHONE GREENPHONE 1272 +compex42x MACH_COMPEXWP18 COMPEXWP18 1273 +xmate MACH_XMATE XMATE 1274 +energizer MACH_ENERGIZER ENERGIZER 1275 +ime1 MACH_IME1 IME1 1276 +sweda_tms MACH_SWEDATMS SWEDATMS 1277 diff -urN -x CVS linux-2.6.20/config linux-2.6.20-AT91/config --- linux-2.6.20/config 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/config 2007-07-12 14:20:45.000000000 -0500 @@ -0,0 +1,1250 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.20 +# Fri Jun 22 13:14:15 2007 +# +CONFIG_ARM=y +# CONFIG_GENERIC_TIME is not set +CONFIG_MMU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_RUNTIME_PHYS_OFFSET=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +CONFIG_ARCH_EP93XX=y +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_OMAP is not set + +# +# Cirrus EP93xx Implementation Options +# +CONFIG_CRUNCH=y + +# +# EP93xx Platforms +# +# CONFIG_MACH_ADSSPHERE is not set +# CONFIG_MACH_EDB9302 is not set +# CONFIG_MACH_EDB9302A is not set +# CONFIG_MACH_EDB9312 is not set +# CONFIG_MACH_EDB9315 is not set +CONFIG_MACH_EDB9315A=y +# CONFIG_MACH_GESBC9312 is not set +# CONFIG_MACH_TS72XX is not set +# CONFIG_MACH_IPAC9302 is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM920T=y +CONFIG_CPU_32v4T=y +CONFIG_CPU_ABRT_EV4T=y +CONFIG_CPU_CACHE_V4WT=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +CONFIG_ARM_VIC=y + +# +# Bus support +# +CONFIG_ARM_AMBA=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +# CONFIG_PREEMPT is not set +# CONFIG_NO_IDLE_HZ is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x80000 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ZBOOT_ROM is not set +CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp" +# CONFIG_XIP_KERNEL is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +CONFIG_FPE_NWFPE_XP=y +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set +CONFIG_APM=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_NET_KEY=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +CONFIG_MTD_DEBUG=y +CONFIG_MTD_DEBUG_VERBOSE=3 +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=0x60000000 +CONFIG_MTD_PHYSMAP_LEN=0x0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# I2O device support +# + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_EP93XX_ETH=y +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set + +# +# Ethernet (1000 Mbit) +# + +# +# Ethernet (10000 Mbit) +# + +# +# Token Ring devices +# + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# IO expansion +# +CONFIG_ECOREEX=y +CONFIG_ECOREEX_TGPIO=y +CONFIG_ECOREEX_SGPWM=y + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_EP93XX_WATCHDOG=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_PCA_ISA is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set +CONFIG_SENSORS_EEPROM=y +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +CONFIG_I2C_DEBUG_CORE=y +CONFIG_I2C_DEBUG_ALGO=y +CONFIG_I2C_DEBUG_BUS=y +CONFIG_I2C_DEBUG_CHIP=y + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Misc devices +# +# CONFIG_TIFM_CORE is not set + +# +# misc device classes +# +CONFIG_GPIOCLASS=y +CONFIG_PWMCLASS=y +CONFIG_EP93XX_PWM=y + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_BANDWIDTH is not set +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# + +# +# USB HID Boot Protocol drivers +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +CONFIG_USB_RTL8150=y +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_AIRPRIME is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP2101 is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=y +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# Real Time Clock +# +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set + +# +# RTC drivers +# +# CONFIG_RTC_DRV_X1205 is not set +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_ISL1208=y +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +CONFIG_RTC_DRV_M48T86=y +CONFIG_RTC_DRV_EP93XX=y +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_TEST is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_DNOTIFY=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_SCHEDSTATS is not set +CONFIG_DEBUG_SLAB=y +# CONFIG_DEBUG_SLAB_LEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_LIST is not set +CONFIG_FRAME_POINTER=y +CONFIG_FORCED_INLINING=y +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +# CONFIG_CRYPTO is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +CONFIG_CRC32=y +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_IOMAP_COPY=y diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/ep93xx_ts1.c linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts1.c --- linux-2.6.20/drivers/input/touchscreen/ep93xx_ts1.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts1.c 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,748 @@ +/* + * linux/drivers/char/ep93xx_ts.c + * + * Copyright (C) 2003-2004 Cirrus Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * To customize for a new touchscreen, there are various macros that + * have to be set. If you allow UART_HACK_DEBUG to be defined, you + * will get real time ts data scrolling up your serial terminal + * screen that will help you empirically determine good values for these. + * + * + * These are used as trigger levels to know when we have pen up/down + * + * The rules: + * 1. TS_HEAVY_INV_PRESSURE < TS_LIGHT_INV_PRESSURE because these + * are Inverse pressure. + * 2. Any touch lighter than TS_LIGHT_INV_PRESSURE is a pen up. + * 3. Any touch heavier than TS_HEAVY_INV_PRESSURE is a pen down. + */ +#define TS_HEAVY_INV_PRESSURE (0x1000 - pressure_max) +#define TS_LIGHT_INV_PRESSURE (0x1000 - pressure_min) + +/* + * If the x, y, or inverse pressure changes more than these values + * between two succeeding points, the point is not reported. + */ +#define TS_MAX_VALID_PRESSURE_CHANGE (pressure_jitter) +#define TS_MAX_VALID_XY_CHANGE (xy_jitter) + +/* old defaults */ +#if 0 +#define TS_X_MIN 0 +#define TS_Y_MIN 0 +#define TS_X_MAX 0xfff +#define TS_Y_MAX 0xfff +#endif + +/* "improved" defaults */ +#define TS_X_MIN 0x2d9 +#define TS_Y_MIN 0xd0a +#define TS_X_MAX 0xd42 +#define TS_Y_MAX 0x2e0 + +static uint16_t pressure_min = 0x001; +static uint16_t pressure_max = 0x010; +static uint16_t pressure_jitter = 0x300; +static uint16_t xy_jitter = 0x100; +module_param(pressure_min, ushort, 0); +module_param(pressure_max, ushort, 0); +module_param(pressure_jitter, ushort, 0); +module_param(xy_jitter, ushort, 0); +MODULE_PARM_DESC(pressure_min, "Minimum pressure (0 - 4095)"); +MODULE_PARM_DESC(pressure_max, "Maximum pressure (0 - 4095)"); +MODULE_PARM_DESC(pressure_jitter, "Minimum pressure jitter (0 - 4095)"); +MODULE_PARM_DESC(xy_jitter, "Minimum X-Y jitter (0 - 4095)"); + +/* This is the minimum Z1 Value that is valid. */ +#define MIN_Z1_VALUE 0x50 + +/* + * Settling delay for taking each ADC measurement. Increase this + * if ts is jittery. + */ +#define EP93XX_TS_ADC_DELAY_USEC 2000 + +/* Delay between TS points. */ + +#define EP93XX_TS_PER_POINT_DELAY_USEC 10000 + +/*----------------------------------------------------------------------------- + * Debug messaging thru the UARTs + *----------------------------------------------------------------------------- + * + * Hello there! Are you trying to get this driver to work with a new + * touschscreen? Turn this on and you will get useful info coming + * out of your serial port. + */ + +/* #define PRINT_CALIBRATION_FACTORS */ +#ifdef PRINT_CALIBRATION_FACTORS +#define UART_HACK_DEBUG 1 +int iMaxX = 0, iMaxY = 0, iMinX = 0xfff, iMinY = 0xfff; +#endif + +/* + * For debugging, let's spew messages out serial port 1 or 3 at 57,600 baud. + */ +#undef UART_HACK_DEBUG +#if defined(UART_HACK_DEBUG) && defined (CONFIG_DEBUG_LL) +static char szBuf[256]; +void UARTWriteString(char *msg); +extern void printascii(const char *msg); +#define DPRINTK( x... ) \ + sprintf( szBuf, ##x ); \ + printascii( szBuf ); +#else +#define DPRINTK( x... ) +#endif + +#define TSSETUP_DEFAULT ( TSSETUP_NSMP_32 | TSSETUP_DEV_64 | \ + ((128<= TS_LIGHT_INV_PRESSURE) { + DPRINTK(" -- up \n"); + bCurrentPenDown = 0; +/* input_report_key(dev, BTN_TOUCH, 0); */ + input_report_abs(dev, ABS_PRESSURE, 0); + input_sync(dev); + TS_Hardware_Scan_Mode(); + return; + } + /* + * Hystheresis: + * If the pen pressure is hard enough to be less than the 'min' OR + * the pen is already down and is still less than the 'max'... + */ + if ((uiInvPressure < TS_HEAVY_INV_PRESSURE) || + (bCurrentPenDown && (uiInvPressure < TS_LIGHT_INV_PRESSURE))) { + if (bCurrentPenDown) { + /* + * If pen was previously down, check the difference between + * the last sample and this one... if the difference between + * samples is too great, ignore the sample. + */ + uiXDiff = abs(guiLastX - sTouch.uiX); + uiYDiff = abs(guiLastY - sTouch.uiY); + uiInvPressureDiff = + abs(guiLastInvPressure - uiInvPressure); + + if ((uiXDiff < TS_MAX_VALID_XY_CHANGE) && + (uiYDiff < TS_MAX_VALID_XY_CHANGE) && + (uiInvPressureDiff < TS_MAX_VALID_PRESSURE_CHANGE)) + { + DPRINTK(" -- valid(two) \n"); + bValidPoint = 1; + } else { + DPRINTK(" -- INvalid(two) \n"); + } + } else { + DPRINTK(" -- valid \n"); + bValidPoint = 1; + } + + /* + * If either the pen was put down or dragged make a note of it. + */ + if (bValidPoint) { + guiLastX = sTouch.uiX; + guiLastY = sTouch.uiY; + guiLastInvPressure = uiInvPressure; + bCurrentPenDown = 1; + input_report_abs(dev, ABS_X, sTouch.uiX); + input_report_abs(dev, ABS_Y, sTouch.uiY); +/* input_report_key(dev, BTN_TOUCH, 1); */ + input_report_abs(dev, ABS_PRESSURE, 1); + input_sync(dev); + } + + TS_Soft_Scan_Mode(); + return; + } + + DPRINTK(" -- fallout \n"); + TS_Hardware_Scan_Mode(); +} + +static void ep93xx_ts_set_direct(unsigned int uiADCSwitch) +{ + unsigned int uiResult; + + /* Set the switch settings in the direct register. */ + writel(0xaa, TSSWLock); + writel(uiADCSwitch, TSDirect); + + /* Read and throw away the first sample. */ + do { + uiResult = readl(TSXYResult); + } while (!(uiResult & TSXYRESULT_SDR)); + +} + +static unsigned int ADCGetData(unsigned int uiSamples, unsigned int uiMaxDiff) +{ + unsigned int uiResult, uiValue, uiCount, uiLowest, uiHighest, uiSum, + uiAve; + + do { + /* Initialize our values. */ + uiLowest = 0xfffffff; + uiHighest = 0; + uiSum = 0; + + for (uiCount = 0; uiCount < uiSamples; uiCount++) { + /* Read the touch screen four more times and average. */ + do { + uiResult = readl(TSXYResult); + } while (!(uiResult & TSXYRESULT_SDR)); + + uiValue = + (uiResult & TSXYRESULT_AD_MASK) >> + TSXYRESULT_AD_SHIFT; + uiValue = + ((uiValue >> 4) + + ((1 + + TSXYRESULT_X_MASK) >> 1)) & TSXYRESULT_X_MASK; + + /* Add up the values. */ + uiSum += uiValue; + + /* Get the lowest and highest values. */ + if (uiValue < uiLowest) + uiLowest = uiValue; + + if (uiValue > uiHighest) + uiHighest = uiValue; + + } + + } while ((uiHighest - uiLowest) > uiMaxDiff); + + /* Calculate the Average value. */ + uiAve = uiSum / uiSamples; + + return uiAve; +} + +/** + * CalculateInvPressure + * + * Is the Touch Valid. Touch is not valid if the X or Y value is not + * in range and the pressure is not enough. + * + * Touch resistance can be measured by the following formula: + * + * Rx * X * Z2 + * Rtouch = --------- * (-- - 1) + * 4096 Z1 + * + * This is simplified in the ration of Rtouch to Rx. The lower the value, the + * higher the pressure. + * + * Z2 + * InvPressure = X * (-- - 1) + * Z1 + */ +static unsigned int CalculateInvPressure(void) +{ + unsigned int uiInvPressure; + + /* Check to see if the point is valid. */ + if (sTouch.uiZ1 < MIN_Z1_VALUE) + uiInvPressure = 0x10000; + + /* Can omit the pressure calculation if you need to get rid of the division. */ + else { + uiInvPressure = + ((sTouch.uiX * sTouch.uiZ2) / sTouch.uiZ1) - sTouch.uiX; + } + + return uiInvPressure; +} + +/** + * TS_Hardware_Scan_Mode + * Enables the ep93xx ts scanning engine so that when the pen goes down + * we will get an interrupt. + */ +static void TS_Hardware_Scan_Mode(void) +{ + unsigned int uiDevCfg; + + DPRINTK("S\n"); + + /* Disable the soft scanning engine. */ + sTouch.state = TS_STATE_STOPPED; + Stop_Timer2(); + + /* + * Clear the TIN (Touchscreen INactive) bit so we can go to + * automatic scanning mode. + */ + uiDevCfg = readl(SYSCON_DEVCFG); + SysconSetLocked(SYSCON_DEVCFG, + ep93xx_SYSCON_DEVCFG(uiDevCfg & ~SYSCON_DEVCFG_TIN)); + + /* + * Enable the touch screen scanning state machine by setting + * the ENABLE bit. + */ + writel((TSSETUP_DEFAULT | TSSETUP_ENABLE), TSSetup); + + /* Set the flag to show that we are in interrupt mode. */ + gScanningMode = TS_MODE_HARDWARE_SCAN; + + /* Initialize TSSetup2 register. */ + writel(TSSETUP2_DEFAULT, TSSetup2); + +} + +/** + * TS_Soft_Scan_Mode - Set the touch screen to manual polling mode. + */ +static void TS_Soft_Scan_Mode(void) +{ + unsigned int uiDevCfg; + + DPRINTK("M\n"); + + if (gScanningMode != TS_MODE_SOFT_SCAN) { + /* + * Disable the touch screen scanning state machine by clearing + * the ENABLE bit. + */ + writel(TSSETUP_DEFAULT, TSSetup); + + /* Set the TIN bit so we can do manual touchscreen polling. */ + uiDevCfg = readl(SYSCON_DEVCFG); + SysconSetLocked(SYSCON_DEVCFG, + ep93xx_SYSCON_DEVCFG(uiDevCfg | + SYSCON_DEVCFG_TIN)); + } + /* Set the switch register up for the first ADC reading */ + ep93xx_ts_set_direct(sSwitchSettings.uiSwitchZ1); + + /* + * Initialize our software state machine to know which ADC + * reading to take + */ + sTouch.state = TS_STATE_Z1; + + /* + * Set the timer so after a mSec or two settling delay it will + * take the first ADC reading. + */ + Set_Timer2_uSec(EP93XX_TS_PER_POINT_DELAY_USEC); + + /* Note that we are in sw scanning mode not hw scanning mode. */ + gScanningMode = TS_MODE_SOFT_SCAN; + +} + +static void Set_Timer2_uSec(unsigned int uiDelay_uSec) +{ + unsigned int uiClockTicks; + + /* + * Stop timer 2 + */ + writel(0, TIMER2CONTROL); + + uiClockTicks = ((uiDelay_uSec * 508) + 999) / 1000; + writel(uiClockTicks, TIMER2LOAD); + writel(uiClockTicks, TIMER2VALUE); + + /* + * Set up Timer 2 for 508 kHz clock and periodic mode. + */ + writel(0xC8, TIMER2CONTROL); + +} + +static void Stop_Timer2(void) +{ + writel(0, TIMER2CONTROL); +} + +static struct input_dev *ep93xx_ts_dev; + +static int __init ep93xx_ts_init(void) +{ + ep93xx_ts_dev = input_allocate_device(); + if (!ep93xx_ts_dev) { + printk(KERN_ERR "ep93xx_ts_dev: not enough memory for input device\n"); + return -ENOMEM; + } + + ep93xx_ts_dev->evbit[0] = BIT(EV_KEY) | BIT(EV_ABS); + ep93xx_ts_dev->keybit[LONG(BTN_TOUCH)] = BIT(BTN_TOUCH); + ep93xx_ts_dev->keybit[LONG(BTN_RAW)] = BIT(BTN_RAW); + + /* untested, I haven't got a touchscreen (yet) :( */ + input_set_abs_params(ep93xx_ts_dev, ABS_X, 0, 4095, 0, 0); + input_set_abs_params(ep93xx_ts_dev, ABS_Y, 0, 4095, 0, 0); + input_set_abs_params(ep93xx_ts_dev, ABS_PRESSURE, 0, 1, 0, 0); + + ep93xx_ts_dev->open = ep93xx_ts_open; + ep93xx_ts_dev->close = ep93xx_ts_close; + ep93xx_ts_dev->name = "Cirrus Logic EP93xx Touchscreen"; + ep93xx_ts_dev->phys = "ep93xx_ts/input0"; + ep93xx_ts_dev->id.bustype = BUS_HOST; + ep93xx_ts_dev->id.vendor = PCI_VENDOR_ID_CIRRUS; + ep93xx_ts_dev->id.product = 0x9300; + + input_set_abs_params(ep93xx_ts_dev, ABS_X, TS_X_MIN, TS_X_MAX, 0, 0); + input_set_abs_params(ep93xx_ts_dev, ABS_Y, TS_Y_MIN, TS_Y_MAX, 0, 0); + input_register_device(ep93xx_ts_dev); + + sTouch.state = TS_STATE_STOPPED; + gScanningMode = TS_MODE_UN_INITIALIZED; + + printk(KERN_NOTICE + "EP93xx touchscreen driver configured for 4-wire operation\n"); + return 0; +} + +static void __exit ep93xx_ts_exit(void) +{ + input_unregister_device(ep93xx_ts_dev); +} + +module_init(ep93xx_ts_init); +module_exit(ep93xx_ts_exit); + +MODULE_DESCRIPTION("Cirrus EP93xx touchscreen driver"); +MODULE_SUPPORTED_DEVICE("touchscreen/ep93xx"); diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/ep93xx_ts.c linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts.c --- linux-2.6.20/drivers/input/touchscreen/ep93xx_ts.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts.c 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,1119 @@ +/* + * linux/drivers/char/ep93xx_ts.c + * + * Copyright (C) 2003-2004 Cirrus Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// To customize for a new touchscreen, there are various macros that +// have to be set. If you allow UART_HACK_DEBUG to be defined, you +// will get real time ts data scrolling up your serial terminal +// screen that will help you empirically determine good values for these. +// + +// +// These are used as trigger levels to know when we have pen up/down +// +// The rules: +// 1. TS_HEAVY_INV_PRESSURE < TS_LIGHT_INV_PRESSURE because these +// are Inverse pressure. +// 2. Any touch lighter than TS_LIGHT_INV_PRESSURE is a pen up. +// 3. Any touch heavier than TS_HEAVY_INV_PRESSURE is a pen down. +// +#define TS_HEAVY_INV_PRESSURE 0xFE0 //C00 +#define TS_LIGHT_INV_PRESSURE 0xFFF //e00 + +// +// If the x, y, or inverse pressure changes more than these values +// between two succeeding points, the point is not reported. +// +#define TS_MAX_VALID_XY_CHANGE 0x300 +#define TS_MAX_VALID_PRESSURE_CHANGE 0x100 + +// +// This is the minimum Z1 Value that is valid. +// +#define MIN_Z1_VALUE 0x50 + +// +// Settling delay for taking each ADC measurement. Increase this +// if ts is jittery. +// +#define EP93XX_TS_ADC_DELAY_USEC 2000 + +// +// Delay between TS points. +// +#define EP93XX_TS_PER_POINT_DELAY_USEC 10000 + +//----------------------------------------------------------------------------- +// Debug messaging thru the UARTs +//----------------------------------------------------------------------------- +/* + * Hello there! Are you trying to get this driver to work with a new + * touschscreen? Turn this on and you will get useful info coming + * out of your serial port. + */ +#define PRINT_CALIBRATION_FACTORS //NZG mod + + +#ifdef PRINT_CALIBRATION_FACTORS +#define UART_HACK_DEBUG 1 +int iMaxX=0, iMaxY=0, iMinX = 0xfff, iMinY = 0xfff; +#endif + +/* + * For debugging, let's spew messages out serial port 1 or 3 at 57,600 baud. + */ +//#define UART_HACK_DEBUG 1 +#if 0 +#ifdef UART_HACK_DEBUG +static char szBuf[256]; +void UARTWriteString(char * msg); +#define DPRINTK( x... ) \ + sprintf( szBuf, ##x ); \ + UARTWriteString( szBuf ); +#else +static char szBuf[256]; +#define DPRINTK( x... ) \ + sprintf( szBuf, ##x ); \ + printk( szBuf ); +#endif +#endif // 0 + +#ifdef UART_HACK_DEBUG //NZG mod, use printk instead +#define DPRINTK(fmt, args...) printk(fmt, ## args) +#else +#define DPRINTK( x... ) +#endif + +//----------------------------------------------------------------------------- +// A few more macros... +//----------------------------------------------------------------------------- +#define TSSETUP_DEFAULT ( TSSETUP_NSMP_32 | TSSETUP_DEV_64 | \ + ((128<>2] & 0x20); + + // send a char to the uart + pDebugUART[0] = value; +} + +void UARTWriteString(char * msg) +{ + int index = 0; + unsigned int uiTemp; + + //if((pDebugUART[0x14>>2] & 0x1) == 0) + if( bUartInitialized == 0 ) + { + uiTemp = inl(SYSCON_DEVCFG); + uiTemp |= SYSCON_DEVCFG_U1EN; + //uiTemp |= SYSCON_DEVCFG_U3EN; + SysconSetLocked(SYSCON_DEVCFG, uiTemp); + pDebugUART[0x10>>2] = 0xf; + pDebugUART[0xc>>2] = 0; + pDebugUART[0x8>>2] = 0x70; + pDebugUART[0x14>>2] = 0x1; + bUartInitialized = 1; + } + while (msg[index] != 0) + { + if (msg[index] == '\n') + { + SendChar('\r'); + SendChar('\n'); + } + else + { + SendChar(msg[index]); + } + index++; + } +} +#endif // UART_HACK_DEBUG + +/* + * ep93xx_ts_isr + */ +static irqreturn_t ep93xx_ts_isr(int irq, void *dev_id, struct pt_regs *regs) +{ + DPRINTK("isr\n"); + + // + // Note that we don't clear the interrupt here. The interrupt + // gets cleared in TS_Soft_Scan_Mode when the TS ENABLE + // bit is cleared. + // + + // + // Set the ts to manual polling mode and schedule a callback. + // That way we can return from the isr in a reasonable amount of + // time and process the touch in the callback after a brief delay. + // + TS_Soft_Scan_Mode(); + + return(IRQ_HANDLED); +} + +/* + * Save the current ts 'event' in an atomic fashion. + */ +static void ee93xx_ts_evt_add( int buttons, int iX, int iY, int iPressure ) +{ + +#ifdef PRINT_CALIBRATION_FACTORS + if( iX > iMaxX ) iMaxX = iX; + if( iX < iMinX ) iMinX = iX; + if( iY > iMaxY ) iMaxY = iY; + if( iY < iMinY ) iMinY = iY; +#endif + + //DPRINTK("cb\n"); + /* + * Note the event, but use spinlocks to keep it from getting + * halfway read if we get interrupted. + */ + + spin_lock(&event_buffer_lock); + gSample.currentX = iX; + gSample.currentY = iY; + gSample.currentButton = buttons; + gSample.currentPressure = iPressure; + bFreshTouchData = 1; + do_gettimeofday(&gSample.currentTime); + + spin_unlock(&event_buffer_lock); + + kill_fasync(&ep93xx_fasync, SIGIO, POLL_IN); + wake_up_interruptible(&queue); + +} + + +static ssize_t ep93xx_ts_read(struct file *filp, char *buf, size_t count, loff_t *l) +{ + + unsigned short data[3]; + struct ts_sample ts_data; + int iReturn = -EFAULT; + +#ifdef PRINT_CALIBRATION_FACTORS + static int lala=0; + if( bFreshTouchData && (lala++ > 9) ) + { + //DPRINTK("%4d, %4d - range [%4d to %4d],[%4d to %4d]\n",f, currentY, iMinX, iMaxX, iMinY, iMaxY ); + DPRINTK("%4d, %4d - range [%4d to %4d],[%4d to %4d]\n",gSample.currentX, gSample.currentY, iMinX, iMaxX, iMinY, iMaxY );//NZG mod + lala = 0; + } +#endif + if( !bFreshTouchData) + { + iReturn = 0; + } + else if( (count == sizeof(data)) ) + { + spin_lock_irq(&event_buffer_lock); + bFreshTouchData = 0; + data[0] = gSample.currentX; + data[1] = gSample.currentY; + data[2] = gSample.currentButton; + + spin_unlock_irq(&event_buffer_lock); + + if (copy_to_user(buf, data, sizeof data)) + { + DPRINTK("read returning error 1\n"); + return -EFAULT; + } + + count -= sizeof(data); + + /* return the # of bytes that got read */ + iReturn = sizeof(data) ; + DPRINTK("read returning %d bytes read\n", iReturn); + } + else if (count == sizeof(struct ts_sample) ) + { + spin_lock_irq(&event_buffer_lock); + bFreshTouchData = 0; + ts_data.x = gSample.currentX; + ts_data.y = gSample.currentY; + ts_data.pressure = gSample.currentPressure; + ts_data.tv = gSample.currentTime; + spin_unlock_irq(&event_buffer_lock); + + if (copy_to_user(buf, &ts_data, sizeof(struct ts_sample))) + { + DPRINTK("read returning error\n"); + iReturn = -EFAULT; + } + else + { + count -= sizeof(ts_data); + iReturn = sizeof(ts_data); + DPRINTK("read returning %d as sizeof(ts_data)\n", iReturn); + } + + } + + return iReturn; +} + +static unsigned int ep93xx_ts_poll(struct file *filp, poll_table *wait) +{ + // printk("ep93xx_ts_poll\n"); + poll_wait(filp, &queue, wait); + + if( bFreshTouchData ) + { + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int ep93xx_ts_open(struct inode *inode, struct file *filp) +{ + DPRINTK("ep93xx_ts_open\n"); + + if( down_trylock(&open_sem) ) + { + return -EBUSY; + } + + ep93xx_ts_setup(); + + return 0; +} + +/* + * Asynchronous I/O support. + */ +static int ep93xx_ts_fasync(int fd, struct file *filp, int on) +{ + int retval; + + retval = fasync_helper(fd, filp, on, &ep93xx_fasync); + if (retval < 0) + { + return retval; + } + + return 0; +} + +static int ep93xx_ts_release(struct inode *inode, struct file *filp) +{ + Stop_Timer2(); + + /* + * Call our async I/O support to request that this file + * cease to be used for async I/O. + */ + ep93xx_ts_fasync(-1, filp, 0); + + ep93xx_ts_shutdown(); + + up(&open_sem); + + return 0; +} + +static ssize_t ep93xx_ts_write(struct file *file, const char *buffer, size_t count, + loff_t *ppos) +{ + return -EINVAL; +} + + +static int ep93xx_ts_ioctl(struct inode *inode, struct file *file, uint command, ulong u) +{ + static const int version = EV_VERSION; + static const u_int32_t bit =(1 << EV_ABS); + static const u_int32_t absbit = (1 << ABS_X) | (1 << ABS_Y) | (1 << ABS_PRESSURE); + int iReturn ; + int i = 0; + + switch(command) + { + case EVIOCGVERSION: + DPRINTK("ep93xx_ts_ioctl command = EVIOCGVERSION\r\n"); + i = copy_to_user((void __user *)u, (void *)version, sizeof(version)); + iReturn = i ? -EFAULT : 0; + break; + + case EVIOCGBIT(0,sizeof(u_int32_t) * 8) : + DPRINTK("ep93xx_ts_ioctl command = EVIOCGBIT(0,sizeof(uint32) * 8)\r\n"); + i = copy_to_user((void __user *)u, (void *)bit, sizeof(bit)); + iReturn = i ? -EFAULT : 0; + break; + + case EVIOCGBIT(EV_ABS, sizeof(absbit) * 8): + DPRINTK("ep93xx_ts_ioctl command = EVIOCGBIT(0,sizeof(uint32) * 8)\r\n"); + copy_to_user((void __user *)u, (void *)absbit, sizeof(absbit)); + iReturn = i ? -EFAULT : 0; + break; + default: + DPRINTK(" ep93xx_ts_ioctl unknown command = %d\n",u); + iReturn = -1; + break; + } + + return iReturn; +} + +static struct file_operations ep93xx_ts_fops = { + owner: THIS_MODULE, + read: ep93xx_ts_read, + write: ep93xx_ts_write, + poll: ep93xx_ts_poll, + open: ep93xx_ts_open, + ioctl: ep93xx_ts_ioctl, + release: ep93xx_ts_release, + fasync: ep93xx_ts_fasync, +}; + +static struct miscdevice ep93xx_ts_miscdev = +{ + EP93XX_TS_MINOR, + "ep93xx_ts", + &ep93xx_ts_fops +}; + +void ep93xx_ts_setup(void) +{ + unsigned int uiKTDIV, uiTSXYMaxMin; + DPRINTK("ep93xx_hw_setup\n"); + + /* + * Set the TSEN bit in KTDIV so that we are enabling the clock + * for the touchscreen. + */ + uiKTDIV = inl(SYSCON_KTDIV); + uiKTDIV |= SYSCON_KTDIV_TSEN; + SysconSetLocked( SYSCON_KTDIV, uiKTDIV ); + + // + // Program the TSSetup and TSSetup2 registers. + // + outl( TSSETUP_DEFAULT, TSSetup ); + outl( TSSETUP2_DEFAULT, TSSetup2 ); + + // + // Set the the touch settings. + // + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDischarge, TSDirect ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDischarge, TSDischarge ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiSwitchZ1, TSXSample ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiSwitchZ2, TSYSample ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDetect, TSDetect ); + + // + // X,YMin set to 0x40 = have to drag that many pixels for a new irq. + // X,YMax set to 0x40 = 1024 pixels is the maximum movement within the + // time scan limit. + // + uiTSXYMaxMin = (50 << TSMAXMIN_XMIN_SHIFT) & TSMAXMIN_XMIN_MASK; + uiTSXYMaxMin |= (50 << TSMAXMIN_YMIN_SHIFT) & TSMAXMIN_YMIN_MASK; + uiTSXYMaxMin |= (0xff << TSMAXMIN_XMAX_SHIFT) & TSMAXMIN_XMAX_MASK; + uiTSXYMaxMin |= (0xff << TSMAXMIN_YMAX_SHIFT) & TSMAXMIN_YMAX_MASK; + outl( uiTSXYMaxMin, TSXYMaxMin ); + + bCurrentPenDown = 0; + bFreshTouchData = 0; + guiLastX = 0; + guiLastY = 0; + guiLastInvPressure = 0xffffff; + + // + // Enable the touch screen scanning engine. + // + TS_Hardware_Scan_Mode(); +} + +/* + * ep93xx_ts_shutdown + * + */ +static void +ep93xx_ts_shutdown(void) +{ + unsigned int uiKTDIV; + + DPRINTK("ep93xx_ts_shutdown\n"); + + sTouch.state = TS_STATE_STOPPED; + Stop_Timer2(); + + /* + * Disable the scanning engine. + */ + outl( 0, TSSetup ); + outl( 0, TSSetup2 ); + + /* + * Clear the TSEN bit in KTDIV so that we are disabling the clock + * for the touchscreen. + */ + uiKTDIV = inl(SYSCON_KTDIV); + uiKTDIV &= ~SYSCON_KTDIV_TSEN; + SysconSetLocked( SYSCON_KTDIV, uiKTDIV ); + +} /* ep93xx_ts_shutdown */ + +static irqreturn_t ep93xx_timer2_isr(int irq, void *dev_id, struct pt_regs *regs) +{ + DPRINTK("state: %d\n", (int)sTouch.state ); + + switch( sTouch.state ) + { + case TS_STATE_STOPPED: + TS_Hardware_Scan_Mode(); + break; + + // + // Get the Z1 value for pressure measurement and set up + // the switch register for getting the Z2 measurement. + // + case TS_STATE_Z1: + Set_Timer2_uSec( EP93XX_TS_ADC_DELAY_USEC ); + sTouch.uiZ1 = ADCGetData( 2, 200 ); + ep93xx_ts_set_direct( sSwitchSettings.uiSwitchZ2 ); + sTouch.state = TS_STATE_Z2; + break; + + // + // Get the Z2 value for pressure measurement and set up + // the switch register for getting the Y measurement. + // + case TS_STATE_Z2: + sTouch.uiZ2 = ADCGetData( 2, 200 ); + ep93xx_ts_set_direct( sSwitchSettings.uiYSample ); + sTouch.state = TS_STATE_Y; + break; + + // + // Get the Y value and set up the switch register for + // getting the X measurement. + // + case TS_STATE_Y: + sTouch.uiY = ADCGetData( 4, 20 ); + ep93xx_ts_set_direct( sSwitchSettings.uiXSample ); + sTouch.state = TS_STATE_X; + break; + + // + // Read the X value. This is the last of the 4 adc values + // we need so we continue on to process the data. + // + case TS_STATE_X: + Stop_Timer2(); + + sTouch.uiX = ADCGetData( 4, 20 ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDischarge, TSDirect ); + + sTouch.state = TS_STATE_DONE; + + /* + * Process this set of ADC readings. + */ + ProcessPointData(); + + break; + + + // + // Shouldn't get here. But if we do, we can recover... + // + case TS_STATE_DONE: + TS_Hardware_Scan_Mode(); + break; + } + + // + // Clear the timer2 interrupt. + // + outl( 1, TIMER2CLEAR ); + return(IRQ_HANDLED); +} + +/*--------------------------------------------------------------------- + * ProcessPointData + * + * This routine processes the ADC data into usable point data and then + * puts the driver into hw or sw scanning mode before returning. + * + * We calculate inverse pressure (lower number = more pressure) then + * do a hystheresis with the two pressure values 'light' and 'heavy'. + * + * If we are above the light, we have pen up. + * If we are below the heavy we have pen down. + * As long as the pressure stays below the light, pen stays down. + * When we get above the light again, pen goes back up. + * + */ +static void ProcessPointData(void) +{ + int bValidPoint = 0; + unsigned int uiXDiff, uiYDiff, uiInvPressureDiff; + unsigned int uiInvPressure; + + // + // Calculate the current pressure. + // + uiInvPressure = CalculateInvPressure(); + + DPRINTK(" X=0x%x, Y=0x%x, Z1=0x%x, Z2=0x%x, InvPressure=0x%x", + sTouch.uiX, sTouch.uiY, sTouch.uiZ1, sTouch.uiZ2, uiInvPressure ); + + // + // If pen pressure is so light that it is greater than the 'max' setting + // then we consider this to be a pen up. + // + if( uiInvPressure >= TS_LIGHT_INV_PRESSURE ) + { + DPRINTK(" -- up \n"); + bCurrentPenDown = 0; + ee93xx_ts_evt_add( 0, guiLastX, guiLastY, 0 ); + TS_Hardware_Scan_Mode(); + return; + } + + // + // Hystheresis: + // If the pen pressure is hard enough to be less than the 'min' OR + // the pen is already down and is still less than the 'max'... + // + if( (uiInvPressure < TS_HEAVY_INV_PRESSURE) || + ( bCurrentPenDown && (uiInvPressure < TS_LIGHT_INV_PRESSURE) ) ) + { + if( bCurrentPenDown ) + { + // + // If pen was previously down, check the difference between + // the last sample and this one... if the difference between + // samples is too great, ignore the sample. + // + uiXDiff = abs(guiLastX - sTouch.uiX); + uiYDiff = abs(guiLastY - sTouch.uiY); + uiInvPressureDiff = abs(guiLastInvPressure - uiInvPressure); + + if( (uiXDiff < TS_MAX_VALID_XY_CHANGE) && (uiYDiff < TS_MAX_VALID_XY_CHANGE) && + (uiInvPressureDiff < TS_MAX_VALID_PRESSURE_CHANGE) ) + { + DPRINTK(" -- valid(two) \n"); + bValidPoint = 1; + } + else + { + DPRINTK(" -- INvalid(two) \n"); + } + } + else + { + DPRINTK(" -- valid \n"); + bValidPoint = 1; + } + + /* + * If either the pen was put down or dragged make a note of it. + */ + if( bValidPoint ) + { + guiLastX = sTouch.uiX; + guiLastY = sTouch.uiY; + guiLastInvPressure = uiInvPressure; + bCurrentPenDown = 1; + DPRINTK("calling ee93xx_ts_evt_add\n"); + ee93xx_ts_evt_add( 1, sTouch.uiX, sTouch.uiY, (0x7000000 /uiInvPressure) ); + } + + TS_Soft_Scan_Mode(); + return; + } + + DPRINTK(" -- fallout \n"); + TS_Hardware_Scan_Mode(); +} + +static void ep93xx_ts_set_direct( unsigned int uiADCSwitch ) +{ + unsigned int uiResult; + + // + // Set the switch settings in the direct register. + // + outl( 0xaa, TSSWLock ); + outl( uiADCSwitch, TSDirect ); + + // + // Read and throw away the first sample. + // + do { + uiResult = inl(TSXYResult); + } while( !(uiResult & TSXYRESULT_SDR) ); + +} + +static unsigned int ADCGetData +( + unsigned int uiSamples, + unsigned int uiMaxDiff +) +{ + unsigned int uiResult, uiValue, uiCount, uiLowest, uiHighest, uiSum, uiAve; + + do + { + // + //Initialize our values. + // + uiLowest = 0xfffffff; + uiHighest = 0; + uiSum = 0; + + for( uiCount = 0 ; uiCount < uiSamples ; uiCount++ ) + { + // + // Read the touch screen four more times and average. + // + do { + uiResult = inl(TSXYResult); + } while( !(uiResult & TSXYRESULT_SDR) ); + + uiValue = (uiResult & TSXYRESULT_AD_MASK) >> TSXYRESULT_AD_SHIFT; + uiValue = ((uiValue >> 4) + ((1 + TSXYRESULT_X_MASK)>>1)) & TSXYRESULT_X_MASK; + + // + // Add up the values. + // + uiSum += uiValue; + + // + // Get the lowest and highest values. + // + if( uiValue < uiLowest ) + { + uiLowest = uiValue; + } + if( uiValue > uiHighest ) + { + uiHighest = uiValue; + } + } + + } while( (uiHighest - uiLowest) > uiMaxDiff ); + + // + // Calculate the Average value. + // + uiAve = uiSum / uiSamples; + + return uiAve; +} + +//**************************************************************************** +// CalculateInvPressure +//**************************************************************************** +// Is the Touch Valid. Touch is not valid if the X or Y value is not +// in range and the pressure is not enough. +// +// Touch resistance can be measured by the following formula: +// +// Rx * X * Z2 +// Rtouch = --------- * (-- - 1) +// 4096 Z1 +// +// This is simplified in the ration of Rtouch to Rx. The lower the value, the +// higher the pressure. +// +// Z2 +// InvPressure = X * (-- - 1) +// Z1 +// +static unsigned int CalculateInvPressure(void) +{ + unsigned int uiInvPressure; + + // + // Check to see if the point is valid. + // + if( sTouch.uiZ1 < MIN_Z1_VALUE ) + { + uiInvPressure = 0x10000; + } + + // + // Can omit the pressure calculation if you need to get rid of the division. + // + else + { + uiInvPressure = ((sTouch.uiX * sTouch.uiZ2) / sTouch.uiZ1) - sTouch.uiX; + } + if (uiInvPressure == 0) { + DPRINTK("Setting InvPressure to 1\n"); + uiInvPressure = 1; + } + return uiInvPressure; +} + + + +//**************************************************************************** +// TS_Hardware_Scan_Mode +//**************************************************************************** +// Enables the ep93xx ts scanning engine so that when the pen goes down +// we will get an interrupt. +// +// +static void TS_Hardware_Scan_Mode(void) +{ + unsigned int uiDevCfg; + + DPRINTK("S\n"); + + // + // Disable the soft scanning engine. + // + sTouch.state = TS_STATE_STOPPED; + Stop_Timer2(); + + // + // Clear the TIN (Touchscreen INactive) bit so we can go to + // automatic scanning mode. + // + uiDevCfg = inl( SYSCON_DEVCFG ); + SysconSetLocked( SYSCON_DEVCFG, (uiDevCfg & ~SYSCON_DEVCFG_TIN) ); + + // + // Enable the touch screen scanning state machine by setting + // the ENABLE bit. + // + outl( (TSSETUP_DEFAULT | TSSETUP_ENABLE), TSSetup ); + + // + // Set the flag to show that we are in interrupt mode. + // + gScanningMode = TS_MODE_HARDWARE_SCAN; + + // + // Initialize TSSetup2 register. + // + outl( TSSETUP2_DEFAULT, TSSetup2 ); + +} + +//**************************************************************************** +// TS_Soft_Scan_Mode +//**************************************************************************** +// Sets the touch screen to manual polling mode. +// +// +static void TS_Soft_Scan_Mode(void) +{ + unsigned int uiDevCfg; + + DPRINTK("M\n"); + + if( gScanningMode != TS_MODE_SOFT_SCAN ) + { + // + // Disable the touch screen scanning state machine by clearing + // the ENABLE bit. + // + outl( TSSETUP_DEFAULT, TSSetup ); + + // + // Set the TIN bit so we can do manual touchscreen polling. + // + uiDevCfg = inl( SYSCON_DEVCFG ); + SysconSetLocked( SYSCON_DEVCFG, (uiDevCfg | SYSCON_DEVCFG_TIN) ); + } + + // + // Set the switch register up for the first ADC reading + // + ep93xx_ts_set_direct( sSwitchSettings.uiSwitchZ1 ); + + // + // Initialize our software state machine to know which ADC + // reading to take + // + sTouch.state = TS_STATE_Z1; + + // + // Set the timer so after a mSec or two settling delay it will + // take the first ADC reading. + // + Set_Timer2_uSec( EP93XX_TS_PER_POINT_DELAY_USEC ); + + // + // Note that we are in sw scanning mode not hw scanning mode. + // + gScanningMode = TS_MODE_SOFT_SCAN; + +} + +static void Set_Timer2_uSec( unsigned int uiDelay_uSec ) +{ + unsigned int uiClockTicks; + + /* + * Stop timer 2 + */ + outl( 0, TIMER2CONTROL ); + + uiClockTicks = ((uiDelay_uSec * 508) + 999) / 1000; + outl( uiClockTicks, TIMER2LOAD ); + outl( uiClockTicks, TIMER2VALUE ); + + /* + * Set up Timer 2 for 508 kHz clock and periodic mode. + */ + outl( 0xC8, TIMER2CONTROL ); + +} + +static void Stop_Timer2(void) +{ + outl( 0, TIMER2CONTROL ); +} + +/* + * Initialization and exit routines + */ +int __init ep93xx_ts_init(void) +{ + int retval; + + DPRINTK("ep93xx_ts_init\n"); + + DPRINTK("request Touchscreen interrupt.\n"); + retval = request_irq( IRQ_EP93XX_TOUCH, ep93xx_ts_isr, SA_INTERRUPT, "ep93xx_ts", 0); + if( retval ) + { + DPRINTK(KERN_WARNING "ep93xx_ts: failed to get touchscreen IRQ\n"); + return retval; + } + + DPRINTK("Request Timer interrupt.\n"); + retval = request_irq( IRQ_EP93XX_TIMER2, ep93xx_timer2_isr, + SA_INTERRUPT, "ep93xx_timer2", 0); + if( retval ) + { + DPRINTK(KERN_WARNING "ep93xx_ts: failed to get timer2 IRQ\n"); + return retval; + } + + DPRINTK("Register Touchscreen Driver\n"); + misc_register(&ep93xx_ts_miscdev); + + sTouch.state = TS_STATE_STOPPED; + gScanningMode = TS_MODE_UN_INITIALIZED; + + DPRINTK(KERN_NOTICE "EP93xx touchscreen driver configured for 4-wire operation\n"); + + return 0; +} +void __exit +ep93xx_ts_exit(void) +{ + DPRINTK("ep93xx_ts_exit\n"); + + Stop_Timer2(); + + free_irq(IRQ_EP93XX_TOUCH, 0); + free_irq(IRQ_EP93XX_TIMER2, 0); + + misc_deregister(&ep93xx_ts_miscdev); +} + +module_init(ep93xx_ts_init); +module_exit(ep93xx_ts_exit); + +MODULE_DESCRIPTION("Cirrus EP93xx touchscreen driver"); +MODULE_SUPPORTED_DEVICE("touchscreen/ep93xx"); diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/ep93xx_ts.c~ linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts.c~ --- linux-2.6.20/drivers/input/touchscreen/ep93xx_ts.c~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts.c~ 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,1119 @@ +/* + * linux/drivers/char/ep93xx_ts.c + * + * Copyright (C) 2003-2004 Cirrus Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// To customize for a new touchscreen, there are various macros that +// have to be set. If you allow UART_HACK_DEBUG to be defined, you +// will get real time ts data scrolling up your serial terminal +// screen that will help you empirically determine good values for these. +// + +// +// These are used as trigger levels to know when we have pen up/down +// +// The rules: +// 1. TS_HEAVY_INV_PRESSURE < TS_LIGHT_INV_PRESSURE because these +// are Inverse pressure. +// 2. Any touch lighter than TS_LIGHT_INV_PRESSURE is a pen up. +// 3. Any touch heavier than TS_HEAVY_INV_PRESSURE is a pen down. +// +#define TS_HEAVY_INV_PRESSURE 0xFE0 //C00 +#define TS_LIGHT_INV_PRESSURE 0xFFF //e00 + +// +// If the x, y, or inverse pressure changes more than these values +// between two succeeding points, the point is not reported. +// +#define TS_MAX_VALID_XY_CHANGE 0x300 +#define TS_MAX_VALID_PRESSURE_CHANGE 0x100 + +// +// This is the minimum Z1 Value that is valid. +// +#define MIN_Z1_VALUE 0x50 + +// +// Settling delay for taking each ADC measurement. Increase this +// if ts is jittery. +// +#define EP93XX_TS_ADC_DELAY_USEC 2000 + +// +// Delay between TS points. +// +#define EP93XX_TS_PER_POINT_DELAY_USEC 10000 + +//----------------------------------------------------------------------------- +// Debug messaging thru the UARTs +//----------------------------------------------------------------------------- +/* + * Hello there! Are you trying to get this driver to work with a new + * touschscreen? Turn this on and you will get useful info coming + * out of your serial port. + */ +//#define PRINT_CALIBRATION_FACTORS //NZG mod + + +#ifdef PRINT_CALIBRATION_FACTORS +#define UART_HACK_DEBUG 1 +int iMaxX=0, iMaxY=0, iMinX = 0xfff, iMinY = 0xfff; +#endif + +/* + * For debugging, let's spew messages out serial port 1 or 3 at 57,600 baud. + */ +//#define UART_HACK_DEBUG 1 +#if 0 +#ifdef UART_HACK_DEBUG +static char szBuf[256]; +void UARTWriteString(char * msg); +#define DPRINTK( x... ) \ + sprintf( szBuf, ##x ); \ + UARTWriteString( szBuf ); +#else +static char szBuf[256]; +#define DPRINTK( x... ) \ + sprintf( szBuf, ##x ); \ + printk( szBuf ); +#endif +#endif // 0 + +#ifdef UART_HACK_DEBUG //NZG mod, use printk instead +#define DPRINTK(fmt, args...) printk(fmt, ## args) +#else +#define DPRINTK( x... ) +#endif + +//----------------------------------------------------------------------------- +// A few more macros... +//----------------------------------------------------------------------------- +#define TSSETUP_DEFAULT ( TSSETUP_NSMP_32 | TSSETUP_DEV_64 | \ + ((128<>2] & 0x20); + + // send a char to the uart + pDebugUART[0] = value; +} + +void UARTWriteString(char * msg) +{ + int index = 0; + unsigned int uiTemp; + + //if((pDebugUART[0x14>>2] & 0x1) == 0) + if( bUartInitialized == 0 ) + { + uiTemp = inl(SYSCON_DEVCFG); + uiTemp |= SYSCON_DEVCFG_U1EN; + //uiTemp |= SYSCON_DEVCFG_U3EN; + SysconSetLocked(SYSCON_DEVCFG, uiTemp); + pDebugUART[0x10>>2] = 0xf; + pDebugUART[0xc>>2] = 0; + pDebugUART[0x8>>2] = 0x70; + pDebugUART[0x14>>2] = 0x1; + bUartInitialized = 1; + } + while (msg[index] != 0) + { + if (msg[index] == '\n') + { + SendChar('\r'); + SendChar('\n'); + } + else + { + SendChar(msg[index]); + } + index++; + } +} +#endif // UART_HACK_DEBUG + +/* + * ep93xx_ts_isr + */ +static irqreturn_t ep93xx_ts_isr(int irq, void *dev_id, struct pt_regs *regs) +{ + DPRINTK("isr\n"); + + // + // Note that we don't clear the interrupt here. The interrupt + // gets cleared in TS_Soft_Scan_Mode when the TS ENABLE + // bit is cleared. + // + + // + // Set the ts to manual polling mode and schedule a callback. + // That way we can return from the isr in a reasonable amount of + // time and process the touch in the callback after a brief delay. + // + TS_Soft_Scan_Mode(); + + return(IRQ_HANDLED); +} + +/* + * Save the current ts 'event' in an atomic fashion. + */ +static void ee93xx_ts_evt_add( int buttons, int iX, int iY, int iPressure ) +{ + +#ifdef PRINT_CALIBRATION_FACTORS + if( iX > iMaxX ) iMaxX = iX; + if( iX < iMinX ) iMinX = iX; + if( iY > iMaxY ) iMaxY = iY; + if( iY < iMinY ) iMinY = iY; +#endif + + //DPRINTK("cb\n"); + /* + * Note the event, but use spinlocks to keep it from getting + * halfway read if we get interrupted. + */ + + spin_lock(&event_buffer_lock); + gSample.currentX = iX; + gSample.currentY = iY; + gSample.currentButton = buttons; + gSample.currentPressure = iPressure; + bFreshTouchData = 1; + do_gettimeofday(&gSample.currentTime); + + spin_unlock(&event_buffer_lock); + + kill_fasync(&ep93xx_fasync, SIGIO, POLL_IN); + wake_up_interruptible(&queue); + +} + + +static ssize_t ep93xx_ts_read(struct file *filp, char *buf, size_t count, loff_t *l) +{ + + unsigned short data[3]; + struct ts_sample ts_data; + int iReturn = -EFAULT; + +#ifdef PRINT_CALIBRATION_FACTORS + static int lala=0; + if( bFreshTouchData && (lala++ > 9) ) + { + //DPRINTK("%4d, %4d - range [%4d to %4d],[%4d to %4d]\n",f, currentY, iMinX, iMaxX, iMinY, iMaxY ); + DPRINTK("%4d, %4d - range [%4d to %4d],[%4d to %4d]\n",gSample.currentX, gSample.currentY, iMinX, iMaxX, iMinY, iMaxY );//NZG mod + lala = 0; + } +#endif + if( !bFreshTouchData) + { + iReturn = 0; + } + else if( (count == sizeof(data)) ) + { + spin_lock_irq(&event_buffer_lock); + bFreshTouchData = 0; + data[0] = gSample.currentX; + data[1] = gSample.currentY; + data[2] = gSample.currentButton; + + spin_unlock_irq(&event_buffer_lock); + + if (copy_to_user(buf, data, sizeof data)) + { + DPRINTK("read returning error 1\n"); + return -EFAULT; + } + + count -= sizeof(data); + + /* return the # of bytes that got read */ + iReturn = sizeof(data) ; + DPRINTK("read returning %d bytes read\n", iReturn); + } + else if (count == sizeof(struct ts_sample) ) + { + spin_lock_irq(&event_buffer_lock); + bFreshTouchData = 0; + ts_data.x = gSample.currentX; + ts_data.y = gSample.currentY; + ts_data.pressure = gSample.currentPressure; + ts_data.tv = gSample.currentTime; + spin_unlock_irq(&event_buffer_lock); + + if (copy_to_user(buf, &ts_data, sizeof(struct ts_sample))) + { + DPRINTK("read returning error\n"); + iReturn = -EFAULT; + } + else + { + count -= sizeof(ts_data); + iReturn = sizeof(ts_data); + DPRINTK("read returning %d as sizeof(ts_data)\n", iReturn); + } + + } + + return iReturn; +} + +static unsigned int ep93xx_ts_poll(struct file *filp, poll_table *wait) +{ + // printk("ep93xx_ts_poll\n"); + poll_wait(filp, &queue, wait); + + if( bFreshTouchData ) + { + return POLLIN | POLLRDNORM; + } + + return 0; +} + +static int ep93xx_ts_open(struct inode *inode, struct file *filp) +{ + DPRINTK("ep93xx_ts_open\n"); + + if( down_trylock(&open_sem) ) + { + return -EBUSY; + } + + ep93xx_ts_setup(); + + return 0; +} + +/* + * Asynchronous I/O support. + */ +static int ep93xx_ts_fasync(int fd, struct file *filp, int on) +{ + int retval; + + retval = fasync_helper(fd, filp, on, &ep93xx_fasync); + if (retval < 0) + { + return retval; + } + + return 0; +} + +static int ep93xx_ts_release(struct inode *inode, struct file *filp) +{ + Stop_Timer2(); + + /* + * Call our async I/O support to request that this file + * cease to be used for async I/O. + */ + ep93xx_ts_fasync(-1, filp, 0); + + ep93xx_ts_shutdown(); + + up(&open_sem); + + return 0; +} + +static ssize_t ep93xx_ts_write(struct file *file, const char *buffer, size_t count, + loff_t *ppos) +{ + return -EINVAL; +} + + +static int ep93xx_ts_ioctl(struct inode *inode, struct file *file, uint command, ulong u) +{ + static const int version = EV_VERSION; + static const u_int32_t bit =(1 << EV_ABS); + static const u_int32_t absbit = (1 << ABS_X) | (1 << ABS_Y) | (1 << ABS_PRESSURE); + int iReturn ; + int i = 0; + + switch(command) + { + case EVIOCGVERSION: + DPRINTK("ep93xx_ts_ioctl command = EVIOCGVERSION\r\n"); + i = copy_to_user((void __user *)u, (void *)version, sizeof(version)); + iReturn = i ? -EFAULT : 0; + break; + + case EVIOCGBIT(0,sizeof(u_int32_t) * 8) : + DPRINTK("ep93xx_ts_ioctl command = EVIOCGBIT(0,sizeof(uint32) * 8)\r\n"); + i = copy_to_user((void __user *)u, (void *)bit, sizeof(bit)); + iReturn = i ? -EFAULT : 0; + break; + + case EVIOCGBIT(EV_ABS, sizeof(absbit) * 8): + DPRINTK("ep93xx_ts_ioctl command = EVIOCGBIT(0,sizeof(uint32) * 8)\r\n"); + copy_to_user((void __user *)u, (void *)absbit, sizeof(absbit)); + iReturn = i ? -EFAULT : 0; + break; + default: + DPRINTK(" ep93xx_ts_ioctl unknown command = %d\n",u); + iReturn = -1; + break; + } + + return iReturn; +} + +static struct file_operations ep93xx_ts_fops = { + owner: THIS_MODULE, + read: ep93xx_ts_read, + write: ep93xx_ts_write, + poll: ep93xx_ts_poll, + open: ep93xx_ts_open, + ioctl: ep93xx_ts_ioctl, + release: ep93xx_ts_release, + fasync: ep93xx_ts_fasync, +}; + +static struct miscdevice ep93xx_ts_miscdev = +{ + EP93XX_TS_MINOR, + "ep93xx_ts", + &ep93xx_ts_fops +}; + +void ep93xx_ts_setup(void) +{ + unsigned int uiKTDIV, uiTSXYMaxMin; + DPRINTK("ep93xx_hw_setup\n"); + + /* + * Set the TSEN bit in KTDIV so that we are enabling the clock + * for the touchscreen. + */ + uiKTDIV = inl(SYSCON_KTDIV); + uiKTDIV |= SYSCON_KTDIV_TSEN; + SysconSetLocked( SYSCON_KTDIV, uiKTDIV ); + + // + // Program the TSSetup and TSSetup2 registers. + // + outl( TSSETUP_DEFAULT, TSSetup ); + outl( TSSETUP2_DEFAULT, TSSetup2 ); + + // + // Set the the touch settings. + // + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDischarge, TSDirect ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDischarge, TSDischarge ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiSwitchZ1, TSXSample ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiSwitchZ2, TSYSample ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDetect, TSDetect ); + + // + // X,YMin set to 0x40 = have to drag that many pixels for a new irq. + // X,YMax set to 0x40 = 1024 pixels is the maximum movement within the + // time scan limit. + // + uiTSXYMaxMin = (50 << TSMAXMIN_XMIN_SHIFT) & TSMAXMIN_XMIN_MASK; + uiTSXYMaxMin |= (50 << TSMAXMIN_YMIN_SHIFT) & TSMAXMIN_YMIN_MASK; + uiTSXYMaxMin |= (0xff << TSMAXMIN_XMAX_SHIFT) & TSMAXMIN_XMAX_MASK; + uiTSXYMaxMin |= (0xff << TSMAXMIN_YMAX_SHIFT) & TSMAXMIN_YMAX_MASK; + outl( uiTSXYMaxMin, TSXYMaxMin ); + + bCurrentPenDown = 0; + bFreshTouchData = 0; + guiLastX = 0; + guiLastY = 0; + guiLastInvPressure = 0xffffff; + + // + // Enable the touch screen scanning engine. + // + TS_Hardware_Scan_Mode(); +} + +/* + * ep93xx_ts_shutdown + * + */ +static void +ep93xx_ts_shutdown(void) +{ + unsigned int uiKTDIV; + + DPRINTK("ep93xx_ts_shutdown\n"); + + sTouch.state = TS_STATE_STOPPED; + Stop_Timer2(); + + /* + * Disable the scanning engine. + */ + outl( 0, TSSetup ); + outl( 0, TSSetup2 ); + + /* + * Clear the TSEN bit in KTDIV so that we are disabling the clock + * for the touchscreen. + */ + uiKTDIV = inl(SYSCON_KTDIV); + uiKTDIV &= ~SYSCON_KTDIV_TSEN; + SysconSetLocked( SYSCON_KTDIV, uiKTDIV ); + +} /* ep93xx_ts_shutdown */ + +static irqreturn_t ep93xx_timer2_isr(int irq, void *dev_id, struct pt_regs *regs) +{ + DPRINTK("state: %d\n", (int)sTouch.state ); + + switch( sTouch.state ) + { + case TS_STATE_STOPPED: + TS_Hardware_Scan_Mode(); + break; + + // + // Get the Z1 value for pressure measurement and set up + // the switch register for getting the Z2 measurement. + // + case TS_STATE_Z1: + Set_Timer2_uSec( EP93XX_TS_ADC_DELAY_USEC ); + sTouch.uiZ1 = ADCGetData( 2, 200 ); + ep93xx_ts_set_direct( sSwitchSettings.uiSwitchZ2 ); + sTouch.state = TS_STATE_Z2; + break; + + // + // Get the Z2 value for pressure measurement and set up + // the switch register for getting the Y measurement. + // + case TS_STATE_Z2: + sTouch.uiZ2 = ADCGetData( 2, 200 ); + ep93xx_ts_set_direct( sSwitchSettings.uiYSample ); + sTouch.state = TS_STATE_Y; + break; + + // + // Get the Y value and set up the switch register for + // getting the X measurement. + // + case TS_STATE_Y: + sTouch.uiY = ADCGetData( 4, 20 ); + ep93xx_ts_set_direct( sSwitchSettings.uiXSample ); + sTouch.state = TS_STATE_X; + break; + + // + // Read the X value. This is the last of the 4 adc values + // we need so we continue on to process the data. + // + case TS_STATE_X: + Stop_Timer2(); + + sTouch.uiX = ADCGetData( 4, 20 ); + + outl( 0xaa, TSSWLock ); + outl( sSwitchSettings.uiDischarge, TSDirect ); + + sTouch.state = TS_STATE_DONE; + + /* + * Process this set of ADC readings. + */ + ProcessPointData(); + + break; + + + // + // Shouldn't get here. But if we do, we can recover... + // + case TS_STATE_DONE: + TS_Hardware_Scan_Mode(); + break; + } + + // + // Clear the timer2 interrupt. + // + outl( 1, TIMER2CLEAR ); + return(IRQ_HANDLED); +} + +/*--------------------------------------------------------------------- + * ProcessPointData + * + * This routine processes the ADC data into usable point data and then + * puts the driver into hw or sw scanning mode before returning. + * + * We calculate inverse pressure (lower number = more pressure) then + * do a hystheresis with the two pressure values 'light' and 'heavy'. + * + * If we are above the light, we have pen up. + * If we are below the heavy we have pen down. + * As long as the pressure stays below the light, pen stays down. + * When we get above the light again, pen goes back up. + * + */ +static void ProcessPointData(void) +{ + int bValidPoint = 0; + unsigned int uiXDiff, uiYDiff, uiInvPressureDiff; + unsigned int uiInvPressure; + + // + // Calculate the current pressure. + // + uiInvPressure = CalculateInvPressure(); + + DPRINTK(" X=0x%x, Y=0x%x, Z1=0x%x, Z2=0x%x, InvPressure=0x%x", + sTouch.uiX, sTouch.uiY, sTouch.uiZ1, sTouch.uiZ2, uiInvPressure ); + + // + // If pen pressure is so light that it is greater than the 'max' setting + // then we consider this to be a pen up. + // + if( uiInvPressure >= TS_LIGHT_INV_PRESSURE ) + { + DPRINTK(" -- up \n"); + bCurrentPenDown = 0; + ee93xx_ts_evt_add( 0, guiLastX, guiLastY, 0 ); + TS_Hardware_Scan_Mode(); + return; + } + + // + // Hystheresis: + // If the pen pressure is hard enough to be less than the 'min' OR + // the pen is already down and is still less than the 'max'... + // + if( (uiInvPressure < TS_HEAVY_INV_PRESSURE) || + ( bCurrentPenDown && (uiInvPressure < TS_LIGHT_INV_PRESSURE) ) ) + { + if( bCurrentPenDown ) + { + // + // If pen was previously down, check the difference between + // the last sample and this one... if the difference between + // samples is too great, ignore the sample. + // + uiXDiff = abs(guiLastX - sTouch.uiX); + uiYDiff = abs(guiLastY - sTouch.uiY); + uiInvPressureDiff = abs(guiLastInvPressure - uiInvPressure); + + if( (uiXDiff < TS_MAX_VALID_XY_CHANGE) && (uiYDiff < TS_MAX_VALID_XY_CHANGE) && + (uiInvPressureDiff < TS_MAX_VALID_PRESSURE_CHANGE) ) + { + DPRINTK(" -- valid(two) \n"); + bValidPoint = 1; + } + else + { + DPRINTK(" -- INvalid(two) \n"); + } + } + else + { + DPRINTK(" -- valid \n"); + bValidPoint = 1; + } + + /* + * If either the pen was put down or dragged make a note of it. + */ + if( bValidPoint ) + { + guiLastX = sTouch.uiX; + guiLastY = sTouch.uiY; + guiLastInvPressure = uiInvPressure; + bCurrentPenDown = 1; + DPRINTK("calling ee93xx_ts_evt_add\n"); + ee93xx_ts_evt_add( 1, sTouch.uiX, sTouch.uiY, (0x7000000 /uiInvPressure) ); + } + + TS_Soft_Scan_Mode(); + return; + } + + DPRINTK(" -- fallout \n"); + TS_Hardware_Scan_Mode(); +} + +static void ep93xx_ts_set_direct( unsigned int uiADCSwitch ) +{ + unsigned int uiResult; + + // + // Set the switch settings in the direct register. + // + outl( 0xaa, TSSWLock ); + outl( uiADCSwitch, TSDirect ); + + // + // Read and throw away the first sample. + // + do { + uiResult = inl(TSXYResult); + } while( !(uiResult & TSXYRESULT_SDR) ); + +} + +static unsigned int ADCGetData +( + unsigned int uiSamples, + unsigned int uiMaxDiff +) +{ + unsigned int uiResult, uiValue, uiCount, uiLowest, uiHighest, uiSum, uiAve; + + do + { + // + //Initialize our values. + // + uiLowest = 0xfffffff; + uiHighest = 0; + uiSum = 0; + + for( uiCount = 0 ; uiCount < uiSamples ; uiCount++ ) + { + // + // Read the touch screen four more times and average. + // + do { + uiResult = inl(TSXYResult); + } while( !(uiResult & TSXYRESULT_SDR) ); + + uiValue = (uiResult & TSXYRESULT_AD_MASK) >> TSXYRESULT_AD_SHIFT; + uiValue = ((uiValue >> 4) + ((1 + TSXYRESULT_X_MASK)>>1)) & TSXYRESULT_X_MASK; + + // + // Add up the values. + // + uiSum += uiValue; + + // + // Get the lowest and highest values. + // + if( uiValue < uiLowest ) + { + uiLowest = uiValue; + } + if( uiValue > uiHighest ) + { + uiHighest = uiValue; + } + } + + } while( (uiHighest - uiLowest) > uiMaxDiff ); + + // + // Calculate the Average value. + // + uiAve = uiSum / uiSamples; + + return uiAve; +} + +//**************************************************************************** +// CalculateInvPressure +//**************************************************************************** +// Is the Touch Valid. Touch is not valid if the X or Y value is not +// in range and the pressure is not enough. +// +// Touch resistance can be measured by the following formula: +// +// Rx * X * Z2 +// Rtouch = --------- * (-- - 1) +// 4096 Z1 +// +// This is simplified in the ration of Rtouch to Rx. The lower the value, the +// higher the pressure. +// +// Z2 +// InvPressure = X * (-- - 1) +// Z1 +// +static unsigned int CalculateInvPressure(void) +{ + unsigned int uiInvPressure; + + // + // Check to see if the point is valid. + // + if( sTouch.uiZ1 < MIN_Z1_VALUE ) + { + uiInvPressure = 0x10000; + } + + // + // Can omit the pressure calculation if you need to get rid of the division. + // + else + { + uiInvPressure = ((sTouch.uiX * sTouch.uiZ2) / sTouch.uiZ1) - sTouch.uiX; + } + if (uiInvPressure == 0) { + DPRINTK("Setting InvPressure to 1\n"); + uiInvPressure = 1; + } + return uiInvPressure; +} + + + +//**************************************************************************** +// TS_Hardware_Scan_Mode +//**************************************************************************** +// Enables the ep93xx ts scanning engine so that when the pen goes down +// we will get an interrupt. +// +// +static void TS_Hardware_Scan_Mode(void) +{ + unsigned int uiDevCfg; + + DPRINTK("S\n"); + + // + // Disable the soft scanning engine. + // + sTouch.state = TS_STATE_STOPPED; + Stop_Timer2(); + + // + // Clear the TIN (Touchscreen INactive) bit so we can go to + // automatic scanning mode. + // + uiDevCfg = inl( SYSCON_DEVCFG ); + SysconSetLocked( SYSCON_DEVCFG, (uiDevCfg & ~SYSCON_DEVCFG_TIN) ); + + // + // Enable the touch screen scanning state machine by setting + // the ENABLE bit. + // + outl( (TSSETUP_DEFAULT | TSSETUP_ENABLE), TSSetup ); + + // + // Set the flag to show that we are in interrupt mode. + // + gScanningMode = TS_MODE_HARDWARE_SCAN; + + // + // Initialize TSSetup2 register. + // + outl( TSSETUP2_DEFAULT, TSSetup2 ); + +} + +//**************************************************************************** +// TS_Soft_Scan_Mode +//**************************************************************************** +// Sets the touch screen to manual polling mode. +// +// +static void TS_Soft_Scan_Mode(void) +{ + unsigned int uiDevCfg; + + DPRINTK("M\n"); + + if( gScanningMode != TS_MODE_SOFT_SCAN ) + { + // + // Disable the touch screen scanning state machine by clearing + // the ENABLE bit. + // + outl( TSSETUP_DEFAULT, TSSetup ); + + // + // Set the TIN bit so we can do manual touchscreen polling. + // + uiDevCfg = inl( SYSCON_DEVCFG ); + SysconSetLocked( SYSCON_DEVCFG, (uiDevCfg | SYSCON_DEVCFG_TIN) ); + } + + // + // Set the switch register up for the first ADC reading + // + ep93xx_ts_set_direct( sSwitchSettings.uiSwitchZ1 ); + + // + // Initialize our software state machine to know which ADC + // reading to take + // + sTouch.state = TS_STATE_Z1; + + // + // Set the timer so after a mSec or two settling delay it will + // take the first ADC reading. + // + Set_Timer2_uSec( EP93XX_TS_PER_POINT_DELAY_USEC ); + + // + // Note that we are in sw scanning mode not hw scanning mode. + // + gScanningMode = TS_MODE_SOFT_SCAN; + +} + +static void Set_Timer2_uSec( unsigned int uiDelay_uSec ) +{ + unsigned int uiClockTicks; + + /* + * Stop timer 2 + */ + outl( 0, TIMER2CONTROL ); + + uiClockTicks = ((uiDelay_uSec * 508) + 999) / 1000; + outl( uiClockTicks, TIMER2LOAD ); + outl( uiClockTicks, TIMER2VALUE ); + + /* + * Set up Timer 2 for 508 kHz clock and periodic mode. + */ + outl( 0xC8, TIMER2CONTROL ); + +} + +static void Stop_Timer2(void) +{ + outl( 0, TIMER2CONTROL ); +} + +/* + * Initialization and exit routines + */ +int __init ep93xx_ts_init(void) +{ + int retval; + + DPRINTK("ep93xx_ts_init\n"); + + DPRINTK("request Touchscreen interrupt.\n"); + retval = request_irq( IRQ_EP93XX_TOUCH, ep93xx_ts_isr, SA_INTERRUPT, "ep93xx_ts", 0); + if( retval ) + { + DPRINTK(KERN_WARNING "ep93xx_ts: failed to get touchscreen IRQ\n"); + return retval; + } + + DPRINTK("Request Timer interrupt.\n"); + retval = request_irq( IRQ_EP93XX_TIMER2, ep93xx_timer2_isr, + SA_INTERRUPT, "ep93xx_timer2", 0); + if( retval ) + { + DPRINTK(KERN_WARNING "ep93xx_ts: failed to get timer2 IRQ\n"); + return retval; + } + + DPRINTK("Register Touchscreen Driver\n"); + misc_register(&ep93xx_ts_miscdev); + + sTouch.state = TS_STATE_STOPPED; + gScanningMode = TS_MODE_UN_INITIALIZED; + + DPRINTK(KERN_NOTICE "EP93xx touchscreen driver configured for 4-wire operation\n"); + + return 0; +} +void __exit +ep93xx_ts_exit(void) +{ + DPRINTK("ep93xx_ts_exit\n"); + + Stop_Timer2(); + + free_irq(IRQ_EP93XX_TOUCH, 0); + free_irq(IRQ_EP93XX_TIMER2, 0); + + misc_deregister(&ep93xx_ts_miscdev); +} + +module_init(ep93xx_ts_init); +module_exit(ep93xx_ts_exit); + +MODULE_DESCRIPTION("Cirrus EP93xx touchscreen driver"); +MODULE_SUPPORTED_DEVICE("touchscreen/ep93xx"); diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/ep93xx_ts.h linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts.h --- linux-2.6.20/drivers/input/touchscreen/ep93xx_ts.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/ep93xx_ts.h 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,53 @@ +/* + * ep93xx_ts.h + * + * The contents of this file are subject to the Mozilla Public License + * Version 1.1 (the "License"); you may not use this file except in + * compliance with the License. You may obtain a copy of the License + * at http://www.mozilla.org/MPL/ + * + * Software distributed under the License is distributed on an "AS IS" + * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See + * the License for the specific language governing rights and + * limitations under the License. + * + * The initial developer of the original code is David A. Hinds + * . Portions created by David A. Hinds + * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. + * + * Alternatively, the contents of this file may be used under the + * terms of the GNU General Public License version 2 (the "GPL"), in + * which case the provisions of the GPL are applicable instead of the + * above. If you wish to allow the use of your version of this file + * only under the terms of the GPL and not to allow others to use + * your version of this file under the MPL, indicate your decision by + * deleting the provisions above and replace them with the notice and + * other provisions required by the GPL. If you do not delete the + * provisions above, a recipient may use your version of this file + * under either the MPL or the GPL. + */ + +#ifndef _LINUX_EP93XX_TS_H +#define _LINUX_EP93XX_TS_H + +/*touchscreen register defines*/ +#define SYSCON_KTDIV EP93XX_SYSCON_KEY_TOUCH_CLOCK_DIV +#define SYSCON_SWLOCK EP93XX_SYSCON_SWLOCK +#define TSSetup EP93XX_TOUCHSCREEN_TSSetup +#define TSXYMaxMin EP93XX_TOUCHSCREEN_TSXYMaxMin +#define TSXYResult EP93XX_TOUCHSCREEN_TSDischarge +#define TSDischarge EP93XX_TOUCHSCREEN_TSDischarge +#define TSXSample EP93XX_TOUCHSCREEN_TSXSample +#define TSYSample EP93XX_TOUCHSCREEN_TSYSample +#define TSDirect EP93XX_TOUCHSCREEN_TSDirect +#define TSDetect EP93XX_TOUCHSCREEN_TSDetect +#define TSSWLock EP93XX_TOUCHSCREEN_TSSWLock +#define TSSetup2 EP93XX_TOUCHSCREEN_TSSetup2 + + +#define SYSCON_DEVCFG EP93XX_SYSCON_DEVICE_CONFIG +#define TIMER2CONTROL EP93XX_TIMER2_CONTROL +#define TIMER2LOAD EP93XX_TIMER2_LOAD +#define TIMER2VALUE EP93XX_TIMER2_VALUE +#define TIMER2CLEAR EP93XX_TIMER2_CLEAR +#endif diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/Kconfig linux-2.6.20-AT91/drivers/input/touchscreen/Kconfig --- linux-2.6.20/drivers/input/touchscreen/Kconfig 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/Kconfig 2007-07-12 14:20:46.000000000 -0500 @@ -159,4 +159,9 @@ To compile this driver as a module, choose M here: the module will be called ucb1400_ts. + +config TOUCHSCREEN_EP93XX + tristate "EP93xx Touchscreen" + depends on ARM && INPUT && ARCH_EP93XX + endif diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/Kconfig.orig linux-2.6.20-AT91/drivers/input/touchscreen/Kconfig.orig --- linux-2.6.20/drivers/input/touchscreen/Kconfig.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/Kconfig.orig 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,162 @@ +# +# Mouse driver configuration +# +menuconfig INPUT_TOUCHSCREEN + bool "Touchscreens" + help + Say Y here, and a list of supported touchscreens will be displayed. + This option doesn't affect the kernel. + + If unsure, say Y. + +if INPUT_TOUCHSCREEN + +config TOUCHSCREEN_ADS7846 + tristate "ADS 7846 based touchscreens" + depends on SPI_MASTER + help + Say Y here if you have a touchscreen interface using the + ADS7846 controller, and your board-specific initialization + code includes that in its table of SPI devices. + + If unsure, say N (but it's safe to say "Y"). + + To compile this driver as a module, choose M here: the + module will be called ads7846. + +config TOUCHSCREEN_BITSY + tristate "Compaq iPAQ H3600 (Bitsy) touchscreen" + depends on SA1100_BITSY + select SERIO + help + Say Y here if you have the h3600 (Bitsy) touchscreen. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called h3600_ts_input. + +config TOUCHSCREEN_CORGI + tristate "SharpSL (Corgi and Spitz series) touchscreen driver" + depends on PXA_SHARPSL + default y + help + Say Y here to enable the driver for the touchscreen on the + Sharp SL-C7xx and SL-Cxx00 series of PDAs. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called corgi_ts. + +config TOUCHSCREEN_GUNZE + tristate "Gunze AHL-51S touchscreen" + select SERIO + help + Say Y here if you have the Gunze AHL-51 touchscreen connected to + your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called gunze. + +config TOUCHSCREEN_ELO + tristate "Elo serial touchscreens" + select SERIO + help + Say Y here if you have an Elo serial touchscreen connected to + your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called elo. + +config TOUCHSCREEN_MTOUCH + tristate "MicroTouch serial touchscreens" + select SERIO + help + Say Y here if you have a MicroTouch (3M) serial touchscreen connected to + your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called mtouch. + +config TOUCHSCREEN_MK712 + tristate "ICS MicroClock MK712 touchscreen" + help + Say Y here if you have the ICS MicroClock MK712 touchscreen + controller chip in your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called mk712. + +config TOUCHSCREEN_HP600 + tristate "HP Jornada 680/690 touchscreen" + depends on SH_HP6XX && SH_ADC + help + Say Y here if you have a HP Jornada 680 or 690 and want to + support the built-in touchscreen. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called hp680_ts_input. + +config TOUCHSCREEN_PENMOUNT + tristate "Penmount serial touchscreen" + select SERIO + help + Say Y here if you have a Penmount serial touchscreen connected to + your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called penmount. + +config TOUCHSCREEN_TOUCHRIGHT + tristate "Touchright serial touchscreen" + select SERIO + help + Say Y here if you have a Touchright serial touchscreen connected to + your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called touchright. + +config TOUCHSCREEN_TOUCHWIN + tristate "Touchwin serial touchscreen" + select SERIO + help + Say Y here if you have a Touchwin serial touchscreen connected to + your system. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called touchwin. + +config TOUCHSCREEN_UCB1400 + tristate "Philips UCB1400 touchscreen" + select AC97_BUS + help + This enables support for the Philips UCB1400 touchscreen interface. + The UCB1400 is an AC97 audio codec. The touchscreen interface + will be initialized only after the ALSA subsystem has been + brought up and the UCB1400 detected. You therefore have to + configure ALSA support as well (either built-in or modular, + independently of whether this driver is itself built-in or + modular) for this driver to work. + + To compile this driver as a module, choose M here: the + module will be called ucb1400_ts. + +endif diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/Makefile linux-2.6.20-AT91/drivers/input/touchscreen/Makefile --- linux-2.6.20/drivers/input/touchscreen/Makefile 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/Makefile 2007-07-12 14:20:46.000000000 -0500 @@ -9,9 +9,10 @@ obj-$(CONFIG_TOUCHSCREEN_CORGI) += corgi_ts.o obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o -obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o +obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o +obj-$(CONFIG_TOUCHSCREEN_EP93XX) += ep93xx_ts.o obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/Makefile~ linux-2.6.20-AT91/drivers/input/touchscreen/Makefile~ --- linux-2.6.20/drivers/input/touchscreen/Makefile~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/Makefile~ 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,18 @@ +# +# Makefile for the mouse drivers. +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o +obj-$(CONFIG_TOUCHSCREEN_BITSY) += h3600_ts_input.o +obj-$(CONFIG_TOUCHSCREEN_CORGI) += corgi_ts.o +obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o +obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o +obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o +obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o +obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o +obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o +obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o +obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o +obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o diff -urN -x CVS linux-2.6.20/drivers/input/touchscreen/Makefile.orig linux-2.6.20-AT91/drivers/input/touchscreen/Makefile.orig --- linux-2.6.20/drivers/input/touchscreen/Makefile.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/input/touchscreen/Makefile.orig 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,18 @@ +# +# Makefile for the mouse drivers. +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o +obj-$(CONFIG_TOUCHSCREEN_BITSY) += h3600_ts_input.o +obj-$(CONFIG_TOUCHSCREEN_CORGI) += corgi_ts.o +obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o +obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o +obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o +obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o +obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o +obj-$(CONFIG_TOUCHSCREEN_PENMOUNT) += penmount.o +obj-$(CONFIG_TOUCHSCREEN_TOUCHRIGHT) += touchright.o +obj-$(CONFIG_TOUCHSCREEN_TOUCHWIN) += touchwin.o +obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o diff -urN -x CVS linux-2.6.20/drivers/ioex/ecoreex.c linux-2.6.20-AT91/drivers/ioex/ecoreex.c --- linux-2.6.20/drivers/ioex/ecoreex.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/ioex/ecoreex.c 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,148 @@ +/************************************************************ + * iPac CPLD resources available on the iPac 9302. + * Devices internal to the CPLD are detected and instatiated as + * classes in sysfs. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//--------------------------------------------------------------------------------- +#ifdef CONFIG_ECOREEX_TGPIO +#define IPACCPLD_BASE_NAME "iPac GPI/O expansion R1.0" +#define IPACCPLD_BASE 0xA0 + +#define IPACCPLD_BASE_NAME_11 "iPac GPI/O expansion R1.1" +#define IPACCPLD_BASE_11 0xA3 + +static inline int IPACCPLD_BASE_map(unsigned long phys_addr,u8 *virt_addr,unsigned long size,const char *name){ + + if(request_mem_region(phys_addr,size,name)==NULL){ + printk("could not obtain physical memory at %lx for EMAC core\n",phys_addr); + iounmap(virt_addr); + return -1; + } + //add appropriate class devices for this version to the system + printk("%s detected at %lx\n",name,phys_addr); + +#ifdef CONFIG_GPIOCLASS + gpio_declare(); + gpio_device_create(&virt_addr[0], &virt_addr[1],"portw"); + gpio_device_create(&virt_addr[2], &virt_addr[3],"portx"); + gpio_device_create(&virt_addr[4], &virt_addr[5],"porty"); + gpio_device_create(&virt_addr[6], &virt_addr[7],"portz"); +#endif + +return 0; +} +#endif //CONFIG_ECOREEX_TGPIO +//--------------------------------------------------------------------------------- +#ifdef CONFIG_ECOREEX_SGPWM +#define IPACCPLD_GPWM_NAME "iPac Shadow GPI/O & PWM expansion R1.0" +#define IPACCPLD_GPWM 0xA1 + +#define IPACCPLD_GPWM_NAME_11 "iPac Shadow GPI/O & PWM expansion R1.1" +#define IPACCPLD_GPWM_11 0xA2 + +static inline int IPACCPLD_GPWM_map(unsigned long phys_addr,u8 *virt_addr,unsigned long size,const char *name){ + + if(request_mem_region(phys_addr,size,name)==NULL){ + printk("could not obtain physical memory at %lx for EMAC core\n",phys_addr); + iounmap(virt_addr); + return -1; + } + + printk("%s detected at %lx\n",name,phys_addr); + //add appropriate class devices for this version to the system + +#ifdef CONFIG_GPIOCLASS + gpio_declare(); + gpi_device_create(&virt_addr[0],"portw"); + gpo_device_create(&virt_addr[1],"portx"); + gpo_device_create(&virt_addr[2],"porty"); + gpi_device_create(&virt_addr[3],"portz"); + gpo_device_create(&virt_addr[7],"control"); +#endif //CONFIG_GPIOCLASS + +#ifdef CONFIG_PWMCLASS + pwmd_device_create(&virt_addr[4],"gpwm1"); + pwmd_device_create(&virt_addr[5],"gpwm2"); +#endif + +return 0; +} + +#endif //CONFIG_ECOREEX_SGPWM + + + + +/************************************************************ + * core mappings based upon a key + */ +static inline void map_core(unsigned long phys_addr, unsigned long size, int key_offset) +{ + u8 *virt_addr = ioremap_nocache(phys_addr,size); + int version; + if(virt_addr==NULL)printk("iPac could not remap physical memory at %lx for EMAC core\n",phys_addr); + else{ + version =ioread8(&virt_addr[key_offset]); + //printk("EMAC core version %x detected\n",version); + switch(version){ + case IPACCPLD_BASE: + IPACCPLD_BASE_map(phys_addr,virt_addr,size,IPACCPLD_BASE_NAME); + break; + case IPACCPLD_BASE_11: + IPACCPLD_BASE_map(phys_addr,virt_addr,size,IPACCPLD_BASE_NAME_11); + break; + case IPACCPLD_GPWM: + IPACCPLD_GPWM_map(phys_addr,virt_addr,size,IPACCPLD_GPWM_NAME); + break; + case IPACCPLD_GPWM_11: + IPACCPLD_GPWM_map(phys_addr,virt_addr,size,IPACCPLD_GPWM_NAME_11); + break; + default://unrecognized CPLD or no CPLD available, silently fail and the physical memory region + iounmap(virt_addr); + } + } +} + +static int ecoreex_probe(struct platform_device *pdev){ + struct ecoreex_data *data; + //printk("ecoreex_probe\n"); + if (pdev == NULL)return -ENODEV; + data = pdev->dev.platform_data; + map_core(pdev->resource->start,(pdev->resource->end-pdev->resource->start+1),data->key_offset); + return 0; +} + +//driver currently has no removal method. +static struct platform_driver ecoreex_driver = { + .probe = ecoreex_probe, + .driver = { + .name = "ecoreex", + }, +}; + +#define DRV_MODULE_NAME "ecoreex" +#define DRV_MODULE_VERSION "1.0" +static int __init ecoreex_init_module(void) +{ + printk(KERN_INFO DRV_MODULE_NAME " version " DRV_MODULE_VERSION " loading\n"); + return platform_driver_register(&ecoreex_driver); +} + +static void __exit ecoreex_cleanup_module(void) +{ + platform_driver_unregister(&ecoreex_driver); +} + +module_init(ecoreex_init_module); +module_exit(ecoreex_cleanup_module); + diff -urN -x CVS linux-2.6.20/drivers/ioex/Kconfig linux-2.6.20-AT91/drivers/ioex/Kconfig --- linux-2.6.20/drivers/ioex/Kconfig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/ioex/Kconfig 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,30 @@ +# +# IO expansion configuration +# + +menu "IO expansion" + +config ECOREEX + tristate "EMAC cores" + ---help--- + Provides autodetection and support for PLD cores following the EMAC + format, which uses a device key to communicate the expansion devices available to + the kernel. + +config ECOREEX_TGPIO + depends on ECOREEX + bool "iPac True GPI/O expansion R1.0" + ---help--- + Provides autodetection and support for the iPac GPI/O expansion + +config ECOREEX_SGPWM + depends on ECOREEX + bool "iPac Shadow GPI/O & PWM expansion R1.0" + ---help--- + Provides autodetection and support for the iPac Shadow GPI/O & PWM expansion + +endmenu + + + + diff -urN -x CVS linux-2.6.20/drivers/ioex/Makefile linux-2.6.20-AT91/drivers/ioex/Makefile --- linux-2.6.20/drivers/ioex/Makefile 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/ioex/Makefile 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,10 @@ +# +# Makefile for the ioex devices +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_ECOREEX) += ecoreex.o + + + diff -urN -x CVS linux-2.6.20/drivers/Kconfig linux-2.6.20-AT91/drivers/Kconfig --- linux-2.6.20/drivers/Kconfig 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/Kconfig 2007-07-12 14:20:47.000000000 -0500 @@ -46,6 +46,8 @@ source "drivers/input/Kconfig" +source "drivers/ioex/Kconfig" + source "drivers/char/Kconfig" source "drivers/i2c/Kconfig" diff -urN -x CVS linux-2.6.20/drivers/Makefile linux-2.6.20-AT91/drivers/Makefile --- linux-2.6.20/drivers/Makefile 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/Makefile 2007-07-12 14:20:46.000000000 -0500 @@ -80,3 +80,4 @@ obj-$(CONFIG_DMA_ENGINE) += dma/ obj-$(CONFIG_HID) += hid/ obj-$(CONFIG_PPC_PS3) += ps3/ +obj-y += ioex/ diff -urN -x CVS linux-2.6.20/drivers/misc/classes/gpio.c linux-2.6.20-AT91/drivers/misc/classes/gpio.c --- linux-2.6.20/drivers/misc/classes/gpio.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/misc/classes/gpio.c 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,195 @@ +/** + * A class for simple gpio ports + * Several types of general purpose devices are available + * which all export the same basic functionity + * through differenet underlying methods + */ +#include +#include +#include +#include +#include +#include +#include + +/************************************************************ + * the global device class + */ +static struct class *gpioclass = NULL; + +struct class *gpio_declare(void){ + if(!gpioclass){ + printk("registering GPIO class\n"); + gpioclass=class_create(THIS_MODULE,"gpio"); + } +return gpioclass; +} + +/************************************************************************************ + * true gpio ports, + * these ports use a ddr register and data register which can always be read + */ +typedef struct gpio_s{ + void *ddr; + void *data; +}gpio_t; + +ssize_t gpio_ddr_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",ioread8(((gpio_t *)cls->class_data)->ddr)); +} + +ssize_t gpio_ddr_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,((gpio_t *)cls->class_data)->ddr,NULL)); +} + +ssize_t gpio_data_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",ioread8(((gpio_t *)cls->class_data)->data)); +} + +ssize_t gpio_data_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,((gpio_t *)cls->class_data)->data,NULL)); +} + +/** + * create a new gpio device + * TODO add printf formatting support for the name + */ +struct class_device *gpio_device_create(void *data, void *ddr,const char *name){ + + static CLASS_DEVICE_ATTR(ddr,S_IRUGO|S_IWUGO,gpio_ddr_show,gpio_ddr_store); + static CLASS_DEVICE_ATTR(data,S_IRUGO|S_IWUGO,gpio_data_show,gpio_data_store); + + if(gpioclass){ + struct class_device *dev = class_device_create(gpioclass, NULL, MKDEV(0, 0), NULL, name); + gpio_t *gpio_pd = kmalloc(sizeof(gpio_t),GFP_KERNEL); + printk("registering gpio device: %s\n",name); + + gpio_pd->ddr = ddr; + gpio_pd->data = data; + dev->class_data = gpio_pd; + + class_device_create_file(dev,&class_device_attr_ddr); + class_device_create_file(dev,&class_device_attr_data); + + return dev; + } + return NULL; +} + + + + + + +/************************************************************************************ + * shadow gpo ports, + * these ports are write only and have no register to read back the current state + * a shadow port is therefore created to keep track of the current state in software. + * this is not as complete an implementation from a hardware standpoint as a user can only + * see the hardware changes if a rogue process if it "plays fair" and modifies the shadow register. + * It is, however, much cheaper from a gate implementation standpoint and probably just fine for + * most applications. + */ +typedef struct gpo_s{ + void *data; + u8 shadow; +}gpo_t; + + +ssize_t gpo_ddr_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",0xff); +} + +ssize_t gpo_ddr_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,NULL,NULL)); +} + +ssize_t gpo_data_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",((gpo_t *)cls->class_data)->shadow); +} + +ssize_t gpo_data_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,((gpo_t *)cls->class_data)->data,&((gpo_t *)cls->class_data)->shadow)); +} + +/** + * create a new gpo device + * TODO add printf formatting support for the name + */ +struct class_device *gpo_device_create(void *data,const char *name){ + static CLASS_DEVICE_ATTR(ddr,S_IRUGO|S_IWUGO,gpo_ddr_show,gpo_ddr_store); + static CLASS_DEVICE_ATTR(data,S_IRUGO|S_IWUGO,gpo_data_show,gpo_data_store); + + if(gpioclass){ + struct class_device *dev = class_device_create(gpioclass, NULL, MKDEV(0, 0), NULL, name); + gpo_t *gpo_pd = kmalloc(sizeof(gpo_t),GFP_KERNEL); + printk("registering gpo device: %s\n",name); + + gpo_pd->data = data; + gpo_pd->shadow = 0; + dev->class_data = gpo_pd; + + class_device_create_file(dev,&class_device_attr_ddr); + class_device_create_file(dev,&class_device_attr_data); + + return dev; + } + return NULL; +} + +/************************************************************************************ + * gpi ports, gpi ports are functionally the same as gpio input only ports, + * but their ddr ports are not implemented in hardware + * and are assumed based upon the PLD key. + * This is a cheaper gate implementation. + */ +typedef struct gpi_s{ + void *data; +}gpi_t; + + +ssize_t gpi_ddr_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",0); +} + +ssize_t gpi_ddr_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,NULL,NULL)); +} + +ssize_t gpi_data_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",ioread8(((gpo_t *)cls->class_data)->data)); +} + +ssize_t gpi_data_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,NULL,NULL)); +} + +/** + * create a new gpo device + * TODO add printf formatting support for the name + */ +struct class_device *gpi_device_create(void *data,const char *name){ + static CLASS_DEVICE_ATTR(ddr,S_IRUGO|S_IWUGO,gpi_ddr_show,gpi_ddr_store); + static CLASS_DEVICE_ATTR(data,S_IRUGO|S_IWUGO,gpi_data_show,gpi_data_store); + + if(gpioclass){ + struct class_device *dev = class_device_create(gpioclass, NULL, MKDEV(0, 0), NULL, name); + gpi_t *gpi_pd = kmalloc(sizeof(gpi_t),GFP_KERNEL); + printk("registering gpi device: %s\n",name); + + gpi_pd->data = data; + dev->class_data = gpi_pd; + + class_device_create_file(dev,&class_device_attr_ddr); + class_device_create_file(dev,&class_device_attr_data); + + return dev; + } + return NULL; +} + + + + + + diff -urN -x CVS linux-2.6.20/drivers/misc/classes/Kconfig linux-2.6.20-AT91/drivers/misc/classes/Kconfig --- linux-2.6.20/drivers/misc/classes/Kconfig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/misc/classes/Kconfig 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,34 @@ +# +# Input device configuration +# + +menu "misc device classes" + +config GPIOCLASS + bool "GPIO class" + ---help--- + This is a set of classes for general purpose io ports. + It allows the creation of gpio classes w + hich can be read/written/configured through sysfs + These devices typically contain a data register, + which holds the current state of the pins, and a ddr register, + which sets the pin to input or output, 0 or 1 respectively + +config PWMCLASS + bool "PWM class" + ---help--- + This is a set of classes for pulse width modulation. + It allows the creation of pwm classes which can be configured + through sysfs. PWM devices typically contain a + duty and frequency configuration register. + +config EP93XX_PWM + depends on PWMCLASS && ARCH_EP93XX + bool "ep93xx PWM device support" + ---help--- + Support control of the ep93xx PWM devices + through the PWM class +endmenu + + + diff -urN -x CVS linux-2.6.20/drivers/misc/classes/Makefile linux-2.6.20-AT91/drivers/misc/classes/Makefile --- linux-2.6.20/drivers/misc/classes/Makefile 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/misc/classes/Makefile 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,9 @@ +# +# Makefile for the ioex classes +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_GPIOCLASS) += gpio.o +obj-$(CONFIG_PWMCLASS) += pwm.o + diff -urN -x CVS linux-2.6.20/drivers/misc/classes/pwm.c linux-2.6.20-AT91/drivers/misc/classes/pwm.c --- linux-2.6.20/drivers/misc/classes/pwm.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/misc/classes/pwm.c 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,157 @@ +/** + * A class for simple pwm ports + * Several types of devices are available + * which all export the same basic functionity + * through differnet underlying methods + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************ + * the global device class + */ +static struct class *pwmclass = NULL; + +struct class *pwm_declare(void){ + if(!pwmclass){ + printk("registering PWM class\n"); + pwmclass=class_create(THIS_MODULE,"pwm"); + } +return pwmclass; +} + +/************************************************************************************ + * pwmd - duty only pwm + * These pwm devices can only modify the duty cycle of an external frequency. + * They therefore have only one register, the 8 bit duty cycle. + */ +typedef struct pwmd_s{ + u8 *duty; + u8 duty_shadow; +}pwmd_t; + +ssize_t pwmd_duty_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",((pwmd_t *)cls->class_data)->duty_shadow); +} + +ssize_t pwmd_duty_store(struct class_device *cls, const char *buf,size_t count){ + return(store8(buf,count,((pwmd_t *)cls->class_data)->duty,&((pwmd_t *)cls->class_data)->duty_shadow)); +} + +/** + * create a new pwmd device + * TODO add printf formatting support for the name + */ +struct class_device *pwmd_device_create(void *duty, const char *name){ + static CLASS_DEVICE_ATTR(duty,S_IRUGO|S_IWUGO, + pwmd_duty_show, + pwmd_duty_store); + + if(pwmclass){ + struct class_device *dev = class_device_create(pwmclass, NULL, MKDEV(0, 0), NULL, name); + pwmd_t *pwmd_pd = kmalloc(sizeof(pwmd_t),GFP_KERNEL); + printk("registering pwmd device: %s\n",name); + + pwmd_pd->duty = duty; + pwmd_pd->duty_shadow = 0; + dev->class_data = pwmd_pd; + + class_device_create_file(dev,&class_device_attr_duty); + + return dev; + } + return NULL; +} + +#ifdef CONFIG_EP93XX_PWM +/************************************************************************************ + * ep93xx_pwm - ep93xx style pwm + * the ep93xx pwm contains 2 16 bit registers for frequency and duty, and 1 control register + * for inverting the frequency + */ +typedef struct ep93xx_pwm_s{ + u16 *duty; + u16 *freq; + u16 *control; + u16 imask; +}ep93xx_pwm_t; + +ssize_t ep93xx_pwm_duty_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",ioread16(((ep93xx_pwm_t *)cls->class_data)->duty)); +} + +ssize_t ep93xx_pwm_duty_store(struct class_device *cls, const char *buf,size_t count){ + return(store16(buf,count,((ep93xx_pwm_t *)cls->class_data)->duty,NULL)); +} + +ssize_t ep93xx_pwm_freq_show(struct class_device *cls, char *buf){ + return sprintf(buf,"%x\r\n",ioread16(((ep93xx_pwm_t *)cls->class_data)->freq)); +} + +ssize_t ep93xx_pwm_freq_store(struct class_device *cls, const char *buf,size_t count){ + return(store16(buf,count,((ep93xx_pwm_t *)cls->class_data)->freq,NULL)); +} + +ssize_t ep93xx_pwm_inv_show(struct class_device *cls, char *buf){ + ep93xx_pwm_t *pwm = cls->class_data; + return sprintf(buf,"%x\r\n",(ioread16(pwm->control)&pwm->imask)); +} + +ssize_t ep93xx_pwm_inv_store(struct class_device *cls, const char *buf,size_t count){ + size_t size; + u8 data = sfs_getint(buf,count,&size); + ep93xx_pwm_t *pwm = cls->class_data; + u16 pwmcontrol = (ioread16(pwm->control)&(!pwm->imask))|((data)?(pwm->imask):0); + iowrite16(pwmcontrol,pwm->control); + return size; +} + +/** + * create a new pwmd device + * TODO add printf formatting support for the name + */ +struct class_device *ep93xx_pwm_device_create(unsigned long base, const char *name){ + static CLASS_DEVICE_ATTR(duty,S_IRUGO|S_IWUGO, + ep93xx_pwm_duty_show, + ep93xx_pwm_duty_store); + + static CLASS_DEVICE_ATTR(freq,S_IRUGO|S_IWUGO, + ep93xx_pwm_freq_show, + ep93xx_pwm_freq_store); + + static CLASS_DEVICE_ATTR(invert,S_IRUGO|S_IWUGO, + ep93xx_pwm_inv_show, + ep93xx_pwm_inv_store); + + + if(pwmclass){ + struct class_device *dev = class_device_create(pwmclass, NULL, MKDEV(0, 0), NULL, name); + ep93xx_pwm_t *pwm_pd = kmalloc(sizeof(ep93xx_pwm_t),GFP_KERNEL); + printk("registering ep93xx_pwm device: %s\n",name); + + pwm_pd->freq = (u16 *)base; + pwm_pd->duty = (u16 *)(base+4); + pwm_pd->control = (u16 *)(base+12); + pwm_pd->imask = 1; + dev->class_data = pwm_pd; + + class_device_create_file(dev,&class_device_attr_duty); + class_device_create_file(dev,&class_device_attr_freq); + class_device_create_file(dev,&class_device_attr_invert); + + //enable PWM + iowrite16(1,(u16 *)(base+8)); + + return dev; + } + return NULL; +} +#endif //CONFIG_EP93XX_PWM + diff -urN -x CVS linux-2.6.20/drivers/misc/Kconfig linux-2.6.20-AT91/drivers/misc/Kconfig --- linux-2.6.20/drivers/misc/Kconfig 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/misc/Kconfig 2007-07-12 14:20:46.000000000 -0500 @@ -88,4 +88,6 @@ If you have an MSI S270 laptop, say Y or M here. +source "drivers/misc/classes/Kconfig" + endmenu diff -urN -x CVS linux-2.6.20/drivers/misc/Makefile linux-2.6.20-AT91/drivers/misc/Makefile --- linux-2.6.20/drivers/misc/Makefile 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/misc/Makefile 2007-07-12 14:20:46.000000000 -0500 @@ -10,3 +10,4 @@ obj-$(CONFIG_TIFM_CORE) += tifm_core.o obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o obj-$(CONFIG_SGI_IOC4) += ioc4.o +obj-y += classes/ \ No newline at end of file diff -urN -x CVS linux-2.6.20/drivers/net/Kconfig~ linux-2.6.20-AT91/drivers/net/Kconfig~ --- linux-2.6.20/drivers/net/Kconfig~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/net/Kconfig~ 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,2918 @@ + +# +# Network device configuration +# + +menu "Network device support" + depends on NET + +config NETDEVICES + default y if UML + bool "Network device support" + ---help--- + You can say N here if you don't intend to connect your Linux box to + any other computer at all. + + You'll have to say Y if your computer contains a network card that + you want to use under Linux. If you are going to run SLIP or PPP over + telephone line or null modem cable you need say Y here. Connecting + two machines with parallel ports using PLIP needs this, as well as + AX.25/KISS for sending Internet traffic over amateur radio links. + + See also "The Linux Network Administrator's Guide" by Olaf Kirch and + Terry Dawson. Available at . + + If unsure, say Y. + +# All the following symbols are dependent on NETDEVICES - do not repeat +# that for each of the symbols. +if NETDEVICES + +config IFB + tristate "Intermediate Functional Block support" + depends on NET_CLS_ACT + ---help--- + This is an intermediate driver that allows sharing of + resources. + To compile this driver as a module, choose M here: the module + will be called ifb. If you want to use more than one ifb + device at a time, you need to compile this driver as a module. + Instead of 'ifb', the devices will then be called 'ifb0', + 'ifb1' etc. + Look at the iproute2 documentation directory for usage etc + +config DUMMY + tristate "Dummy net driver support" + ---help--- + This is essentially a bit-bucket device (i.e. traffic you send to + this device is consigned into oblivion) with a configurable IP + address. It is most commonly used in order to make your currently + inactive SLIP address seem like a real address for local programs. + If you use SLIP or PPP, you might want to say Y here. Since this + thing often comes in handy, the default is Y. It won't enlarge your + kernel either. What a deal. Read about it in the Network + Administrator's Guide, available from + . + + To compile this driver as a module, choose M here: the module + will be called dummy. If you want to use more than one dummy + device at a time, you need to compile this driver as a module. + Instead of 'dummy', the devices will then be called 'dummy0', + 'dummy1' etc. + +config BONDING + tristate "Bonding driver support" + depends on INET + ---help--- + Say 'Y' or 'M' if you wish to be able to 'bond' multiple Ethernet + Channels together. This is called 'Etherchannel' by Cisco, + 'Trunking' by Sun, 802.3ad by the IEEE, and 'Bonding' in Linux. + + The driver supports multiple bonding modes to allow for both high + performance and high availability operation. + + Refer to for more + information. + + To compile this driver as a module, choose M here: the module + will be called bonding. + +config EQUALIZER + tristate "EQL (serial line load balancing) support" + ---help--- + If you have two serial connections to some other computer (this + usually requires two modems and two telephone lines) and you use + SLIP (the protocol for sending Internet traffic over telephone + lines) or PPP (a better SLIP) on them, you can make them behave like + one double speed connection using this driver. Naturally, this has + to be supported at the other end as well, either with a similar EQL + Linux driver or with a Livingston Portmaster 2e. + + Say Y if you want this and read + . You may also want to read + section 6.2 of the NET-3-HOWTO, available from + . + + To compile this driver as a module, choose M here: the module + will be called eql. If unsure, say N. + +config TUN + tristate "Universal TUN/TAP device driver support" + select CRC32 + ---help--- + TUN/TAP provides packet reception and transmission for user space + programs. It can be viewed as a simple Point-to-Point or Ethernet + device, which instead of receiving packets from a physical media, + receives them from user space program and instead of sending packets + via physical media writes them to the user space program. + + When a program opens /dev/net/tun, driver creates and registers + corresponding net device tunX or tapX. After a program closed above + devices, driver will automatically delete tunXX or tapXX device and + all routes corresponding to it. + + Please read for more + information. + + To compile this driver as a module, choose M here: the module + will be called tun. + + If you don't know what to use this for, you don't need it. + +config NET_SB1000 + tristate "General Instruments Surfboard 1000" + depends on PNP + ---help--- + This is a driver for the General Instrument (also known as + NextLevel) SURFboard 1000 internal + cable modem. This is an ISA card which is used by a number of cable + TV companies to provide cable modem access. It's a one-way + downstream-only cable modem, meaning that your upstream net link is + provided by your regular phone modem. + + At present this driver only compiles as a module, so say M here if + you have this card. The module will be called sb1000. Then read + for information on how + to use this module, as it needs special ppp scripts for establishing + a connection. Further documentation and the necessary scripts can be + found at: + + + + + + If you don't have this card, of course say N. + +source "drivers/net/arcnet/Kconfig" + +source "drivers/net/phy/Kconfig" + +# +# Ethernet +# + +menu "Ethernet (10 or 100Mbit)" + depends on !UML + +config NET_ETHERNET + bool "Ethernet (10 or 100Mbit)" + ---help--- + Ethernet (also called IEEE 802.3 or ISO 8802-2) is the most common + type of Local Area Network (LAN) in universities and companies. + + Common varieties of Ethernet are: 10BASE-2 or Thinnet (10 Mbps over + coaxial cable, linking computers in a chain), 10BASE-T or twisted + pair (10 Mbps over twisted pair cable, linking computers to central + hubs), 10BASE-F (10 Mbps over optical fiber links, using hubs), + 100BASE-TX (100 Mbps over two twisted pair cables, using hubs), + 100BASE-T4 (100 Mbps over 4 standard voice-grade twisted pair + cables, using hubs), 100BASE-FX (100 Mbps over optical fiber links) + [the 100BASE varieties are also known as Fast Ethernet], and Gigabit + Ethernet (1 Gbps over optical fiber or short copper links). + + If your Linux machine will be connected to an Ethernet and you have + an Ethernet network interface card (NIC) installed in your computer, + say Y here and read the Ethernet-HOWTO, available from + . You will then also have + to say Y to the driver for your particular NIC. + + Note that the answer to this question won't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Ethernet network cards. If unsure, say N. + +config MII + tristate "Generic Media Independent Interface device support" + depends on NET_ETHERNET + help + Most ethernet controllers have MII transceiver either as an external + or internal device. It is safe to say Y or M here even if your + ethernet card lack MII. + +config MACB + tristate "Atmel MACB support" + depends on NET_ETHERNET && AVR32 + select MII + help + The Atmel MACB ethernet interface is found on many AT32 and AT91 + parts. Say Y to include support for the MACB chip. + + To compile this driver as a module, choose M here: the module + will be called macb. + +source "drivers/net/arm/Kconfig" + +config MACE + tristate "MACE (Power Mac ethernet) support" + depends on NET_ETHERNET && PPC_PMAC && PPC32 + select CRC32 + help + Power Macintoshes and clones with Ethernet built-in on the + motherboard will usually use a MACE (Medium Access Control for + Ethernet) interface. Say Y to include support for the MACE chip. + + To compile this driver as a module, choose M here: the module + will be called mace. + +config MACE_AAUI_PORT + bool "Use AAUI port instead of TP by default" + depends on MACE + help + Some Apple machines (notably the Apple Network Server) which use the + MACE ethernet chip have an Apple AUI port (small 15-pin connector), + instead of an 8-pin RJ45 connector for twisted-pair ethernet. Say + Y here if you have such a machine. If unsure, say N. + The driver will default to AAUI on ANS anyway, and if you use it as + a module, you can provide the port_aaui=0|1 to force the driver. + +config BMAC + tristate "BMAC (G3 ethernet) support" + depends on NET_ETHERNET && PPC_PMAC && PPC32 + select CRC32 + help + Say Y for support of BMAC Ethernet interfaces. These are used on G3 + computers. + + To compile this driver as a module, choose M here: the module + will be called bmac. + +config OAKNET + tristate "National DP83902AV (Oak ethernet) support" + depends on NET_ETHERNET && PPC && BROKEN + select CRC32 + help + Say Y if your machine has this type of Ethernet network card. + + To compile this driver as a module, choose M here: the module + will be called oaknet. + +config ARIADNE + tristate "Ariadne support" + depends on NET_ETHERNET && ZORRO + help + If you have a Village Tronic Ariadne Ethernet adapter, say Y. + Otherwise, say N. + + To compile this driver as a module, choose M here: the module + will be called ariadne. + +config A2065 + tristate "A2065 support" + depends on NET_ETHERNET && ZORRO + select CRC32 + help + If you have a Commodore A2065 Ethernet adapter, say Y. Otherwise, + say N. + + To compile this driver as a module, choose M here: the module + will be called a2065. + +config HYDRA + tristate "Hydra support" + depends on NET_ETHERNET && ZORRO + select CRC32 + help + If you have a Hydra Ethernet adapter, say Y. Otherwise, say N. + + To compile this driver as a module, choose M here: the module + will be called hydra. + +config ZORRO8390 + tristate "Zorro NS8390-based Ethernet support" + depends on NET_ETHERNET && ZORRO + select CRC32 + help + This driver is for Zorro Ethernet cards using an NS8390-compatible + chipset, like the Village Tronic Ariadne II and the Individual + Computers X-Surf Ethernet cards. If you have such a card, say Y. + Otherwise, say N. + + To compile this driver as a module, choose M here: the module + will be called zorro8390. + +config APNE + tristate "PCMCIA NE2000 support" + depends on NET_ETHERNET && AMIGA_PCMCIA + select CRC32 + help + If you have a PCMCIA NE2000 compatible adapter, say Y. Otherwise, + say N. + + To compile this driver as a module, choose M here: the module + will be called apne. + +config APOLLO_ELPLUS + tristate "Apollo 3c505 support" + depends on NET_ETHERNET && APOLLO + help + Say Y or M here if your Apollo has a 3Com 3c505 ISA Ethernet card. + If you don't have one made for Apollos, you can use one from a PC, + except that your Apollo won't be able to boot from it (because the + code in the ROM will be for a PC). + +config MAC8390 + bool "Macintosh NS 8390 based ethernet cards" + depends on NET_ETHERNET && MAC + select CRC32 + help + If you want to include a driver to support Nubus or LC-PDS + Ethernet cards using an NS8390 chipset or its equivalent, say Y + and read the Ethernet-HOWTO, available from + . + +config MAC89x0 + tristate "Macintosh CS89x0 based ethernet cards" + depends on NET_ETHERNET && MAC && BROKEN + ---help--- + Support for CS89x0 chipset based Ethernet cards. If you have a + Nubus or LC-PDS network (Ethernet) card of this type, say Y and + read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . This module will + be called mac89x0. + +config MACSONIC + tristate "Macintosh SONIC based ethernet (onboard, NuBus, LC, CS)" + depends on NET_ETHERNET && MAC + ---help--- + Support for NatSemi SONIC based Ethernet devices. This includes + the onboard Ethernet in many Quadras as well as some LC-PDS, + a few Nubus and all known Comm Slot Ethernet cards. If you have + one of these say Y and read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . This module will + be called macsonic. + +config MACMACE + bool "Macintosh (AV) onboard MACE ethernet (EXPERIMENTAL)" + depends on NET_ETHERNET && MAC && EXPERIMENTAL + select CRC32 + help + Support for the onboard AMD 79C940 MACE Ethernet controller used in + the 660AV and 840AV Macintosh. If you have one of these Macintoshes + say Y and read the Ethernet-HOWTO, available from + . + +config MVME147_NET + tristate "MVME147 (Lance) Ethernet support" + depends on NET_ETHERNET && MVME147 + select CRC32 + help + Support for the on-board Ethernet interface on the Motorola MVME147 + single-board computer. Say Y here to include the + driver for this chip in your kernel. + To compile this driver as a module, choose M here. + +config MVME16x_NET + tristate "MVME16x Ethernet support" + depends on NET_ETHERNET && MVME16x + help + This is the driver for the Ethernet interface on the Motorola + MVME162, 166, 167, 172 and 177 boards. Say Y here to include the + driver for this chip in your kernel. + To compile this driver as a module, choose M here. + +config BVME6000_NET + tristate "BVME6000 Ethernet support" + depends on NET_ETHERNET && BVME6000 + help + This is the driver for the Ethernet interface on BVME4000 and + BVME6000 VME boards. Say Y here to include the driver for this chip + in your kernel. + To compile this driver as a module, choose M here. + +config ATARILANCE + tristate "Atari Lance support" + depends on NET_ETHERNET && ATARI + help + Say Y to include support for several Atari Ethernet adapters based + on the AMD Lance chipset: RieblCard (with or without battery), or + PAMCard VME (also the version by Rhotron, with different addresses). + +config ATARI_BIONET + tristate "BioNet-100 support" + depends on NET_ETHERNET && ATARI && ATARI_ACSI && BROKEN + help + Say Y to include support for BioData's BioNet-100 Ethernet adapter + for the ACSI port. The driver works (has to work...) with a polled + I/O scheme, so it's rather slow :-( + +config ATARI_PAMSNET + tristate "PAMsNet support" + depends on NET_ETHERNET && ATARI && ATARI_ACSI && BROKEN + help + Say Y to include support for the PAMsNet Ethernet adapter for the + ACSI port ("ACSI node"). The driver works (has to work...) with a + polled I/O scheme, so it's rather slow :-( + +config SUN3LANCE + tristate "Sun3/Sun3x on-board LANCE support" + depends on NET_ETHERNET && (SUN3 || SUN3X) + help + Most Sun3 and Sun3x motherboards (including the 3/50, 3/60 and 3/80) + featured an AMD Lance 10Mbit Ethernet controller on board; say Y + here to compile in the Linux driver for this and enable Ethernet. + General Linux information on the Sun 3 and 3x series (now + discontinued) is at + . + + If you're not building a kernel for a Sun 3, say N. + +config SUN3_82586 + bool "Sun3 on-board Intel 82586 support" + depends on NET_ETHERNET && SUN3 + help + This driver enables support for the on-board Intel 82586 based + Ethernet adapter found on Sun 3/1xx and 3/2xx motherboards. Note + that this driver does not support 82586-based adapters on additional + VME boards. + +config HPLANCE + bool "HP on-board LANCE support" + depends on NET_ETHERNET && DIO + select CRC32 + help + If you want to use the builtin "LANCE" Ethernet controller on an + HP300 machine, say Y here. + +config LASI_82596 + tristate "Lasi ethernet" + depends on NET_ETHERNET && PARISC && GSC_LASI + help + Say Y here to support the on-board Intel 82596 ethernet controller + built into Hewlett-Packard PA-RISC machines. + +config MIPS_JAZZ_SONIC + tristate "MIPS JAZZ onboard SONIC Ethernet support" + depends on NET_ETHERNET && MACH_JAZZ + help + This is the driver for the onboard card of MIPS Magnum 4000, + Acer PICA, Olivetti M700-10 and a few other identical OEM systems. + +config MIPS_AU1X00_ENET + bool "MIPS AU1000 Ethernet support" + depends on NET_ETHERNET && SOC_AU1X00 + select PHYLIB + select CRC32 + help + If you have an Alchemy Semi AU1X00 based system + say Y. Otherwise, say N. + +config NET_SB1250_MAC + tristate "SB1250 Ethernet support" + depends on NET_ETHERNET && SIBYTE_SB1xxx_SOC + +config SGI_IOC3_ETH + bool "SGI IOC3 Ethernet" + depends on NET_ETHERNET && PCI && SGI_IP27 + select CRC32 + select MII + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + +config SGI_IOC3_ETH_HW_RX_CSUM + bool "Receive hardware checksums" + depends on SGI_IOC3_ETH && INET + default y + help + The SGI IOC3 network adapter supports TCP and UDP checksums in + hardware to offload processing of these checksums from the CPU. At + the moment only acceleration of IPv4 is supported. This option + enables offloading for checksums on receive. If unsure, say Y. + +config SGI_IOC3_ETH_HW_TX_CSUM + bool "Transmit hardware checksums" + depends on SGI_IOC3_ETH && INET + default y + help + The SGI IOC3 network adapter supports TCP and UDP checksums in + hardware to offload processing of these checksums from the CPU. At + the moment only acceleration of IPv4 is supported. This option + enables offloading for checksums on transmit. If unsure, say Y. + +config MIPS_SIM_NET + tristate "MIPS simulator Network device (EXPERIMENTAL)" + depends on MIPS_SIM && EXPERIMENTAL + help + The MIPSNET device is a simple Ethernet network device which is + emulated by the MIPS Simulator. + If you are not using a MIPSsim or are unsure, say N. + +config SGI_O2MACE_ETH + tristate "SGI O2 MACE Fast Ethernet support" + depends on NET_ETHERNET && SGI_IP32=y + +config STNIC + tristate "National DP83902AV support" + depends on NET_ETHERNET && SUPERH + select CRC32 + help + Support for cards based on the National Semiconductor DP83902AV + ST-NIC Serial Network Interface Controller for Twisted Pair. This + is a 10Mbit/sec Ethernet controller. Product overview and specs at + . + + If unsure, say N. + +config SUNLANCE + tristate "Sun LANCE support" + depends on NET_ETHERNET && SBUS + select CRC32 + help + This driver supports the "le" interface present on all 32-bit Sparc + systems, on some older Ultra systems and as an Sbus option. These + cards are based on the AMD Lance chipset, which is better known + via the NE2100 cards. + + To compile this driver as a module, choose M here: the module + will be called sunlance. + +config HAPPYMEAL + tristate "Sun Happy Meal 10/100baseT support" + depends on NET_ETHERNET && (SBUS || PCI) + select CRC32 + help + This driver supports the "hme" interface present on most Ultra + systems and as an option on older Sbus systems. This driver supports + both PCI and Sbus devices. This driver also supports the "qfe" quad + 100baseT device available in both PCI and Sbus configurations. + + To compile this driver as a module, choose M here: the module + will be called sunhme. + +config SUNBMAC + tristate "Sun BigMAC 10/100baseT support (EXPERIMENTAL)" + depends on NET_ETHERNET && SBUS && EXPERIMENTAL + select CRC32 + help + This driver supports the "be" interface available as an Sbus option. + This is Sun's older 100baseT Ethernet device. + + To compile this driver as a module, choose M here: the module + will be called sunbmac. + +config SUNQE + tristate "Sun QuadEthernet support" + depends on NET_ETHERNET && SBUS + select CRC32 + help + This driver supports the "qe" 10baseT Ethernet device, available as + an Sbus option. Note that this is not the same as Quad FastEthernet + "qfe" which is supported by the Happy Meal driver instead. + + To compile this driver as a module, choose M here: the module + will be called sunqe. + +config SUNGEM + tristate "Sun GEM support" + depends on NET_ETHERNET && PCI + select CRC32 + help + Support for the Sun GEM chip, aka Sun GigabitEthernet/P 2.0. See also + . + +config CASSINI + tristate "Sun Cassini support" + depends on NET_ETHERNET && PCI + select CRC32 + help + Support for the Sun Cassini chip, aka Sun GigaSwift Ethernet. See also + + +config NET_VENDOR_3COM + bool "3COM cards" + depends on NET_ETHERNET && (ISA || EISA || MCA || PCI) + help + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from + . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about 3COM cards. If you say Y, you will be asked for + your specific card in the following questions. + +config EL1 + tristate "3c501 \"EtherLink\" support" + depends on NET_VENDOR_3COM && ISA + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . Also, consider buying a + new card, since the 3c501 is slow, broken, and obsolete: you will + have problems. Some people suggest to ping ("man ping") a nearby + machine every minute ("man cron") when using this card. + + To compile this driver as a module, choose M here and read + . The module + will be called 3c501. + +config EL2 + tristate "3c503 \"EtherLink II\" support" + depends on NET_VENDOR_3COM && ISA + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called 3c503. + +config ELPLUS + tristate "3c505 \"EtherLink Plus\" support" + depends on NET_VENDOR_3COM && ISA && ISA_DMA_API + ---help--- + Information about this network (Ethernet) card can be found in + . If you have a card of + this type, say Y and read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called 3c505. + +config EL16 + tristate "3c507 \"EtherLink 16\" support (EXPERIMENTAL)" + depends on NET_VENDOR_3COM && ISA && EXPERIMENTAL + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called 3c507. + +config EL3 + tristate "3c509/3c529 (MCA)/3c579 \"EtherLink III\" support" + depends on NET_VENDOR_3COM && (ISA || EISA || MCA) + ---help--- + If you have a network (Ethernet) card belonging to the 3Com + EtherLinkIII series, say Y and read the Ethernet-HOWTO, available + from . + + If your card is not working you may need to use the DOS + setup disk to disable Plug & Play mode, and to select the default + media type. + + To compile this driver as a module, choose M here and read + . The module + will be called 3c509. + +config 3C515 + tristate "3c515 ISA \"Fast EtherLink\"" + depends on NET_VENDOR_3COM && (ISA || EISA) && ISA_DMA_API + help + If you have a 3Com ISA EtherLink XL "Corkscrew" 3c515 Fast Ethernet + network card, say Y and read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called 3c515. + +config ELMC + tristate "3c523 \"EtherLink/MC\" support" + depends on NET_VENDOR_3COM && MCA_LEGACY + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called 3c523. + +config ELMC_II + tristate "3c527 \"EtherLink/MC 32\" support (EXPERIMENTAL)" + depends on NET_VENDOR_3COM && MCA && MCA_LEGACY + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called 3c527. + +config VORTEX + tristate "3c590/3c900 series (592/595/597) \"Vortex/Boomerang\" support" + depends on NET_VENDOR_3COM && (PCI || EISA) + select MII + ---help--- + This option enables driver support for a large number of 10Mbps and + 10/100Mbps EISA, PCI and PCMCIA 3Com network cards: + + "Vortex" (Fast EtherLink 3c590/3c592/3c595/3c597) EISA and PCI + "Boomerang" (EtherLink XL 3c900 or 3c905) PCI + "Cyclone" (3c540/3c900/3c905/3c980/3c575/3c656) PCI and Cardbus + "Tornado" (3c905) PCI + "Hurricane" (3c555/3cSOHO) PCI + + If you have such a card, say Y and read the Ethernet-HOWTO, + available from . More + specific information is in + and in the comments at + the beginning of . + + To compile this support as a module, choose M here and read + . + +config TYPHOON + tristate "3cr990 series \"Typhoon\" support" + depends on NET_VENDOR_3COM && PCI + select CRC32 + ---help--- + This option enables driver support for the 3cr990 series of cards: + + 3C990-TX, 3CR990-TX-95, 3CR990-TX-97, 3CR990-FX-95, 3CR990-FX-97, + 3CR990SVR, 3CR990SVR95, 3CR990SVR97, 3CR990-FX-95 Server, + 3CR990-FX-97 Server, 3C990B-TX-M, 3C990BSVR + + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called typhoon. + +config LANCE + tristate "AMD LANCE and PCnet (AT1500 and NE2100) support" + depends on NET_ETHERNET && ISA && ISA_DMA_API + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . Some LinkSys cards are + of this type. + + To compile this driver as a module, choose M here: the module + will be called lance. This is recommended. + +config NET_VENDOR_SMC + bool "Western Digital/SMC cards" + depends on NET_ETHERNET && (ISA || MCA || EISA || MAC) + help + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from + . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Western Digital cards. If you say Y, you will be + asked for your specific card in the following questions. + +config WD80x3 + tristate "WD80*3 support" + depends on NET_VENDOR_SMC && ISA + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called wd. + +config ULTRAMCA + tristate "SMC Ultra MCA support" + depends on NET_VENDOR_SMC && MCA + select CRC32 + help + If you have a network (Ethernet) card of this type and are running + an MCA based system (PS/2), say Y and read the Ethernet-HOWTO, + available from . + + To compile this driver as a module, choose M here and read + . The module + will be called smc-mca. + +config ULTRA + tristate "SMC Ultra support" + depends on NET_VENDOR_SMC && ISA + select CRC32 + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + Important: There have been many reports that, with some motherboards + mixing an SMC Ultra and an Adaptec AHA154x SCSI card (or compatible, + such as some BusLogic models) causes corruption problems with many + operating systems. The Linux smc-ultra driver has a work-around for + this but keep it in mind if you have such a SCSI card and have + problems. + + To compile this driver as a module, choose M here and read + . The module + will be called smc-ultra. + +config ULTRA32 + tristate "SMC Ultra32 EISA support" + depends on NET_VENDOR_SMC && EISA + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called smc-ultra32. + +config SMC91X + tristate "SMC 91C9x/91C1xxx support" + select CRC32 + select MII + depends on NET_ETHERNET && (ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00) + help + This is a driver for SMC's 91x series of Ethernet chipsets, + including the SMC91C94 and the SMC91C111. Say Y if you want it + compiled into the kernel, and read the file + and the Ethernet-HOWTO, + available from . + + This driver is also available as a module ( = code which can be + inserted in and removed from the running kernel whenever you want). + The module will be called smc91x. If you want to compile it as a + module, say M here and read as well + as . + +config SMC9194 + tristate "SMC 9194 support" + depends on NET_VENDOR_SMC && (ISA || MAC && BROKEN) + select CRC32 + ---help--- + This is support for the SMC9xxx based Ethernet cards. Choose this + option if you have a DELL laptop with the docking station, or + another SMC9192/9194 based chipset. Say Y if you want it compiled + into the kernel, and read the file + and the Ethernet-HOWTO, + available from . + + To compile this driver as a module, choose M here and read + . The module + will be called smc9194. + +config NET_NETX + tristate "NetX Ethernet support" + select MII + depends on NET_ETHERNET && ARCH_NETX + help + This is support for the Hilscher netX builtin Ethernet ports + + To compile this driver as a module, choose M here and read + . The module + will be called netx-eth. + +config DM9000 + tristate "DM9000 support" + depends on (ARM || MIPS) && NET_ETHERNET + select CRC32 + select MII + ---help--- + Support for DM9000 chipset. + + To compile this driver as a module, choose M here and read + . The module will be + called dm9000. + +config SMC911X + tristate "SMSC LAN911[5678] support" + select CRC32 + select MII + depends on NET_ETHERNET && ARCH_PXA + help + This is a driver for SMSC's LAN911x series of Ethernet chipsets + including the new LAN9115, LAN9116, LAN9117, and LAN9118. + Say Y if you want it compiled into the kernel, + and read the Ethernet-HOWTO, available from + . + + This driver is also available as a module. The module will be + called smc911x. If you want to compile it as a module, say M + here and read + +config NET_VENDOR_RACAL + bool "Racal-Interlan (Micom) NI cards" + depends on NET_ETHERNET && ISA + help + If you have a network (Ethernet) card belonging to this class, such + as the NI5010, NI5210 or NI6210, say Y and read the Ethernet-HOWTO, + available from . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about NI cards. If you say Y, you will be asked for + your specific card in the following questions. + +config NI5010 + tristate "NI5010 support (EXPERIMENTAL)" + depends on NET_VENDOR_RACAL && ISA && EXPERIMENTAL && BROKEN_ON_SMP + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . Note that this is still + experimental code. + + To compile this driver as a module, choose M here and read + . The module + will be called ni5010. + +config NI52 + tristate "NI5210 support" + depends on NET_VENDOR_RACAL && ISA + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called ni52. + +config NI65 + tristate "NI6510 support" + depends on NET_VENDOR_RACAL && ISA && ISA_DMA_API + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called ni65. + +source "drivers/net/tulip/Kconfig" + +config AT1700 + tristate "AT1700/1720 support (EXPERIMENTAL)" + depends on NET_ETHERNET && (ISA || MCA_LEGACY) && EXPERIMENTAL + select CRC32 + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called at1700. + +config DEPCA + tristate "DEPCA, DE10x, DE200, DE201, DE202, DE422 support" + depends on NET_ETHERNET && (ISA || EISA || MCA) + select CRC32 + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + as well as + . + + To compile this driver as a module, choose M here and read + . The module + will be called depca. + +config HP100 + tristate "HP 10/100VG PCLAN (ISA, EISA, PCI) support" + depends on NET_ETHERNET && (ISA || EISA || PCI) + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called hp100. + +config NET_ISA + bool "Other ISA cards" + depends on NET_ETHERNET && ISA + ---help--- + If your network (Ethernet) card hasn't been mentioned yet and its + bus system (that's the way the cards talks to the other components + of your computer) is ISA (as opposed to EISA, VLB or PCI), say Y. + Make sure you know the name of your card. Read the Ethernet-HOWTO, + available from . + + If unsure, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the remaining ISA network card questions. If you say Y, you will be + asked for your specific card in the following questions. + +config E2100 + tristate "Cabletron E21xx support" + depends on NET_ISA + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called e2100. + +config EWRK3 + tristate "EtherWORKS 3 (DE203, DE204, DE205) support" + depends on NET_ISA + select CRC32 + ---help--- + This driver supports the DE203, DE204 and DE205 network (Ethernet) + cards. If this is for you, say Y and read + in the kernel source as + well as the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called ewrk3. + +config EEXPRESS + tristate "EtherExpress 16 support" + depends on NET_ISA + ---help--- + If you have an EtherExpress16 network (Ethernet) card, say Y and + read the Ethernet-HOWTO, available from + . Note that the Intel + EtherExpress16 card used to be regarded as a very poor choice + because the driver was very unreliable. We now have a new driver + that should do better. + + To compile this driver as a module, choose M here and read + . The module + will be called eexpress. + +config EEXPRESS_PRO + tristate "EtherExpressPro support/EtherExpress 10 (i82595) support" + depends on NET_ISA + ---help--- + If you have a network (Ethernet) card of this type, say Y. This + driver supports Intel i82595{FX,TX} based boards. Note however + that the EtherExpress PRO/100 Ethernet card has its own separate + driver. Please read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called eepro. + +config HPLAN_PLUS + tristate "HP PCLAN+ (27247B and 27252A) support" + depends on NET_ISA + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called hp-plus. + +config HPLAN + tristate "HP PCLAN (27245 and other 27xxx series) support" + depends on NET_ISA + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called hp. + +config LP486E + tristate "LP486E on board Ethernet" + depends on NET_ISA + help + Say Y here to support the 82596-based on-board Ethernet controller + for the Panther motherboard, which is one of the two shipped in the + Intel Professional Workstation. + +config ETH16I + tristate "ICL EtherTeam 16i/32 support" + depends on NET_ISA + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called eth16i. + +config NE2000 + tristate "NE2000/NE1000 support" + depends on NET_ISA || (Q40 && m) || M32R + select CRC32 + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . Many Ethernet cards + without a specific driver are compatible with NE2000. + + If you have a PCI NE2000 card however, say N here and Y to "PCI + NE2000 and clone support" under "EISA, VLB, PCI and on board + controllers" below. If you have a NE2000 card and are running on + an MCA system (a bus system used on some IBM PS/2 computers and + laptops), say N here and Y to "NE/2 (ne2000 MCA version) support", + below. + + To compile this driver as a module, choose M here and read + . The module + will be called ne. + +config ZNET + tristate "Zenith Z-Note support (EXPERIMENTAL)" + depends on NET_ISA && EXPERIMENTAL && ISA_DMA_API + help + The Zenith Z-Note notebook computer has a built-in network + (Ethernet) card, and this is the Linux driver for it. Note that the + IBM Thinkpad 300 is compatible with the Z-Note and is also supported + by this driver. Read the Ethernet-HOWTO, available from + . + +config SEEQ8005 + tristate "SEEQ8005 support (EXPERIMENTAL)" + depends on NET_ISA && EXPERIMENTAL + help + This is a driver for the SEEQ 8005 network (Ethernet) card. If this + is for you, read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called seeq8005. + +config SKMC + tristate "SKnet MCA support" + depends on NET_ETHERNET && MCA && BROKEN + ---help--- + These are Micro Channel Ethernet adapters. You need to say Y to "MCA + support" in order to use this driver. Supported cards are the SKnet + Junior MC2 and the SKnet MC2(+). The driver automatically + distinguishes between the two cards. Note that using multiple boards + of different type hasn't been tested with this driver. Say Y if you + have one of these Ethernet adapters. + + To compile this driver as a module, choose M here and read + . The module + will be called sk_mca. + +config NE2_MCA + tristate "NE/2 (ne2000 MCA version) support" + depends on NET_ETHERNET && MCA_LEGACY + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called ne2. + +config IBMLANA + tristate "IBM LAN Adapter/A support" + depends on NET_ETHERNET && MCA && MCA_LEGACY + ---help--- + This is a Micro Channel Ethernet adapter. You need to set + CONFIG_MCA to use this driver. It is both available as an in-kernel + driver and as a module. + + To compile this driver as a module, choose M here and read + . The only + currently supported card is the IBM LAN Adapter/A for Ethernet. It + will both support 16K and 32K memory windows, however a 32K window + gives a better security against packet losses. Usage of multiple + boards with this driver should be possible, but has not been tested + up to now due to lack of hardware. + +config IBMVETH + tristate "IBM LAN Virtual Ethernet support" + depends on NET_ETHERNET && PPC_PSERIES + ---help--- + This driver supports virtual ethernet adapters on newer IBM iSeries + and pSeries systems. + + To compile this driver as a module, choose M here and read + . The module will + be called ibmveth. + +config IBM_EMAC + tristate "PowerPC 4xx on-chip Ethernet support" + depends on 4xx + help + This driver supports the PowerPC 4xx EMAC family of on-chip + Ethernet controllers. + +config IBM_EMAC_RXB + int "Number of receive buffers" + depends on IBM_EMAC + default "128" + +config IBM_EMAC_TXB + int "Number of transmit buffers" + depends on IBM_EMAC + default "64" + +config IBM_EMAC_POLL_WEIGHT + int "MAL NAPI polling weight" + depends on IBM_EMAC + default "32" + +config IBM_EMAC_RX_COPY_THRESHOLD + int "RX skb copy threshold (bytes)" + depends on IBM_EMAC + default "256" + +config IBM_EMAC_RX_SKB_HEADROOM + int "Additional RX skb headroom (bytes)" + depends on IBM_EMAC + default "0" + help + Additional receive skb headroom. Note, that driver + will always reserve at least 2 bytes to make IP header + aligned, so usually there is no need to add any additional + headroom. + + If unsure, set to 0. + +config IBM_EMAC_PHY_RX_CLK_FIX + bool "PHY Rx clock workaround" + depends on IBM_EMAC && (405EP || 440GX || 440EP || 440GR) + help + Enable this if EMAC attached to a PHY which doesn't generate + RX clock if there is no link, if this is the case, you will + see "TX disable timeout" or "RX disable timeout" in the system + log. + + If unsure, say N. + +config IBM_EMAC_DEBUG + bool "Debugging" + depends on IBM_EMAC + default n + +config IBM_EMAC_ZMII + bool + depends on IBM_EMAC && (NP405H || NP405L || 44x) + default y + +config IBM_EMAC_RGMII + bool + depends on IBM_EMAC && 440GX + default y + +config IBM_EMAC_TAH + bool + depends on IBM_EMAC && 440GX + default y + +config NET_PCI + bool "EISA, VLB, PCI and on board controllers" + depends on NET_ETHERNET && (ISA || EISA || PCI) + help + This is another class of network cards which attach directly to the + bus. If you have one of those, say Y and read the Ethernet-HOWTO, + available from . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about this class of network cards. If you say Y, you + will be asked for your specific card in the following questions. If + you are unsure, say Y. + +config PCNET32 + tristate "AMD PCnet32 PCI support" + depends on NET_PCI && PCI + select CRC32 + select MII + help + If you have a PCnet32 or PCnetPCI based network (Ethernet) card, + answer Y here and read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called pcnet32. + +config PCNET32_NAPI + bool "Use RX polling (NAPI) (EXPERIMENTAL)" + depends on PCNET32 && EXPERIMENTAL + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config AMD8111_ETH + tristate "AMD 8111 (new PCI lance) support" + depends on NET_PCI && PCI + select CRC32 + select MII + help + If you have an AMD 8111-based PCI lance ethernet card, + answer Y here and read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called amd8111e. +config AMD8111E_NAPI + bool "Enable NAPI support" + depends on AMD8111_ETH + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config ADAPTEC_STARFIRE + tristate "Adaptec Starfire/DuraLAN support" + depends on NET_PCI && PCI + select CRC32 + select MII + help + Say Y here if you have an Adaptec Starfire (or DuraLAN) PCI network + adapter. The DuraLAN chip is used on the 64 bit PCI boards from + Adaptec e.g. the ANA-6922A. The older 32 bit boards use the tulip + driver. + + To compile this driver as a module, choose M here: the module + will be called starfire. This is recommended. + +config ADAPTEC_STARFIRE_NAPI + bool "Use Rx Polling (NAPI) (EXPERIMENTAL)" + depends on ADAPTEC_STARFIRE && EXPERIMENTAL + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config AC3200 + tristate "Ansel Communications EISA 3200 support (EXPERIMENTAL)" + depends on NET_PCI && (ISA || EISA) && EXPERIMENTAL + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called ac3200. + +config APRICOT + tristate "Apricot Xen-II on board Ethernet" + depends on NET_PCI && ISA + help + If you have a network (Ethernet) controller of this type, say Y and + read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module will be + called apricot. + +config B44 + tristate "Broadcom 4400 ethernet support" + depends on NET_PCI && PCI + select MII + help + If you have a network (Ethernet) controller of this type, say Y and + read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module will be + called b44. + +config FORCEDETH + tristate "nForce Ethernet support" + depends on NET_PCI && PCI + help + If you have a network (Ethernet) controller of this type, say Y and + read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module will be + called forcedeth. + +config FORCEDETH_NAPI + bool "Use Rx and Tx Polling (NAPI) (EXPERIMENTAL)" + depends on FORCEDETH && EXPERIMENTAL + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config CS89x0 + tristate "CS89x0 support" + depends on NET_PCI && (ISA || MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X) + ---help--- + Support for CS89x0 chipset based Ethernet cards. If you have a + network (Ethernet) card of this type, say Y and read the + Ethernet-HOWTO, available from + as well as + . + + To compile this driver as a module, choose M here and read + . The module will be + called cs89x0. + +config TC35815 + tristate "TOSHIBA TC35815 Ethernet support" + depends on NET_PCI && PCI && TOSHIBA_JMR3927 + +config DGRS + tristate "Digi Intl. RightSwitch SE-X support" + depends on NET_PCI && (PCI || EISA) + ---help--- + This is support for the Digi International RightSwitch series of + PCI/EISA Ethernet switch cards. These include the SE-4 and the SE-6 + models. If you have a network card of this type, say Y and read the + Ethernet-HOWTO, available from + . More specific + information is contained in . + + To compile this driver as a module, choose M here and read + . The module + will be called dgrs. + +config EEPRO100 + tristate "EtherExpressPro/100 support (eepro100, original Becker driver)" + depends on NET_PCI && PCI + select MII + help + If you have an Intel EtherExpress PRO/100 PCI network (Ethernet) + card, say Y and read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called eepro100. + + +config E100 + tristate "Intel(R) PRO/100+ support" + depends on NET_PCI && PCI + select MII + ---help--- + This driver supports Intel(R) PRO/100 family of adapters. + To verify that your adapter is supported, find the board ID number + on the adapter. Look for a label that has a barcode and a number + in the format 123456-001 (six digits hyphen three digits). + + Use the above information and the Adapter & Driver ID Guide at: + + + + to identify the adapter. + + For the latest Intel PRO/100 network driver for Linux, see: + + + + More specific information on configuring the driver is in + . + + To compile this driver as a module, choose M here and read + . The module + will be called e100. + +config LNE390 + tristate "Mylex EISA LNE390A/B support (EXPERIMENTAL)" + depends on NET_PCI && EISA && EXPERIMENTAL + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called lne390. + +config FEALNX + tristate "Myson MTD-8xx PCI Ethernet support" + depends on NET_PCI && PCI + select CRC32 + select MII + help + Say Y here to support the Mysom MTD-800 family of PCI-based Ethernet + cards. Specifications and data at + . + +config NATSEMI + tristate "National Semiconductor DP8381x series PCI Ethernet support" + depends on NET_PCI && PCI + select CRC32 + help + This driver is for the National Semiconductor DP83810 series, + which is used in cards from PureData, NetGear, Linksys + and others, including the 83815 chip. + More specific information and updates are available from + . + +config NE2K_PCI + tristate "PCI NE2000 and clones support (see help)" + depends on NET_PCI && PCI + select CRC32 + ---help--- + This driver is for NE2000 compatible PCI cards. It will not work + with ISA NE2000 cards (they have their own driver, "NE2000/NE1000 + support" below). If you have a PCI NE2000 network (Ethernet) card, + say Y and read the Ethernet-HOWTO, available from + . + + This driver also works for the following NE2000 clone cards: + RealTek RTL-8029 Winbond 89C940 Compex RL2000 KTI ET32P2 + NetVin NV5000SC Via 86C926 SureCom NE34 Winbond + Holtek HT80232 Holtek HT80229 + + To compile this driver as a module, choose M here and read + . The module + will be called ne2k-pci. + +config NE3210 + tristate "Novell/Eagle/Microdyne NE3210 EISA support (EXPERIMENTAL)" + depends on NET_PCI && EISA && EXPERIMENTAL + select CRC32 + ---help--- + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . Note that this driver + will NOT WORK for NE3200 cards as they are completely different. + + To compile this driver as a module, choose M here and read + . The module + will be called ne3210. + +config ES3210 + tristate "Racal-Interlan EISA ES3210 support (EXPERIMENTAL)" + depends on NET_PCI && EISA && EXPERIMENTAL + select CRC32 + help + If you have a network (Ethernet) card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module + will be called es3210. + +config 8139CP + tristate "RealTek RTL-8139 C+ PCI Fast Ethernet Adapter support (EXPERIMENTAL)" + depends on NET_PCI && PCI && EXPERIMENTAL + select CRC32 + select MII + help + This is a driver for the Fast Ethernet PCI network cards based on + the RTL8139C+ chips. If you have one of those, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here: the module + will be called 8139cp. This is recommended. + +config 8139TOO + tristate "RealTek RTL-8129/8130/8139 PCI Fast Ethernet Adapter support" + depends on NET_PCI && PCI + select CRC32 + select MII + ---help--- + This is a driver for the Fast Ethernet PCI network cards based on + the RTL 8129/8130/8139 chips. If you have one of those, say Y and + read the Ethernet-HOWTO . + + To compile this driver as a module, choose M here: the module + will be called 8139too. This is recommended. + +config 8139TOO_PIO + bool "Use PIO instead of MMIO" + default y + depends on 8139TOO + help + This instructs the driver to use programmed I/O ports (PIO) instead + of PCI shared memory (MMIO). This can possibly solve some problems + in case your mainboard has memory consistency issues. If unsure, + say N. + +config 8139TOO_TUNE_TWISTER + bool "Support for uncommon RTL-8139 rev. K (automatic channel equalization)" + depends on 8139TOO + help + This implements a function which might come in handy in case you + are using low quality on long cabling. It is required for RealTek + RTL-8139 revision K boards, and totally unused otherwise. It tries + to match the transceiver to the cable characteristics. This is + experimental since hardly documented by the manufacturer. + If unsure, say Y. + +config 8139TOO_8129 + bool "Support for older RTL-8129/8130 boards" + depends on 8139TOO + help + This enables support for the older and uncommon RTL-8129 and + RTL-8130 chips, which support MII via an external transceiver, + instead of an internal one. Disabling this option will save some + memory by making the code size smaller. If unsure, say Y. + +config 8139_OLD_RX_RESET + bool "Use older RX-reset method" + depends on 8139TOO + help + The 8139too driver was recently updated to contain a more rapid + reset sequence, in the face of severe receive errors. This "new" + RX-reset method should be adequate for all boards. But if you + experience problems, you can enable this option to restore the + old RX-reset behavior. If unsure, say N. + +config SIS900 + tristate "SiS 900/7016 PCI Fast Ethernet Adapter support" + depends on NET_PCI && PCI + select CRC32 + select MII + ---help--- + This is a driver for the Fast Ethernet PCI network cards based on + the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in + SiS 630 and SiS 540 chipsets. + + This driver also supports AMD 79C901 HomePNA so that you can use + your phone line as a network cable. + + To compile this driver as a module, choose M here: the module + will be called sis900. This is recommended. + +config EPIC100 + tristate "SMC EtherPower II" + depends on NET_PCI && PCI + select CRC32 + select MII + help + This driver is for the SMC EtherPower II 9432 PCI Ethernet NIC, + which is based on the SMC83c17x (EPIC/100). + More specific information and updates are available from + . + +config SUNDANCE + tristate "Sundance Alta support" + depends on NET_PCI && PCI + select CRC32 + select MII + help + This driver is for the Sundance "Alta" chip. + More specific information and updates are available from + . + +config SUNDANCE_MMIO + bool "Use MMIO instead of PIO" + depends on SUNDANCE + help + Enable memory-mapped I/O for interaction with Sundance NIC registers. + Do NOT enable this by default, PIO (enabled when MMIO is disabled) + is known to solve bugs on certain chips. + + If unsure, say N. + +config TLAN + tristate "TI ThunderLAN support" + depends on NET_PCI && (PCI || EISA) && !64BIT + ---help--- + If you have a PCI Ethernet network card based on the ThunderLAN chip + which is supported by this driver, say Y and read the + Ethernet-HOWTO, available from + . + + Devices currently supported by this driver are Compaq Netelligent, + Compaq NetFlex and Olicom cards. Please read the file + for more details. + + To compile this driver as a module, choose M here and read + . The module + will be called tlan. + + Please email feedback to . + +config VIA_RHINE + tristate "VIA Rhine support" + depends on NET_PCI && PCI + select CRC32 + select MII + help + If you have a VIA "Rhine" based network card (Rhine-I (VT86C100A), + Rhine-II (VT6102), or Rhine-III (VT6105)), say Y here. Rhine-type + Ethernet functions can also be found integrated on South Bridges + (e.g. VT8235). + + To compile this driver as a module, choose M here. The module + will be called via-rhine. + +config VIA_RHINE_MMIO + bool "Use MMIO instead of PIO" + depends on VIA_RHINE + help + This instructs the driver to use PCI shared memory (MMIO) instead of + programmed I/O ports (PIO). Enabling this gives an improvement in + processing time in parts of the driver. + + If unsure, say Y. + +config VIA_RHINE_NAPI + bool "Use Rx Polling (NAPI)" + depends on VIA_RHINE + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + +config LAN_SAA9730 + bool "Philips SAA9730 Ethernet support" + depends on NET_PCI && PCI && MIPS_ATLAS + help + The SAA9730 is a combined multimedia and peripheral controller used + in thin clients, Internet access terminals, and diskless + workstations. + See . + +config NET_POCKET + bool "Pocket and portable adapters" + depends on NET_ETHERNET && PARPORT + ---help--- + Cute little network (Ethernet) devices which attach to the parallel + port ("pocket adapters"), commonly used with laptops. If you have + one of those, say Y and read the Ethernet-HOWTO, available from + . + + If you want to plug a network (or some other) card into the PCMCIA + (or PC-card) slot of your laptop instead (PCMCIA is the standard for + credit card size extension cards used by all modern laptops), you + need the pcmcia-cs package (location contained in the file + ) and you can say N here. + + Laptop users should read the Linux Laptop home page at + or + Tuxmobil - Linux on Mobile Computers at . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about this class of network devices. If you say Y, you + will be asked for your specific device in the following questions. + +config ATP + tristate "AT-LAN-TEC/RealTek pocket adapter support" + depends on NET_POCKET && PARPORT && X86 + select CRC32 + ---help--- + This is a network (Ethernet) device which attaches to your parallel + port. Read as well as the Ethernet-HOWTO, + available from , if you + want to use this. If you intend to use this driver, you should have + said N to the "Parallel printer support", because the two drivers + don't like each other. + + To compile this driver as a module, choose M here: the module + will be called atp. + +config DE600 + tristate "D-Link DE600 pocket adapter support" + depends on NET_POCKET && PARPORT + ---help--- + This is a network (Ethernet) device which attaches to your parallel + port. Read as well as the + Ethernet-HOWTO, available from + , if you want to use + this. It is possible to have several devices share a single parallel + port and it is safe to compile the corresponding drivers into the + kernel. + + To compile this driver as a module, choose M here: the module + will be called de600. + +config DE620 + tristate "D-Link DE620 pocket adapter support" + depends on NET_POCKET && PARPORT + ---help--- + This is a network (Ethernet) device which attaches to your parallel + port. Read as well as the + Ethernet-HOWTO, available from + , if you want to use + this. It is possible to have several devices share a single parallel + port and it is safe to compile the corresponding drivers into the + kernel. + + To compile this driver as a module, choose M here: the module + will be called de620. + +config SGISEEQ + tristate "SGI Seeq ethernet controller support" + depends on NET_ETHERNET && SGI_IP22 + help + Say Y here if you have an Seeq based Ethernet network card. This is + used in many Silicon Graphics machines. + +config DECLANCE + tristate "DEC LANCE ethernet controller support" + depends on NET_ETHERNET && MACH_DECSTATION + select CRC32 + help + This driver is for the series of Ethernet controllers produced by + DEC (now Compaq) based on the AMD Lance chipset, including the + DEPCA series. (This chipset is better known via the NE2100 cards.) + +config 68360_ENET + bool "Motorola 68360 ethernet controller" + depends on M68360 + help + Say Y here if you want to use the built-in ethernet controller of + the Motorola 68360 processor. + +config FEC + bool "FEC ethernet controller (of ColdFire CPUs)" + depends on M523x || M527x || M5272 || M528x || M520x + help + Say Y here if you want to use the built-in 10/100 Fast ethernet + controller on some Motorola ColdFire processors. + +config FEC2 + bool "Second FEC ethernet controller (on some ColdFire CPUs)" + depends on FEC + help + Say Y here if you want to use the second built-in 10/100 Fast + ethernet controller on some Motorola ColdFire processors. + +config NE_H8300 + tristate "NE2000 compatible support for H8/300" + depends on H8300 && NET_ETHERNET + help + Say Y here if you want to use the NE2000 compatible + controller on the Renesas H8/300 processor. + +source "drivers/net/fec_8xx/Kconfig" +source "drivers/net/fs_enet/Kconfig" + +endmenu + +# +# Gigabit Ethernet +# + +menu "Ethernet (1000 Mbit)" + depends on !UML + +config ACENIC + tristate "Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support" + depends on PCI + ---help--- + Say Y here if you have an Alteon AceNIC, 3Com 3C985(B), NetGear + GA620, SGI Gigabit or Farallon PN9000-SX PCI Gigabit Ethernet + adapter. The driver allows for using the Jumbo Frame option (9000 + bytes/frame) however it requires that your switches can handle this + as well. To enable Jumbo Frames, add `mtu 9000' to your ifconfig + line. + + To compile this driver as a module, choose M here: the + module will be called acenic. + +config ACENIC_OMIT_TIGON_I + bool "Omit support for old Tigon I based AceNICs" + depends on ACENIC + help + Say Y here if you only have Tigon II based AceNICs and want to leave + out support for the older Tigon I based cards which are no longer + being sold (ie. the original Alteon AceNIC and 3Com 3C985 (non B + version)). This will reduce the size of the driver object by + app. 100KB. If you are not sure whether your card is a Tigon I or a + Tigon II, say N here. + + The safe and default value for this is N. + +config DL2K + tristate "D-Link DL2000-based Gigabit Ethernet support" + depends on PCI + select CRC32 + help + This driver supports D-Link 2000-based gigabit ethernet cards, which + includes + D-Link DGE-550T Gigabit Ethernet Adapter. + D-Link DL2000-based Gigabit Ethernet Adapter. + + To compile this driver as a module, choose M here: the + module will be called dl2k. + +config E1000 + tristate "Intel(R) PRO/1000 Gigabit Ethernet support" + depends on PCI + ---help--- + This driver supports Intel(R) PRO/1000 gigabit ethernet family of + adapters. For more information on how to identify your adapter, go + to the Adapter & Driver ID Guide at: + + + + For general information and support, go to the Intel support + website at: + + + + More specific information on configuring the driver is in + . + + To compile this driver as a module, choose M here and read + . The module + will be called e1000. + +config E1000_NAPI + bool "Use Rx Polling (NAPI)" + depends on E1000 + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config E1000_DISABLE_PACKET_SPLIT + bool "Disable Packet Split for PCI express adapters" + depends on E1000 + help + Say Y here if you want to use the legacy receive path for PCI express + hardware. + + If in doubt, say N. + +source "drivers/net/ixp2000/Kconfig" + +config MYRI_SBUS + tristate "MyriCOM Gigabit Ethernet support" + depends on SBUS + help + This driver supports MyriCOM Sbus gigabit Ethernet cards. + + To compile this driver as a module, choose M here: the module + will be called myri_sbus. This is recommended. + +config NS83820 + tristate "National Semiconductor DP83820 support" + depends on PCI + help + This is a driver for the National Semiconductor DP83820 series + of gigabit ethernet MACs. Cards using this chipset include + the D-Link DGE-500T, PureData's PDP8023Z-TG, SMC's SMC9462TX, + SOHO-GA2000T, SOHO-GA2500T. The driver supports the use of + zero copy. + +config HAMACHI + tristate "Packet Engines Hamachi GNIC-II support" + depends on PCI + select MII + help + If you have a Gigabit Ethernet card of this type, say Y and read + the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here and read + . The module will be + called hamachi. + +config YELLOWFIN + tristate "Packet Engines Yellowfin Gigabit-NIC support (EXPERIMENTAL)" + depends on PCI && EXPERIMENTAL + select CRC32 + ---help--- + Say Y here if you have a Packet Engines G-NIC PCI Gigabit Ethernet + adapter or the SYM53C885 Ethernet controller. The Gigabit adapter is + used by the Beowulf Linux cluster project. See + for more + information about this driver in particular and Beowulf in general. + + To compile this driver as a module, choose M here: the module + will be called yellowfin. This is recommended. + +config R8169 + tristate "Realtek 8169 gigabit ethernet support" + depends on PCI + select CRC32 + ---help--- + Say Y here if you have a Realtek 8169 PCI Gigabit Ethernet adapter. + + To compile this driver as a module, choose M here: the module + will be called r8169. This is recommended. + +config R8169_NAPI + bool "Use Rx and Tx Polling (NAPI) (EXPERIMENTAL)" + depends on R8169 && EXPERIMENTAL + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config R8169_VLAN + bool "VLAN support" + depends on R8169 && VLAN_8021Q + ---help--- + Say Y here for the r8169 driver to support the functions required + by the kernel 802.1Q code. + + If in doubt, say Y. + +config SIS190 + tristate "SiS190/SiS191 gigabit ethernet support" + depends on PCI + select CRC32 + select MII + ---help--- + Say Y here if you have a SiS 190 PCI Fast Ethernet adapter or + a SiS 191 PCI Gigabit Ethernet adapter. Both are expected to + appear in lan on motherboard designs which are based on SiS 965 + and SiS 966 south bridge. + + To compile this driver as a module, choose M here: the module + will be called sis190. This is recommended. + +config SKGE + tristate "New SysKonnect GigaEthernet support" + depends on PCI + select CRC32 + ---help--- + This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx + and related Gigabit Ethernet adapters. It is a new smaller driver + with better performance and more complete ethtool support. + + It does not support the link failover and network management + features that "portable" vendor supplied sk98lin driver does. + + This driver supports adapters based on the original Yukon chipset: + Marvell 88E8001, Belkin F5D5005, CNet GigaCard, DLink DGE-530T, + Linksys EG1032/EG1064, 3Com 3C940/3C940B, SysKonnect SK-9871/9872. + + It does not support the newer Yukon2 chipset: a separate driver, + sky2, is provided for Yukon2-based adapters. + + To compile this driver as a module, choose M here: the module + will be called skge. This is recommended. + +config SKY2 + tristate "SysKonnect Yukon2 support (EXPERIMENTAL)" + depends on PCI + select CRC32 + ---help--- + This driver supports Gigabit Ethernet adapters based on the + Marvell Yukon 2 chipset: + Marvell 88E8021/88E8022/88E8035/88E8036/88E8038/88E8050/88E8052/ + 88E8053/88E8055/88E8061/88E8062, SysKonnect SK-9E21D/SK-9S21 + + There is companion driver for the older Marvell Yukon and + Genesis based adapters: skge. + + To compile this driver as a module, choose M here: the module + will be called sky2. This is recommended. + +config SK98LIN + tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support" + depends on PCI + ---help--- + Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx + compliant Gigabit Ethernet Adapter. + + This driver supports the original Yukon chipset. A cleaner driver is + also available (skge) which seems to work better than this one. + + This driver does not support the newer Yukon2 chipset. A separate + driver, sky2, is provided to support Yukon2-based adapters. + + The following adapters are supported by this driver: + - 3Com 3C940 Gigabit LOM Ethernet Adapter + - 3Com 3C941 Gigabit LOM Ethernet Adapter + - Allied Telesyn AT-2970LX Gigabit Ethernet Adapter + - Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter + - Allied Telesyn AT-2970SX Gigabit Ethernet Adapter + - Allied Telesyn AT-2970SX/2SC Gigabit Ethernet Adapter + - Allied Telesyn AT-2970TX Gigabit Ethernet Adapter + - Allied Telesyn AT-2970TX/2TX Gigabit Ethernet Adapter + - Allied Telesyn AT-2971SX Gigabit Ethernet Adapter + - Allied Telesyn AT-2971T Gigabit Ethernet Adapter + - Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45 + - EG1032 v2 Instant Gigabit Network Adapter + - EG1064 v2 Instant Gigabit Network Adapter + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte) + - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill) + - Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel) + - Marvell RDK-8001 Adapter + - Marvell RDK-8002 Adapter + - Marvell RDK-8003 Adapter + - Marvell RDK-8004 Adapter + - Marvell RDK-8006 Adapter + - Marvell RDK-8007 Adapter + - Marvell RDK-8008 Adapter + - Marvell RDK-8009 Adapter + - Marvell RDK-8010 Adapter + - Marvell RDK-8011 Adapter + - Marvell RDK-8012 Adapter + - Marvell RDK-8052 Adapter + - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit) + - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit) + - N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L) + - SK-9521 10/100/1000Base-T Adapter + - SK-9521 V2.0 10/100/1000Base-T Adapter + - SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T) + - SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter + - SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link) + - SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX) + - SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter + - SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link) + - SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX) + - SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter + - SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link) + - SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter + - SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition) + - SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter + - SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link) + - SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX) + - SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter + - SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link) + - SMC EZ Card 1000 (SMC9452TXV.2) + + The adapters support Jumbo Frames. + The dual link adapters support link-failover and dual port features. + Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support + the scatter-gather functionality with sendfile(). Please refer to + for more information about + optional driver parameters. + Questions concerning this driver may be addressed to: + + + If you want to compile this driver as a module ( = code which can be + inserted in and removed from the running kernel whenever you want), + say M here and read . The module will + be called sk98lin. This is recommended. + +config VIA_VELOCITY + tristate "VIA Velocity support" + depends on NET_PCI && PCI + select CRC32 + select CRC_CCITT + select MII + help + If you have a VIA "Velocity" based network card say Y here. + + To compile this driver as a module, choose M here. The module + will be called via-velocity. + +config TIGON3 + tristate "Broadcom Tigon3 support" + depends on PCI + help + This driver supports Broadcom Tigon3 based gigabit Ethernet cards. + + To compile this driver as a module, choose M here: the module + will be called tg3. This is recommended. + +config BNX2 + tristate "Broadcom NetXtremeII support" + depends on PCI + select CRC32 + select ZLIB_INFLATE + help + This driver supports Broadcom NetXtremeII gigabit Ethernet cards. + + To compile this driver as a module, choose M here: the module + will be called bnx2. This is recommended. + +config SPIDER_NET + tristate "Spider Gigabit Ethernet driver" + depends on PCI && PPC_IBM_CELL_BLADE + select FW_LOADER + help + This driver supports the Gigabit Ethernet chips present on the + Cell Processor-Based Blades from IBM. + +config TSI108_ETH + tristate "Tundra TSI108 gigabit Ethernet support" + depends on TSI108_BRIDGE + help + This driver supports Tundra TSI108 gigabit Ethernet ports. + To compile this driver as a module, choose M here: the module + will be called tsi108_eth. + +config GIANFAR + tristate "Gianfar Ethernet" + depends on 85xx || 83xx || PPC_86xx + select PHYLIB + help + This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx, + and MPC86xx family of chips, and the FEC on the 8540. + +config GFAR_NAPI + bool "NAPI Support" + depends on GIANFAR + +config UCC_GETH + tristate "Freescale QE UCC GETH" + depends on QUICC_ENGINE && UCC_FAST + help + This driver supports the Gigabit Ethernet mode of QE UCC. + QE can be found on MPC836x CPUs. + +config UGETH_NAPI + bool "NAPI Support" + depends on UCC_GETH + +config UGETH_MAGIC_PACKET + bool "Magic Packet detection support" + depends on UCC_GETH + +config UGETH_FILTERING + bool "Mac address filtering support" + depends on UCC_GETH + +config UGETH_TX_ON_DEMOND + bool "Transmit on Demond support" + depends on UCC_GETH + +config UGETH_HAS_GIGA + bool + depends on UCC_GETH && PPC_MPC836x + +config MV643XX_ETH + tristate "MV-643XX Ethernet support" + depends on MOMENCO_OCELOT_C || MOMENCO_JAGUAR_ATX || MV64360 || MOMENCO_OCELOT_3 || (PPC_MULTIPLATFORM && PPC32) + select MII + help + This driver supports the gigabit Ethernet on the Marvell MV643XX + chipset which is used in the Momenco Ocelot C and Jaguar ATX and + Pegasos II, amongst other PPC and MIPS boards. + +config MV643XX_ETH_0 + bool "MV-643XX Port 0" + depends on MV643XX_ETH + help + This enables support for Port 0 of the Marvell MV643XX Gigabit + Ethernet. + +config MV643XX_ETH_1 + bool "MV-643XX Port 1" + depends on MV643XX_ETH + help + This enables support for Port 1 of the Marvell MV643XX Gigabit + Ethernet. + +config MV643XX_ETH_2 + bool "MV-643XX Port 2" + depends on MV643XX_ETH + help + This enables support for Port 2 of the Marvell MV643XX Gigabit + Ethernet. + +config QLA3XXX + tristate "QLogic QLA3XXX Network Driver Support" + depends on PCI + help + This driver supports QLogic ISP3XXX gigabit Ethernet cards. + + To compile this driver as a module, choose M here: the module + will be called qla3xxx. + +endmenu + +# +# 10 Gigabit Ethernet +# + +menu "Ethernet (10000 Mbit)" + depends on !UML + +config CHELSIO_T1 + tristate "Chelsio 10Gb Ethernet support" + depends on PCI + select CRC32 + help + This driver supports Chelsio gigabit and 10-gigabit + Ethernet cards. More information about adapter features and + performance tuning is in . + + For general information about Chelsio and our products, visit + our website at . + + For customer support, please visit our customer support page at + . + + Please send feedback to . + + To compile this driver as a module, choose M here: the module + will be called cxgb. + +config CHELSIO_T1_1G + bool "Chelsio gigabit Ethernet support" + depends on CHELSIO_T1 + help + Enables support for Chelsio's gigabit Ethernet PCI cards. If you + are using only 10G cards say 'N' here. + +config CHELSIO_T1_NAPI + bool "Use Rx Polling (NAPI)" + depends on CHELSIO_T1 + default y + help + NAPI is a driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. + +config EHEA + tristate "eHEA Ethernet support" + depends on IBMEBUS + ---help--- + This driver supports the IBM pSeries eHEA ethernet adapter. + + To compile the driver as a module, choose M here. The module + will be called ehea. + +config IXGB + tristate "Intel(R) PRO/10GbE support" + depends on PCI + ---help--- + This driver supports Intel(R) PRO/10GbE family of + adapters. For more information on how to identify your adapter, go + to the Adapter & Driver ID Guide at: + + + + For general information and support, go to the Intel support + website at: + + + + More specific information on configuring the driver is in + . + + To compile this driver as a module, choose M here and read + . The module + will be called ixgb. + +config IXGB_NAPI + bool "Use Rx Polling (NAPI) (EXPERIMENTAL)" + depends on IXGB && EXPERIMENTAL + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config S2IO + tristate "S2IO 10Gbe XFrame NIC" + depends on PCI + ---help--- + This driver supports the 10Gbe XFrame NIC of S2IO. + More specific information on configuring the driver is in + . + +config S2IO_NAPI + bool "Use Rx Polling (NAPI) (EXPERIMENTAL)" + depends on S2IO && EXPERIMENTAL + help + NAPI is a new driver API designed to reduce CPU and interrupt load + when the driver is receiving lots of packets from the card. It is + still somewhat experimental and thus not yet enabled by default. + + If your estimated Rx load is 10kpps or more, or if the card will be + deployed on potentially unfriendly networks (e.g. in a firewall), + then say Y here. + + See for more + information. + + If in doubt, say N. + +config MYRI10GE + tristate "Myricom Myri-10G Ethernet support" + depends on PCI + select FW_LOADER + select CRC32 + ---help--- + This driver supports Myricom Myri-10G Dual Protocol interface in + Ethernet mode. If the eeprom on your board is not recent enough, + you will need a newer firmware image. + You may get this image or more information, at: + + + + To compile this driver as a module, choose M here and read + . The module + will be called myri10ge. + +config NETXEN_NIC + tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC" + depends on PCI + help + This enables the support for NetXen's Gigabit Ethernet card. + +endmenu + +source "drivers/net/tokenring/Kconfig" + +source "drivers/net/wireless/Kconfig" + +source "drivers/net/pcmcia/Kconfig" + +source "drivers/net/wan/Kconfig" + +source "drivers/atm/Kconfig" + +source "drivers/s390/net/Kconfig" + +config ISERIES_VETH + tristate "iSeries Virtual Ethernet driver support" + depends on PPC_ISERIES + +config RIONET + tristate "RapidIO Ethernet over messaging driver support" + depends on RAPIDIO + +config RIONET_TX_SIZE + int "Number of outbound queue entries" + depends on RIONET + default "128" + +config RIONET_RX_SIZE + int "Number of inbound queue entries" + depends on RIONET + default "128" + +config FDDI + bool "FDDI driver support" + depends on (PCI || EISA) + help + Fiber Distributed Data Interface is a high speed local area network + design; essentially a replacement for high speed Ethernet. FDDI can + run over copper or fiber. If you are connected to such a network and + want a driver for the FDDI card in your computer, say Y here (and + then also Y to the driver for your FDDI card, below). Most people + will say N. + +config DEFXX + tristate "Digital DEFEA and DEFPA adapter support" + depends on FDDI && (PCI || EISA) + help + This is support for the DIGITAL series of EISA (DEFEA) and PCI + (DEFPA) controllers which can connect you to a local FDDI network. + +config SKFP + tristate "SysKonnect FDDI PCI support" + depends on FDDI && PCI + ---help--- + Say Y here if you have a SysKonnect FDDI PCI adapter. + The following adapters are supported by this driver: + - SK-5521 (SK-NET FDDI-UP) + - SK-5522 (SK-NET FDDI-UP DAS) + - SK-5541 (SK-NET FDDI-FP) + - SK-5543 (SK-NET FDDI-LP) + - SK-5544 (SK-NET FDDI-LP DAS) + - SK-5821 (SK-NET FDDI-UP64) + - SK-5822 (SK-NET FDDI-UP64 DAS) + - SK-5841 (SK-NET FDDI-FP64) + - SK-5843 (SK-NET FDDI-LP64) + - SK-5844 (SK-NET FDDI-LP64 DAS) + - Netelligent 100 FDDI DAS Fibre SC + - Netelligent 100 FDDI SAS Fibre SC + - Netelligent 100 FDDI DAS UTP + - Netelligent 100 FDDI SAS UTP + - Netelligent 100 FDDI SAS Fibre MIC + + Read for information about + the driver. + + Questions concerning this driver can be addressed to: + + + To compile this driver as a module, choose M here: the module + will be called skfp. This is recommended. + +config HIPPI + bool "HIPPI driver support (EXPERIMENTAL)" + depends on EXPERIMENTAL && INET && PCI + help + HIgh Performance Parallel Interface (HIPPI) is a 800Mbit/sec and + 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI + can run over copper (25m) or fiber (300m on multi-mode or 10km on + single-mode). HIPPI networks are commonly used for clusters and to + connect to super computers. If you are connected to a HIPPI network + and have a HIPPI network card in your computer that you want to use + under Linux, say Y here (you must also remember to enable the driver + for your HIPPI card below). Most people will say N here. + +config ROADRUNNER + tristate "Essential RoadRunner HIPPI PCI adapter support (EXPERIMENTAL)" + depends on HIPPI && PCI + help + Say Y here if this is your PCI HIPPI network card. + + To compile this driver as a module, choose M here: the module + will be called rrunner. If unsure, say N. + +config ROADRUNNER_LARGE_RINGS + bool "Use large TX/RX rings (EXPERIMENTAL)" + depends on ROADRUNNER + help + If you say Y here, the RoadRunner driver will preallocate up to 2 MB + of additional memory to allow for fastest operation, both for + transmitting and receiving. This memory cannot be used by any other + kernel code or by user space programs. Say Y here only if you have + the memory. + +config PLIP + tristate "PLIP (parallel port) support" + depends on PARPORT + ---help--- + PLIP (Parallel Line Internet Protocol) is used to create a + reasonably fast mini network consisting of two (or, rarely, more) + local machines. A PLIP link from a Linux box is a popular means to + install a Linux distribution on a machine which doesn't have a + CD-ROM drive (a minimal system has to be transferred with floppies + first). The kernels on both machines need to have this PLIP option + enabled for this to work. + + The PLIP driver has two modes, mode 0 and mode 1. The parallel + ports (the connectors at the computers with 25 holes) are connected + with "null printer" or "Turbo Laplink" cables which can transmit 4 + bits at a time (mode 0) or with special PLIP cables, to be used on + bidirectional parallel ports only, which can transmit 8 bits at a + time (mode 1); you can find the wiring of these cables in + . The cables can be up to + 15m long. Mode 0 works also if one of the machines runs DOS/Windows + and has some PLIP software installed, e.g. the Crynwr PLIP packet + driver () + and winsock or NCSA's telnet. + + If you want to use PLIP, say Y and read the PLIP mini-HOWTO as well + as the NET-3-HOWTO, both available from + . Note that the PLIP + protocol has been changed and this PLIP driver won't work together + with the PLIP support in Linux versions 1.0.x. This option enlarges + your kernel by about 8 KB. + + To compile this driver as a module, choose M here and read + . The module will be + called plip. If unsure, say Y or M, in case you buy a laptop + later. + +config PPP + tristate "PPP (point-to-point protocol) support" + select SLHC + ---help--- + PPP (Point to Point Protocol) is a newer and better SLIP. It serves + the same purpose: sending Internet traffic over telephone (and other + serial) lines. Ask your access provider if they support it, because + otherwise you can't use it; most Internet access providers these + days support PPP rather than SLIP. + + To use PPP, you need an additional program called pppd as described + in the PPP-HOWTO, available at + . Make sure that you have + the version of pppd recommended in . + The PPP option enlarges your kernel by about 16 KB. + + There are actually two versions of PPP: the traditional PPP for + asynchronous lines, such as regular analog phone lines, and + synchronous PPP which can be used over digital ISDN lines for + example. If you want to use PPP over phone lines or other + asynchronous serial lines, you need to say Y (or M) here and also to + the next option, "PPP support for async serial ports". For PPP over + synchronous lines, you should say Y (or M) here and to "Support + synchronous PPP", below. + + If you said Y to "Version information on all symbols" above, then + you cannot compile the PPP driver into the kernel; you can then only + compile it as a module. To compile this driver as a module, choose M + here and read . + The module will be called ppp_generic. + +config PPP_MULTILINK + bool "PPP multilink support (EXPERIMENTAL)" + depends on PPP && EXPERIMENTAL + help + PPP multilink is a protocol (defined in RFC 1990) which allows you + to combine several (logical or physical) lines into one logical PPP + connection, so that you can utilize your full bandwidth. + + This has to be supported at the other end as well and you need a + version of the pppd daemon which understands the multilink protocol. + + If unsure, say N. + +config PPP_FILTER + bool "PPP filtering" + depends on PPP + help + Say Y here if you want to be able to filter the packets passing over + PPP interfaces. This allows you to control which packets count as + activity (i.e. which packets will reset the idle timer or bring up + a demand-dialed link) and which packets are to be dropped entirely. + You need to say Y here if you wish to use the pass-filter and + active-filter options to pppd. + + If unsure, say N. + +config PPP_ASYNC + tristate "PPP support for async serial ports" + depends on PPP + select CRC_CCITT + ---help--- + Say Y (or M) here if you want to be able to use PPP over standard + asynchronous serial ports, such as COM1 or COM2 on a PC. If you use + a modem (not a synchronous or ISDN modem) to contact your ISP, you + need this option. + + To compile this driver as a module, choose M here. + + If unsure, say Y. + +config PPP_SYNC_TTY + tristate "PPP support for sync tty ports" + depends on PPP + help + Say Y (or M) here if you want to be able to use PPP over synchronous + (HDLC) tty devices, such as the SyncLink adapter. These devices + are often used for high-speed leased lines like T1/E1. + + To compile this driver as a module, choose M here. + +config PPP_DEFLATE + tristate "PPP Deflate compression" + depends on PPP + select ZLIB_INFLATE + select ZLIB_DEFLATE + ---help--- + Support for the Deflate compression method for PPP, which uses the + Deflate algorithm (the same algorithm that gzip uses) to compress + each PPP packet before it is sent over the wire. The machine at the + other end of the PPP link (usually your ISP) has to support the + Deflate compression method as well for this to be useful. Even if + they don't support it, it is safe to say Y here. + + To compile this driver as a module, choose M here. + +config PPP_BSDCOMP + tristate "PPP BSD-Compress compression" + depends on PPP + ---help--- + Support for the BSD-Compress compression method for PPP, which uses + the LZW compression method to compress each PPP packet before it is + sent over the wire. The machine at the other end of the PPP link + (usually your ISP) has to support the BSD-Compress compression + method as well for this to be useful. Even if they don't support it, + it is safe to say Y here. + + The PPP Deflate compression method ("PPP Deflate compression", + above) is preferable to BSD-Compress, because it compresses better + and is patent-free. + + Note that the BSD compression code will always be compiled as a + module; it is called bsd_comp and will show up in the directory + modules once you have said "make modules". If unsure, say N. + +config PPP_MPPE + tristate "PPP MPPE compression (encryption) (EXPERIMENTAL)" + depends on PPP && EXPERIMENTAL + select CRYPTO + select CRYPTO_SHA1 + select CRYPTO_ARC4 + select CRYPTO_ECB + ---help--- + Support for the MPPE Encryption protocol, as employed by the + Microsoft Point-to-Point Tunneling Protocol. + + See http://pptpclient.sourceforge.net/ for information on + configuring PPTP clients and servers to utilize this method. + +config PPPOE + tristate "PPP over Ethernet (EXPERIMENTAL)" + depends on EXPERIMENTAL && PPP + help + Support for PPP over Ethernet. + + This driver requires the latest version of pppd from the CVS + repository at cvs.samba.org. Alternatively, see the + RoaringPenguin package () + which contains instruction on how to use this driver (under + the heading "Kernel mode PPPoE"). + +config PPPOATM + tristate "PPP over ATM" + depends on ATM && PPP + help + Support PPP (Point to Point Protocol) encapsulated in ATM frames. + This implementation does not yet comply with section 8 of RFC2364, + which can lead to bad results if the ATM peer loses state and + changes its encapsulation unilaterally. + +config SLIP + tristate "SLIP (serial line) support" + ---help--- + Say Y if you intend to use SLIP or CSLIP (compressed SLIP) to + connect to your Internet service provider or to connect to some + other local Unix box or if you want to configure your Linux box as a + Slip/CSlip server for other people to dial in. SLIP (Serial Line + Internet Protocol) is a protocol used to send Internet traffic over + serial connections such as telephone lines or null modem cables; + nowadays, the protocol PPP is more commonly used for this same + purpose. + + Normally, your access provider has to support SLIP in order for you + to be able to use it, but there is now a SLIP emulator called SLiRP + around (available from + ) which + allows you to use SLIP over a regular dial up shell connection. If + you plan to use SLiRP, make sure to say Y to CSLIP, below. The + NET-3-HOWTO, available from + , explains how to + configure SLIP. Note that you don't need this option if you just + want to run term (term is a program which gives you almost full + Internet connectivity if you have a regular dial up shell account on + some Internet connected Unix computer. Read + ). SLIP + support will enlarge your kernel by about 4 KB. If unsure, say N. + + To compile this driver as a module, choose M here and read + . The module will be + called slip. + +config SLIP_COMPRESSED + bool "CSLIP compressed headers" + depends on SLIP + select SLHC + ---help--- + This protocol is faster than SLIP because it uses compression on the + TCP/IP headers (not on the data itself), but it has to be supported + on both ends. Ask your access provider if you are not sure and + answer Y, just in case. You will still be able to use plain SLIP. If + you plan to use SLiRP, the SLIP emulator (available from + ) which + allows you to use SLIP over a regular dial up shell connection, you + definitely want to say Y here. The NET-3-HOWTO, available from + , explains how to configure + CSLIP. This won't enlarge your kernel. + +config SLHC + tristate + help + This option enables Van Jacobsen serial line header compression + routines. + +config SLIP_SMART + bool "Keepalive and linefill" + depends on SLIP + help + Adds additional capabilities to the SLIP driver to support the + RELCOM line fill and keepalive monitoring. Ideal on poor quality + analogue lines. + +config SLIP_MODE_SLIP6 + bool "Six bit SLIP encapsulation" + depends on SLIP + help + Just occasionally you may need to run IP over hostile serial + networks that don't pass all control characters or are only seven + bit. Saying Y here adds an extra mode you can use with SLIP: + "slip6". In this mode, SLIP will only send normal ASCII symbols over + the serial device. Naturally, this has to be supported at the other + end of the link as well. It's good enough, for example, to run IP + over the async ports of a Camtec JNT Pad. If unsure, say N. + +config NET_FC + bool "Fibre Channel driver support" + depends on SCSI && PCI + help + Fibre Channel is a high speed serial protocol mainly used to connect + large storage devices to the computer; it is compatible with and + intended to replace SCSI. + + If you intend to use Fibre Channel, you need to have a Fibre channel + adaptor card in your computer; say Y here and to the driver for your + adaptor below. You also should have said Y to "SCSI support" and + "SCSI generic support". + +config SHAPER + tristate "Traffic Shaper (OBSOLETE)" + depends on EXPERIMENTAL + ---help--- + The traffic shaper is a virtual network device that allows you to + limit the rate of outgoing data flow over some other network device. + The traffic that you want to slow down can then be routed through + these virtual devices. See + for more information. + + An alternative to this traffic shaper are traffic schedulers which + you'll get if you say Y to "QoS and/or fair queuing" in + "Networking options". + + To compile this driver as a module, choose M here: the module + will be called shaper. If unsure, say N. + +config NETCONSOLE + tristate "Network console logging support (EXPERIMENTAL)" + depends on EXPERIMENTAL + ---help--- + If you want to log kernel messages over the network, enable this. + See for details. + +endif #NETDEVICES + +config NETPOLL + def_bool NETCONSOLE + +config NETPOLL_RX + bool "Netpoll support for trapping incoming packets" + default n + depends on NETPOLL + +config NETPOLL_TRAP + bool "Netpoll traffic trapping" + default n + depends on NETPOLL + +config NET_POLL_CONTROLLER + def_bool NETPOLL + +endmenu diff -urN -x CVS linux-2.6.20/drivers/net/Makefile linux-2.6.20-AT91/drivers/net/Makefile --- linux-2.6.20/drivers/net/Makefile 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/drivers/net/Makefile 2007-07-12 14:20:46.000000000 -0500 @@ -196,7 +196,6 @@ obj-$(CONFIG_SMC911X) += smc911x.o obj-$(CONFIG_DM9000) += dm9000.o obj-$(CONFIG_FEC_8XX) += fec_8xx/ - obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_ARM) += arm/ diff -urN -x CVS linux-2.6.20/drivers/video/cx25871.h linux-2.6.20-AT91/drivers/video/cx25871.h --- linux-2.6.20/drivers/video/cx25871.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/cx25871.h 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,80 @@ +/* + * Filename: cx25871.h + * + * Description: Regisister Definitions and function prototypes for + * CX25871 NTSC/PAL encoder. + * + * Copyright(c) Cirrus Logic Corporation 2003, All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _H_CX25871 +#define _H_CX25871 + +// +// CS25871 Device Address. +// +#define CX25871_DEV_ADDRESS 0x88 + +// +// Register 0x32 +// +#define CX25871_REGx32_AUTO_CHK 0x80 +#define CX25871_REGx32_DRVS_MASK 0x60 +#define CX25871_REGx32_DRVS_SHIFT 5 +#define CX25871_REGx32_SETUP_HOLD 0x10 +#define CX25871_REGx32_INMODE_ 0x08 +#define CX25871_REGx32_DATDLY_RE 0x04 +#define CX25871_REGx32_OFFSET_RGB 0x02 +#define CX25871_REGx32_CSC_SEL 0x01 + +// +// Register 0xBA +// +#define CX25871_REGxBA_SRESET 0x80 +#define CX25871_REGxBA_CHECK_STAT 0x40 +#define CX25871_REGxBA_SLAVER 0x20 +#define CX25871_REGxBA_DACOFF 0x10 +#define CX25871_REGxBA_DACDISD 0x08 +#define CX25871_REGxBA_DACDISC 0x04 +#define CX25871_REGxBA_DACDISB 0x02 +#define CX25871_REGxBA_DACDISA 0x01 + +// +// Register 0xC4 +// +#define CX25871_REGxC4_ESTATUS_MASK 0xC0 +#define CX25871_REGxC4_ESTATUS_SHIFT 6 +#define CX25871_REGxC4_ECCF2 0x20 +#define CX25871_REGxC4_ECCF1 0x10 +#define CX25871_REGxC4_ECCGATE 0x08 +#define CX25871_REGxC4_ECBAR 0x04 +#define CX25871_REGxC4_DCHROMA 0x02 +#define CX25871_REGxC4_EN_OUT 0x01 + + +// +// Register 0xC6 +// +#define CX25871_REGxC6_EN_BLANKO 0x80 +#define CX25871_REGxC6_EN_DOT 0x40 +#define CX25871_REGxC6_FIELDI 0x20 +#define CX25871_REGxC6_VSYNCI 0x10 +#define CX25871_REGxC6_HSYNCI 0x08 +#define CX25871_REGxC6_INMODE_MASK 0x07 +#define CX25871_REGxC6_INMODE_SHIFT 0 + +#endif // _H_CX25871 diff -urN -x CVS linux-2.6.20/drivers/video/ep93xxfb.c linux-2.6.20-AT91/drivers/video/ep93xxfb.c --- linux-2.6.20/drivers/video/ep93xxfb.c 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/ep93xxfb.c 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,1790 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ep93xxfb.h" +#include "cx25871.h" +#include +#include + +extern int pls_proba; + +#define DEBUG 1 +#ifdef DEBUG +#define DPRINTK( fmt, arg... ) printk( fmt, ##arg ) +#else +#define DPRINTK( fmt, arg... ) +#endif + +#define FBDEV_NAME "ep93xxfb" + +#define ep93xxfb_outl(value, reg) \ +{ \ + outl(RASTER_SWLOCK_VALUE, RASTER_SWLOCK); \ + outl(value, reg); \ +} + +#if defined(CONFIG_FB_EP93XX_CRT) +#define DEFAULT_MODE 1 +#define DEFAULT_OUT CRT_OUT +#elif defined(CONFIG_FB_EP93XX_LCD) +#define DEFAULT_MODE 0 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_LCDWS) /* Wide screen */ +#define DEFAULT_MODE 17 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_QVGA) /* QVGA */ +#define DEFAULT_MODE 16 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_PAL) +#define DEFAULT_MODE 12 +#define DEFAULT_OUT TV_OUT +#elif defined(CONFIG_FB_EP93XX_NTSC) +#define DEFAULT_MODE 0 +#define DEFAULT_OUT TV_OUT +#else +#define DEFAULT_MODE 0 +#define DEFAULT_OUT LCD_OUT +#endif + +#if defined(CONFIG_FB_EP93XX_8BPP) +#define DEFAULT_BPP 8 +#elif defined(CONFIG_FB_EP93XX_16BPP) +#define DEFAULT_BPP 16 +#else +#define DEFAULT_BPP 16 +#endif + +static DECLARE_WAIT_QUEUE_HEAD(ep93xxfb_wait_in); + +static unsigned int pseudo_palette[256]; +static unsigned long *cursor_data = NULL; +static struct ep93xxfb_info epinfo; + +static int vout = DEFAULT_OUT; +static int vmode = DEFAULT_MODE; +static int depth = DEFAULT_BPP; + +static int ep93xxfb_setcol(struct fb_info *info, int bpp); + +struct cx25871_vmodes cxmods[CXMODES_COUNT]= +{ + + { "CX25871-NTSC", 0x10, 640, 400, 936, 525, 259, 76, 29454552 }, // 0 + { "CX25871-NTSC", 0x00, 640, 480, 784, 600, 126, 75, 28195793 }, // 1 + { "CX25871-NTSC", 0x40, 640, 480, 770, 645, 113, 100, 29769241 }, // 2 + { "CX25871-NTSC", 0x30, 720, 400, 1053, 525, 291, 76, 33136345 }, // 3 + { "CX25871-NTSC", 0x54, 720, 480, 880, 525, 140, 36, 27692310 }, // 4 + { "CX25871-NTSC", 0x02, 800, 600, 880, 735, 66, 86, 38769241 }, // 5 + { "CX25871-NTSC", 0x22, 800, 600, 1176, 750, 329, 94, 52867138 }, // 6 + { "CX25871-NTSC", 0x42, 800, 600, 1170, 805, 323, 125, 56454552 }, // 7 + { "CX25871-NTSC", 0x50, 800, 600, 1170, 770, 323, 105, 54000000 }, // 8 + { "CX25871-NTSC", 0x12, 1024, 768, 1176, 975, 133, 130,68727276 }, // 9 + { "CX25871-NTSC", 0x32, 1024, 768, 1170, 945, 127, 115, 66272724 }, // 10 + { "CX25871-NTSC", 0x52, 1024, 768, 1170, 1015, 127, 150, 71181793 },// 11 + + { "CX25871-PAL", 0x11, 640, 400, 1160, 500, 363, 64, 28999992 }, // 12 + { "CX25871-PAL", 0x01, 640, 480, 944, 625, 266, 90, 29500008 }, // 13 + { "CX25871-PAL", 0x21, 640, 480, 950, 600, 271,76 , 28500011 }, // 14 + { "CX25871-PAL", 0x41, 640, 480, 950, 650, 271, 104, 30875015 }, // 15 + { "CX25871-PAL-M", 0x56, 640, 480, 784, 600, 126, 75, 28195793 }, // 16 + { "CX25871-PAL-Nc", 0x57, 640, 480, 944, 625, 266, 90, 29500008 }, // 17 + { "CX25871-PAL", 0x31, 720, 400, 1305, 500, 411, 64, 32625000 }, // 18 + { "CX25871-PAL", 0x03, 800, 600, 960, 750, 140, 95, 36000000 }, // 19 + { "CX25871-PAL", 0x23, 800, 600, 950, 775, 131, 109, 36812508 }, // 20 + { "CX25871-PAL", 0x43, 800, 600, 950, 800, 131, 122, 37999992 }, // 21 + { "CX25871-PAL", 0x13, 1024, 768, 1400, 975, 329, 131, 68249989 }, // 22 + { "CX25871-PAL", 0x53, 1024, 768, 1410, 1000, 337, 147, 70499989 },// 23 + +}; + +static int cx25871_reboot(struct notifier_block *this, unsigned long event, void *x) +{ + switch (event) + { + case SYS_HALT: + case SYS_POWER_OFF: + case SYS_RESTART: + write_reg(0xba, 0x80); + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block cx25871_notifier = +{ + cx25871_reboot, + NULL, + 5 +}; + + +int write_reg(unsigned char ucRegAddr, unsigned char ucRegValue) +{ + unsigned long uiVal, uiDDR; + unsigned char ucData, ucIdx, ucBit; + unsigned long ulTimeout; + + uiVal = inl(GPIO_PGDR); + uiDDR = inl(GPIO_PGDDR); + uiVal |= (GPIOG_EEDAT | GPIOG_EECLK); + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiDDR |= (GPIOG_EEDAT | GPIOG_EECLK); + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + uiVal &= ~GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal &= ~GPIOG_EECLK; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + + for (ucIdx = 0; ucIdx < 3; ucIdx++) { + if (ucIdx == 0) + ucData = (unsigned char)CX25871_DEV_ADDRESS; + else if (ucIdx == 1) + ucData = ucRegAddr; + else + ucData = ucRegValue; + + for (ucBit = 0; ucBit < 8; ucBit++) { + if (ucData & 0x80) + uiVal |= GPIOG_EEDAT; + else + uiVal &= ~GPIOG_EEDAT; + + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + outl( (uiVal | GPIOG_EECLK), GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + ucData <<= 1; + } + + uiDDR &= ~GPIOG_EEDAT; + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + outl( (uiVal | GPIOG_EECLK), GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + ulTimeout = 0; + while ( inl(GPIO_PGDR) & GPIOG_EEDAT ) { + udelay( EE_DELAY_USEC ); + ulTimeout++; + if (ulTimeout > EE_READ_TIMEOUT ) + return 1; + } + + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiDDR |= GPIOG_EEDAT; + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + } + + uiVal &= ~GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal |= GPIOG_EECLK; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal |= GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + return 0; +} + +void cx25871_on( unsigned char value ) +{ + write_reg(0x30,0x00); + write_reg(0xBA, 0x20 ); +} + +void cx25871_off( unsigned char value ) +{ + write_reg(0xBA, 0x30); + write_reg(0xC4, 0x00); + write_reg(0x30, 0x02); +} + +void cx25871_config( unsigned char value ) +{ + write_reg(0xBA, CX25871_REGxBA_SRESET); + mdelay(1); + write_reg(0xB8, value); + write_reg(0xBA, CX25871_REGxBA_SLAVER | CX25871_REGxBA_DACOFF); + write_reg(0xC6,(CX25871_REGxC6_INMODE_MASK & 0x3)); + write_reg(0xC4, CX25871_REGxC4_EN_OUT); + write_reg(0xBA, CX25871_REGxBA_SLAVER ); +} + +static struct ep93xxfb_videomodes ep93xxfb_vmods[] = { + { // 0 + "Philips-LB064V02-640x480x60", + 640, 24, 96, 40, 480, 10, 2, 33, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 1 + "CRT-640x480-60", + 640, 24, 96, 40, 480, 11, 2, 32, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 2 + "CRT-640x480-72", + 640, 40, 40, 144, 480, 8, 3, 30, 72, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 3 + "CRT-640x480-75", + 640, 16, 76, 120, 480, 1, 3, 16, 75, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 4 + "CRT-640x480-85", + 640, 56, 56, 80, 480, 1, 3, 25, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 5 + "CTR-640x480-100", + 640, 32, 96, 96, 480, 8, 6, 36, 100, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 6 + "CRT-800x600-56", + 800, 24, 72, 128, 600, 1, 2, 22, 56, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 7 + "CRT-800x600-60", + 800, 40, 128, 88, 600, 1, 4, 23, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 8 + "CRT-800x600-72", + 800, 56, 120, 64, 600, 37, 6, 23, 72, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 9 + "CRT-800x600-85", + 800, 64, 64, 160, 600, 16, 5, 36, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 10 + "CRT-800x600-100", + 800, 64, 64, 160, 600, 4, 6, 30, 100, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 11 + "CRT-1024x768-60", + 1024, 8, 144, 168, 768, 3, 6, 29, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 12 + "CRT-1024x768-70", + 1024, 24, 136, 144, 768, 3, 6, 29, 70, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 13 + "CRT-1024x768-75", + 1024, 16, 96, 176, 768, 1, 3, 28, 75, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 14 + "CRT-1024x768-85", + 1024, 48, 96, 208, 768, 1, 3, 36, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 15 + "CRT-1280x720-60", + 1280, 48, 112, 248, 720, 1, 3, 38, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + /* Add support for the LB040Q02 QVGA and the Primeview PM070WX2 800x480 LCD */ + /* TAS */ + { // 16 + "LB040Q02-QVGA-320x240", + 320, 25, 30, 25, 240, 6, 7, 10, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 17 + "PM070WX2-800x480", + 800, 24, 96, 40, 480, 10, 2, 33, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + } +}; + +static void philips_lb064v02_on(unsigned char value) +{ + DPRINTK("philips_lb064v02_on \n"); + DPRINTK("GPIO pin is set to %d\n", CONFIG_FB_EP93XX_GPIO); + /* The GPIO line that turns on power to the LCD differs + * depending on the board. This has been moved to the + * Kconfig as an option. Currently, the EDB9315A board + * should use 2, the EMAC Thermatron board uses 1. + */ + /*outl(inl(GPIO_PADDR) | 2, GPIO_PADDR); */ + /*outl(inl(GPIO_PADDR) | 1, GPIO_PADDR); */ + outl(inl(GPIO_PADDR) | CONFIG_FB_EP93XX_GPIO, GPIO_PADDR); + /*outl(inl(GPIO_PADR) | 2, GPIO_PADR); */ + /*outl(inl(GPIO_PADR) | 1, GPIO_PADR); */ + outl(inl(GPIO_PADDR) | CONFIG_FB_EP93XX_GPIO, GPIO_PADDR); +} + +static void philips_lb064v02_off(unsigned char value) +{ + DPRINTK("philips_lb064v02_off \n"); + outl(inl(GPIO_PADR) & ~2, GPIO_PADR); +} + +static irqreturn_t ep93xxfb_irq_handler(int i, void *blah, struct pt_regs *regs) +{ + outl(0x00000000, BLOCKCTRL); + wake_up(&ep93xxfb_wait_in); + return IRQ_HANDLED; +} + +static void ep93xxfb_wait(void) +{ + DECLARE_WAITQUEUE(wait, current); + add_wait_queue(&ep93xxfb_wait_in, &wait); + set_current_state(TASK_UNINTERRUPTIBLE); + + while (inl(BLOCKCTRL) & 0x00000001){ + if((pls_proba==1)&&(!in_atomic())) + schedule(); + } + + remove_wait_queue(&ep93xxfb_wait_in, &wait); + set_current_state(TASK_RUNNING); + +} + +void ep93xxfb_fillrect(struct fb_info *p, const struct fb_fillrect *fill) +{ + unsigned long blkdestwidth,tmp; + + if (!fill->width || !fill->height || + (fill->dx >= p->var.xres) || + (fill->dy >= p->var.yres) || + ((fill->dx + fill->width - 1) >= p->var.xres) || + ((fill->dy + fill->height - 1) >= p->var.yres)) + return; + + tmp = (( fill->dx + fill->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (fill->dx * epinfo.bpp) / 32; + + outl(fill->color, BLOCKMASK); + outl( ((fill->dx * epinfo.bpp) & 0x1F) | + ((((fill->dx + fill->width - 1) * epinfo.bpp ) & 0x1F) << 16), + DESTPIXELSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH); + outl( blkdestwidth, BLKDESTWIDTH ); + outl(fill->height - 1, BLKDESTHEIGHT); + outl((epinfo.fb_phys + (fill->dy * epinfo.xres * epinfo.bpp ) / 8 + + (fill->dx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( epinfo.pixformat | 0x0000000B, BLOCKCTRL); + ep93xxfb_wait(); + +} + +void ep93xxfb_copyarea(struct fb_info *p, const struct fb_copyarea *area) +{ + unsigned long startsx,stopsx,startdx,stopdx,startsy,startdy; + unsigned long blksrcwidth,blkdestwidth,tmp; + unsigned long val = 0; + + if( !area->width || !area->width || + (area->sx >= p->var.xres) || (area->sy >= p->var.yres) || + (area->dx >= p->var.xres) || (area->dy >= p->var.yres) || + ((area->dx + area->width - 1) >= p->var.xres) || + ((area->dy + area->height - 1) >= p->var.yres)) + return; + + if(area->sx == area->dx && area->sy == area->dy) + return; + + if ((area->dy == area->sy) && (area->dx > area->sx) && + (area->dx < (area->sx + area->width - 1))) { + startdx = area->dx + area->width - 1; + stopdx = area->dx; + startsx = area->sx + area->width - 1; + stopsx = area->sx; + val |= 0x000000A0; + } + else { + startdx = area->dx; + stopdx = area->dx + area->width - 1; + startsx = area->sx; + stopsx = area->sx + area->width - 1; + } + + if (area->dy <= area->sy) { + startdy = area->dy; + startsy = area->sy; + } + else { + startdy = area->dy + area->height -1; + startsy = area->sy + area->height -1; + val |= 0x00000140; + } + + tmp = (( area->sx + area->width ) * epinfo.bpp ); + blksrcwidth = tmp / 32; + if(blksrcwidth > 0 && (tmp % 32 == 0)) + blksrcwidth--; + blksrcwidth = blksrcwidth - (area->sx * epinfo.bpp) / 32; + tmp = (( area->dx + area->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (area->dx * epinfo.bpp) / 32; + + outl( 0x00000000 , BLOCKCTRL); + + /*** src ***/ + outl((((startsx * epinfo.bpp) & 0x1F) | + (((stopsx * epinfo.bpp ) & 0x1F) << 16)) + , SRCPIXELSTRT); + outl((epinfo.fb_phys + (startsy * epinfo.xres * epinfo.bpp ) / 8 + + (startsx * epinfo.bpp ) / 8 ) + , BLKSRCSTRT); + outl(((epinfo.xres * epinfo.bpp) / 32), SRCLINELENGTH); + outl( blksrcwidth, BLKSRCWIDTH ); + + /*** dest ***/ + outl((((startdx * epinfo.bpp) & 0x1F) | + (((stopdx * epinfo.bpp ) & 0x1F) << 16)) + , DESTPIXELSTRT); + outl((epinfo.fb_phys + (startdy * epinfo.xres * epinfo.bpp ) / 8 + + (startdx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH); + outl( blkdestwidth, BLKDESTWIDTH); + outl( area->height - 1 , BLKDESTHEIGHT); + outl( epinfo.pixformat | val | 0x00000003, BLOCKCTRL); + ep93xxfb_wait(); +} + +void ep93xxfb_imageblit(struct fb_info *p, const struct fb_image *image) +{ +// unsigned long blkdestwidth,tmp; +// void * pucBlitBuf; + cfb_imageblit( p , image ); + return; +/* + if ((image->dx >= p->var.xres) || + (image->dy >= p->var.yres) || + ((image->dx + image->width - 1) >= p->var.xres) || + ((image->dy + image->height - 1) >= p->var.yres)) + return; + if (epinfo.bpp != image->depth ) + return; + + tmp = (( image->dx + image->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (image->dx * epinfo.bpp) / 32; + + pucBlitBuf = kmalloc(1024*8,GFP_KERNEL); + copy_from_user(pucBlitBuf, image->data, 5000); + + outl( 0x00000000 , BLOCKCTRL); + + outl( 0x00000000, SRCPIXELSTRT); + outl( virt_to_phys(pucBlitBuf), BLKSRCSTRT); + outl( (image->width * epinfo.bpp) / 32 , SRCLINELENGTH); + outl(((image->width - 1) * epinfo.bpp) / 32, BLKSRCWIDTH ); + + outl(((image->dx * epinfo.bpp) & 0x1F) | + ((((image->dx + image->width - 1) * epinfo.bpp ) & 0x1F) << 16) + , DESTPIXELSTRT); + outl((epinfo.fb_phys + (image->dy * epinfo.xres * epinfo.bpp ) / 8 + + (image->dx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH ); + outl( blkdestwidth, BLKDESTWIDTH ); + outl( image->height - 1 , BLKDESTHEIGHT); + outl(image->fg_color, BLOCKMASK); + outl(image->bg_color, BACKGROUND); + outl( epinfo.pixformat | 0x00000003, BLOCKCTRL ); + ep93xxfb_wait(); +*/ +} + + +static unsigned long isqrt(unsigned long a) +{ + unsigned long rem = 0; + unsigned long root = 0; + int i; + + for (i = 0; i < 16; i++) { + root <<= 1; + rem = ((rem << 2) + (a >> 30)); + a <<= 2; + root++; + if (root <= rem) { + rem -= root; + root++; + } + else + root--; + } + return root >> 1; +} + +int ep93xxfb_line(struct fb_info *info, struct ep93xx_line *line) +{ + unsigned long value = 0; + long x, y, dx, dy, count, xinc, yinc, xval, yval, incr; + + if ((line->x1 > info->var.xres) || + (line->x2 > info->var.xres) || + (line->y1 > info->var.yres) || + (line->y2 > info->var.yres)) + return -EFAULT; + x = line->x1; + y = line->y1; + dx = line->x2 - line->x1; + dy = line->y2 - line->y1; + + if ( !dx || !dy ) + return -EFAULT; + + if ( dx < 0 && dy < 0 ) { + x = line->x2; + y = line->y2; + dx *= -1; + dy *= -1; + } + else if ( dx < 0 && dy > 0 ){ + dx *= -1; + value = 0x000000A0; + } + else if( dy < 0 && dx > 0 ){ + dy *= -1; + value = 0x00000140; + } + + if (line->flags & LINE_PRECISE) { + count = isqrt(((dy * dy) + (dx * dx)) * 4096); + xinc = (4095 * 64 * dx) / count; + yinc = (4095 * 64 * dy) / count; + xval = 2048; + yval = 2048; + count = 0; + while (dx || dy) { + incr = 0; + xval -= xinc; + if (xval <= 0) { + xval += 4096; + dx--; + incr = 1; + } + yval -= yinc; + if (yval <= 0) { + yval += 4096; + dy--; + incr = 1; + } + count += incr; + } + } + else { + if ( dx == dy ) { + xinc = 4095; + yinc = 4095; + count = dx; + + } + else if ( dx < dy ) { + xinc = ( dx * 4095 ) / dy; + yinc = 4095; + count = dy; + + } + else { + xinc = 4095; + yinc = ( dy * 4095 ) / dx; + count = dx; + } + } + + outl(0x08000800, LINEINIT); + if (line->flags & LINE_PATTERN) + outl(line->pattern, LINEPATTRN); + else + outl(0x000fffff, LINEPATTRN); + outl(epinfo.fb_phys + ((y * epinfo.xres * epinfo.bpp) / 8) + + ((x * epinfo.bpp ) / 8 ), BLKDSTSTRT); + + outl(((x * epinfo.bpp) & 0x1F) | + ((((x + dx - 1) * epinfo.bpp) & 0x1F ) << 16), + DESTPIXELSTRT); + outl((epinfo.xres * epinfo.bpp) / 32, DESTLINELENGTH); + outl(line->fgcolor, BLOCKMASK); + outl(line->bgcolor, BACKGROUND); + outl((yinc << 16) | xinc, LINEINC); + outl( count & 0xFFF, BLKDESTWIDTH); + outl( 0 , BLKDESTHEIGHT); + value |= (line->flags & LINE_BACKGROUND) ? 0x00004000 : 0; + outl(epinfo.pixformat | value | 0x00000013, BLOCKCTRL); + ep93xxfb_wait(); + return 0; +} + + +int ep93xxfb_cursor(struct fb_info *info, struct ep93xx_cursor *cursor) +{ + unsigned long x,y,save,copy_ret; + copy_ret = 0; + + if (cursor->width > 64 || cursor->height > 64) + return -ENXIO; + + if (cursor->flags & CURSOR_OFF) + outl(inl(CURSORXYLOC) & ~0x00008000, CURSORXYLOC); + + if (cursor->flags & CURSOR_SETSHAPE) { + copy_ret = copy_from_user(cursor_data, cursor->data, + cursor->width * cursor->height / 4); + save = inl(CURSORXYLOC); + outl(save & ~0x00008000, CURSORXYLOC); + + outl(virt_to_phys(cursor_data), CURSOR_ADR_START); + outl(virt_to_phys(cursor_data), CURSOR_ADR_RESET); + outl(((cursor->width - 1) & 0x30) << 4 | ((cursor->height - 1) << 2) | + ((cursor->width - 1) >> 4), CURSORSIZE); + outl(save, CURSORXYLOC); + + } + + if (cursor->flags & CURSOR_SETCOLOR) { + outl(cursor->color1, CURSORCOLOR1); + outl(cursor->color2, CURSORCOLOR2); + outl(cursor->blinkcolor1, CURSORBLINK1); + outl(cursor->blinkcolor2, CURSORBLINK2); + } + + if (cursor->flags & CURSOR_BLINK) { + if (cursor->blinkrate) + outl(0x00000100 | cursor->blinkrate, CURSORBLINK); + else + outl(0x0000000FF, CURSORBLINK); + } + + if (cursor->flags & CURSOR_MOVE) { + x = (inl(HACTIVESTRTSTOP) & 0x000007ff) - cursor->dx - 2; + y = (inl(VACTIVESTRTSTOP) & 0x000007ff) - cursor->dy; + outl((inl(CURSORXYLOC) & 0x8000) | (y << 16) | x, CURSORXYLOC); + } + + if(cursor->flags & CURSOR_ON) + outl(inl(CURSORXYLOC) | 0x00008000, CURSORXYLOC); + if (copy_ret != 0) + return -1; + else + return 0; +} + +static inline void +ep93xxfb_palette_write(u_int regno, u_int red, u_int green, + u_int blue, u_int trans) +{ + unsigned int cont, i, pal; + DPRINTK("ep93xxfb_palette_write - enter\n"); + pal = ((red & 0xFF00) << 8) | (green & 0xFF00) | ((blue & 0xFF00) >> 8); + pseudo_palette[regno] = pal; + outl( pal, ( COLOR_LUT + ( regno << 2 ))); + cont = inl( LUTCONT ); + + if (( cont & LUTCONT_STAT && cont & LUTCONT_RAM1 ) || + ( !( cont & LUTCONT_STAT ) && !( cont&LUTCONT_RAM1 ))) { + for ( i = 0; i < 256; i++ ) { + outl( pseudo_palette[i], ( COLOR_LUT + ( i << 2 )) ); + } + outl( cont ^ LUTCONT_RAM1, LUTCONT ); + } +} + +int ep93xxfb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + +#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) + + switch ( info->fix.visual ) + { + case FB_VISUAL_PSEUDOCOLOR: + ep93xxfb_palette_write(regno, red, green, blue, transp); + break; + case FB_VISUAL_TRUECOLOR: + if (regno >= 16) + return 1; + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + ((u32 *)(info->pseudo_palette))[regno] = + (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + return 0; +} + +static int ep93xx_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + DPRINTK("ep93xx_pan_display - enter\n"); + + if (var->yoffset < 0 + || var->yoffset + var->yres > info->var.yres_virtual + || var->xoffset) + return -EINVAL; + + outl(epinfo.fb_phys + info->fix.line_length * var->yoffset + , VIDSCRNPAGE); + + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + + DPRINTK("ep93xx_pan_display - exit\n"); + return 0; +} + + +static int +ep93xxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct fb_var_screeninfo tmp_var; + unsigned long pclk; + DPRINTK("ep93xxfb_check_var - enter\n"); + + memcpy (&tmp_var, var, sizeof (tmp_var)); + + if( (tmp_var.vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED ) { + DPRINTK(" ep93xxfb_check_var - unsupported video mode\n"); + return -EINVAL; + } + + if( ((tmp_var.xres * tmp_var.yres * tmp_var.bits_per_pixel) / 8) > + MAX_FBMEM_SIZE ) { + DPRINTK(" ep93xxfb_check_var - memory error \n"); + return -ENOMEM; + } + + if( ((tmp_var.xres_virtual * tmp_var.yres_virtual * tmp_var.bits_per_pixel) / 8) > + MAX_FBMEM_SIZE ) { + DPRINTK(" ep93xxfb_check_var - memory error \n"); + return -ENOMEM; + } + + pclk = 1000 * (1000000000 / tmp_var.pixclock); + + if( pclk > ep93xx_get_max_video_clk() ) { + DPRINTK(" ep93xxfb_check_var - pixel clock error %lu\n",pclk); + return -EINVAL; + } + + if (var->xres_virtual != var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if (var->xoffset < 0) + var->xoffset = 0; + if (var->yoffset < 0) + var->yoffset = 0; + + switch (tmp_var.bits_per_pixel) { + case 8: + break; + case 16: + break; + case 24: + break; + case 32: + break; + default: + return -EINVAL; + } + + DPRINTK("ep93xxfb_check_var - exit\n"); + return 0; +} + + +static int ep93xxfb_set_par(struct fb_info *info) +{ + struct fb_var_screeninfo tmp_var; + unsigned long attribs; + + DPRINTK("ep93xxfb_set_par - enter\n"); + + if( ep93xxfb_check_var(&info->var,info) < 0 ) + return -EINVAL; + + if( !ep93xxfb_setcol(info,info->var.bits_per_pixel) ) + return -EINVAL; + + + info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8; + + ep93xxfb_blank( 1 , info ); + + memcpy(&tmp_var,&info->var,sizeof(tmp_var)); + + epinfo.xres = tmp_var.xres; + epinfo.xsync = tmp_var.hsync_len; + epinfo.xfp = tmp_var.right_margin; + epinfo.xbp = tmp_var.left_margin; + epinfo.xtotal = epinfo.xres + epinfo.xsync + + epinfo.xfp + epinfo.xbp; + + epinfo.yres = tmp_var.yres; + epinfo.ysync = tmp_var.vsync_len; + epinfo.yfp = tmp_var.lower_margin; + epinfo.ybp = tmp_var.upper_margin; + epinfo.ytotal = epinfo.yres + epinfo.ysync + + epinfo.yfp + epinfo.ybp; + + epinfo.pixclock = tmp_var.pixclock ; + epinfo.refresh = 1000 * (1000000000 / tmp_var.pixclock) ; + + if( epinfo.refresh > ep93xx_get_max_video_clk()) + epinfo.refresh = ep93xx_get_max_video_clk(); + epinfo.bpp = tmp_var.bits_per_pixel; + + ep93xxfb_setclk(); + ep93xxfb_timing_signal_generation(); + + // set video memory parameters + outl(epinfo.fb_phys, VIDSCRNPAGE); + outl(epinfo.yres , SCRNLINES); + outl(((epinfo.xres * epinfo.bpp) / 32) - 1, LINELENGTH); + outl((epinfo.xres * epinfo.bpp) / 32, VLINESTEP); + + // set pixel mode + ep93xxfb_pixelmod(epinfo.bpp); + + attribs = 0; +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + /* We can't set the clock here, we don't know anything + * about it yet. This causes the clock to always be + * rising edge, which distorts the image. It is set if + * needed in the ep93xx_config function. -- TAS */ + //attribs |= VIDEOATTRIBS_INVCLK; + if( tmp_var.sync & FB_SYNC_HOR_HIGH_ACT ) + attribs |= VIDEOATTRIBS_HSPOL; + if( tmp_var.sync & FB_SYNC_VERT_HIGH_ACT ) + attribs |= VIDEOATTRIBS_VCPOL; + + ep93xxfb_outl(attribs, VIDEOATTRIBS); + ep93xxfb_blank( 0 , info ); + + DPRINTK("ep93xxfb_set_par - exit\n"); + + return 0; +} + + +static int ep93xxfb_blank(int blank_mode,struct fb_info *info) +{ + unsigned long attribs; + DPRINTK("ep93xxfb_blank - enter\n"); + attribs = inl(VIDEOATTRIBS); + +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + if (blank_mode) { + if (epinfo.off) + (epinfo.off)( 0 ); + + ep93xxfb_outl(attribs & ~(VIDEOATTRIBS_DATAEN | + VIDEOATTRIBS_SYNCEN | VIDEOATTRIBS_PCLKEN | + VIDEOATTRIBS_EN), VIDEOATTRIBS); + } + else { + if (epinfo.clk_src == CLK_INTERNAL) + attribs |= VIDEOATTRIBS_PCLKEN; + else + attribs &= ~VIDEOATTRIBS_PCLKEN; + + ep93xxfb_outl(attribs | VIDEOATTRIBS_DATAEN | + VIDEOATTRIBS_SYNCEN | VIDEOATTRIBS_EN, + VIDEOATTRIBS); + + if (epinfo.configure) + (epinfo.configure)( epinfo.automods ); + if (epinfo.on) + (epinfo.on)( 0 ); + } + return 0; +} + +static int ep93xxfb_mmap(struct fb_info *info,struct vm_area_struct *vma) +{ + unsigned long off, start, len; + + DPRINTK("ep93xxfb_mmap - enter\n"); + + off = vma->vm_pgoff << PAGE_SHIFT; + start = info->fix.smem_start; + len = PAGE_ALIGN(start & ~PAGE_MASK) + info->fix.smem_len; + start &= PAGE_MASK; + if ((vma->vm_end - vma->vm_start + off) > len) + return -EINVAL; + + off += start; + vma->vm_pgoff = off >> PAGE_SHIFT; + + vma->vm_flags |= VM_IO; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + DPRINTK("ep93xxfb_mmap error\n"); + return -EAGAIN; + } + + DPRINTK("ep93xxfb_mmap - exit\n"); + return 0; +} + +static unsigned long ep93xx_get_pll_frequency(unsigned long pll) +{ + unsigned long fb1, fb2, ipd, ps, freq; + + if (pll == 1) + pll = inl(SYSCON_CLKSET1); + else if (pll == 2) + pll = inl(SYSCON_CLKSET2); + else + return 0; + + ps = (pll & SYSCON_CLKSET1_PLL1_PS_MASK) >> SYSCON_CLKSET1_PLL1_PS_SHIFT; + fb1 = ((pll & SYSCON_CLKSET1_PLL1_X1FBD1_MASK) >> SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT); + fb2 = ((pll & SYSCON_CLKSET1_PLL1_X2FBD2_MASK) >> SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT); + ipd = ((pll & SYSCON_CLKSET1_PLL1_X2IPD_MASK) >> SYSCON_CLKSET1_PLL1_X2IPD_SHIFT); + + freq = (((0x00e10000 * (fb1+1)) / (ipd+1)) * (fb2+1)) >> ps; + return freq; +} + +static int ep93xx_get_max_video_clk() +{ + unsigned long f,freq = 0; + + freq = 14745600 / 4; + f = ep93xx_get_pll_frequency(1) / 4; + if ( f > freq ) + freq = f; + f = ep93xx_get_pll_frequency(2) / 4; + if ( f > freq ) + freq = f; + + return freq; +} + +static int ep93xx_set_video_div(unsigned long freq) +{ + unsigned long pdiv = 0, div = 0, psel = 0, esel = 0; + unsigned long err, f, i, j, k; + + err = -1; + + for (i = 0; i < 3; i++) { + if (i == 0) + f = 14745600 * 2; + else if (i == 1) + f = ep93xx_get_pll_frequency(1) * 2; + else + f = ep93xx_get_pll_frequency(2) * 2; + + for (j = 4; j <= 6; j++) { + k = f / (freq * j); + if (k < 2) + continue; + + if (abs(((f / (j * k))) - freq ) < err ) { + pdiv = j - 3; + div = k; + psel = (i == 2) ? 1 : 0; + esel = (i == 0) ? 0 : 1; + err = (f / (j * k)) - freq; + } + } + } + + if (err == -1) + return -1; + + outl(0xaa, SYSCON_SWLOCK); + outl(SYSCON_VIDDIV_VENA | (esel ? SYSCON_VIDDIV_ESEL : 0) | + (psel ? SYSCON_VIDDIV_PSEL : 0) | + (pdiv << SYSCON_VIDDIV_PDIV_SHIFT) | + (div << SYSCON_VIDDIV_VDIV_SHIFT), SYSCON_VIDDIV); + + return freq + err; +} + +static void ep93xxfb_pixelmod(int bpp) +{ + unsigned long tmpdata = 0; + + DPRINTK("ep93xxfb_pixelmod %dbpp -enter\n",bpp); + switch(bpp) { + case 8: + tmpdata = PIXELMODE_P_8BPP | + PIXELMODE_S_1PPCMAPPED | + PIXELMODE_C_LUT; + epinfo.pixformat = PIXEL_FORMAT_8; + break; + case 16: + tmpdata = PIXELMODE_P_16BPP | + PIXELMODE_S_1PPCMAPPED | + PIXELMODE_C_565; + epinfo.pixformat = PIXEL_FORMAT_16; + break; + case 24: + tmpdata = PIXELMODE_P_24BPP | + PIXELMODE_S_1PPC | + PIXELMODE_C_888; + epinfo.pixformat = PIXEL_FORMAT_24; + break; + case 32: + tmpdata = PIXELMODE_P_32BPP | + PIXELMODE_S_1PPC | + PIXELMODE_C_888; + epinfo.pixformat = PIXEL_FORMAT_32; + break; + default: + break; + } + outl(tmpdata,PIXELMODE); +} + +static void ep93xxfb_timing_signal_generation(void) +{ + unsigned long vlinestotal,vsyncstart,vsyncstop, + vactivestart,vactivestop, + vblankstart,vblankstop, + vclkstart,vclkstop; + + unsigned long hclkstotal,hsyncstart,hsyncstop, + hactivestart,hactivestop, + hblankstart,hblankstop, + hclkstart,hclkstop; + + DPRINTK("ep93xxfb_timing_signal_generation - enter\n"); + + vlinestotal = epinfo.ytotal - 1; + vsyncstart = vlinestotal; + vsyncstop = vlinestotal - epinfo.ysync; + vblankstart = vlinestotal - epinfo.ysync - epinfo.ybp; + vblankstop = epinfo.yfp - 1; + vactivestart = vblankstart; + vactivestop = vblankstop; + vclkstart = vlinestotal; + vclkstop = vlinestotal + 1; + + hclkstotal = epinfo.xtotal - 1; + hsyncstart = hclkstotal; + hsyncstop = hclkstotal - epinfo.xsync; + hblankstart = hclkstotal - epinfo.xsync - epinfo.xbp; + hblankstop = epinfo.xfp - 1; + hactivestart = hblankstart; + hactivestop = hblankstop; + hclkstart = hclkstotal ; + hclkstop = hclkstotal ; + + ep93xxfb_outl(0, VIDEOATTRIBS); + + ep93xxfb_outl( vlinestotal , VLINESTOTAL ); + ep93xxfb_outl( vsyncstart + (vsyncstop << 16), VSYNCSTRTSTOP ); + ep93xxfb_outl( vactivestart + (vactivestop << 16), VACTIVESTRTSTOP ); + ep93xxfb_outl( vblankstart + (vblankstop << 16), VBLANKSTRTSTOP ); + ep93xxfb_outl( vclkstart + (vclkstop << 16), VCLKSTRTSTOP ); + + ep93xxfb_outl( hclkstotal , HCLKSTOTAL ); + ep93xxfb_outl( hsyncstart + (hsyncstop << 16), HSYNCSTRTSTOP ); + ep93xxfb_outl( hactivestart + (hactivestop << 16) , HACTIVESTRTSTOP ); + ep93xxfb_outl( hblankstart + (hblankstop << 16) , HBLANKSTRTSTOP ); + ep93xxfb_outl( hclkstart + (hclkstop << 16) , HCLKSTRTSTOP ); + + ep93xxfb_outl(0, LINECARRY); + +} + +static int ep93xxfb_setcol(struct fb_info *info, int bpp) +{ + + DPRINTK("ep93xxfb_setcol %dbpp\n",bpp); + switch(bpp) { + case 8: + info->var.bits_per_pixel = 8; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + break; + case 16: + info->var.bits_per_pixel = 16; + info->var.red.offset = 11; + info->var.red.length = 5; + info->var.green.offset = 5; + info->var.green.length = 6; + info->var.blue.offset = 0; + info->var.blue.length = 5; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + case 24: + info->var.bits_per_pixel = 24; + info->var.red.length = 8; + info->var.blue.length = 8; + info->var.green.length = 8; + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + case 32: + info->var.bits_per_pixel = 32; + info->var.red.length = 8; + info->var.blue.length = 8; + info->var.green.length = 8; + info->var.transp.length = 0; + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.transp.offset = 0; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + default: + return 0; + } + return 1; +} + +static int ep93xxfb_setclk() +{ + unsigned long calc_clk,act_clk; + + if ( epinfo.clk_src == CLK_INTERNAL ) { + outl(0xaa, SYSCON_SWLOCK); + outl(inl(SYSCON_DEVCFG) & ~SYSCON_DEVCFG_EXVC, SYSCON_DEVCFG); + calc_clk = epinfo.refresh; + act_clk = ep93xx_set_video_div( calc_clk ); + if ( act_clk == -1 ) + return -ENODEV; + + epinfo.refresh = act_clk; + epinfo.pixclock = 1000000000 / (act_clk / 1000); + } + else { + outl(0xaa, SYSCON_SWLOCK); + outl(0, SYSCON_VIDDIV); + outl(0xaa, SYSCON_SWLOCK); + outl(inl(SYSCON_DEVCFG) | SYSCON_DEVCFG_EXVC, SYSCON_DEVCFG); + } + + return 0; +} + + +static void ep93xxfb_get_par(struct fb_info *info) +{ + + DPRINTK("ep93xxfb_get_par - enter\n"); + epinfo.configure = NULL; + epinfo.on = NULL; + epinfo.off = NULL; + + switch( vout ) { + case LCD_OUT: + epinfo.on = philips_lb064v02_on; + epinfo.off = philips_lb064v02_off; + + case CRT_OUT: + epinfo.xres = ep93xxfb_vmods[vmode].hres; + epinfo.xsync = ep93xxfb_vmods[vmode].hsync; + epinfo.xfp = ep93xxfb_vmods[vmode].hfp; + epinfo.xbp = ep93xxfb_vmods[vmode].hbp; + epinfo.xtotal = epinfo.xres + epinfo.xsync + + epinfo.xfp + epinfo.xbp; + + epinfo.yres = ep93xxfb_vmods[vmode].vres; + epinfo.ysync = ep93xxfb_vmods[vmode].vsync; + epinfo.yfp = ep93xxfb_vmods[vmode].vfp; + epinfo.ybp = ep93xxfb_vmods[vmode].vbp; + epinfo.ytotal = epinfo.yres + epinfo.ysync + + epinfo.yfp + epinfo.ybp; + + epinfo.refresh = ep93xxfb_vmods[vmode].refresh; + epinfo.refresh = epinfo.xtotal * epinfo.ytotal * epinfo.refresh; + epinfo.pixclock = 1000000000 / ( epinfo.refresh / 1000); + epinfo.bpp = depth; + + epinfo.clk_src = ep93xxfb_vmods[vmode].clk_src; + epinfo.clk_edge = ep93xxfb_vmods[vmode].clk_edge; + epinfo.pol_blank = ep93xxfb_vmods[vmode].pol_blank; + epinfo.pol_xsync = ep93xxfb_vmods[vmode].pol_hsync; + epinfo.pol_ysync = ep93xxfb_vmods[vmode].pol_vsync; + break; + + case TV_OUT: + epinfo.xres = cxmods[vmode].hres; + epinfo.xsync = 4; + epinfo.xbp = cxmods[vmode].hblank; + epinfo.xfp = cxmods[vmode].hclktotal - epinfo.xbp - + cxmods[vmode].hres - 4; + epinfo.xtotal = cxmods[vmode].hclktotal; + + epinfo.yres = cxmods[vmode].vres; + epinfo.ysync = 2; + epinfo.ybp = cxmods[vmode].vblank; + epinfo.yfp = cxmods[vmode].vclktotal - epinfo.ybp - + cxmods[vmode].vres - 2; + epinfo.ytotal = cxmods[vmode].vclktotal; + epinfo.bpp = depth; + + epinfo.clk_src = CLK_EXTERNAL; + epinfo.automods = cxmods[vmode].automode; + epinfo.clk_edge = EDGE_FALLING; + epinfo.pol_blank = POL_LOW; + epinfo.pol_xsync = POL_LOW, + epinfo.pol_ysync = POL_LOW; + + epinfo.refresh = cxmods[vmode].clkfrequency ; + epinfo.pixclock = 1000000000 / ( epinfo.refresh / 1000); + + epinfo.configure = cx25871_config; + epinfo.on = cx25871_on; + epinfo.off = cx25871_off; + break; + } +} + +static int ep93xxfb_alloc_videomem(void) +{ + unsigned long adr,size,pgsize; + int order; + + DPRINTK("ep93xxfb_alloc_videomem - enter \n"); + + epinfo.fb_log = NULL; + epinfo.fb_size = PAGE_ALIGN( MAX_FBMEM_SIZE ); + order = get_order( epinfo.fb_size ); + order = ( ( (1 << order)*PAGE_SIZE ) < epinfo.fb_size ) ? (order+1) : order; + epinfo.fb_log = (void*) __get_free_pages( GFP_KERNEL, order ); + + if (epinfo.fb_log) { + epinfo.fb_phys = __virt_to_phys((int) epinfo.fb_log ); +/** + adr = (unsigned long)epinfo.fb_log; + size = epinfo.fb_size; + pgsize = 1 << order; + do { + adr += pgsize; + SetPageReserved(virt_to_page(adr)); + } while(size -= pgsize); +**/ + } + else + return -ENOMEM; + memset(epinfo.fb_log,0x00,epinfo.fb_size); + DPRINTK(" fb_log_addres = 0x%x\n",epinfo.fb_log); + DPRINTK(" fb_phys_address = 0x%x\n",epinfo.fb_phys); + DPRINTK(" fb_size = %lu\n",epinfo.fb_size); + DPRINTK(" fb_page_order = %d\n",order); + + DPRINTK("ep93xxfb_alloc_videomem - exit \n"); + return 0; +} + +static void ep93xxfb_release_videomem(void) +{ + unsigned long adr,size,psize; + int order; + + DPRINTK("ep93xxfb_release_videomem - enter \n"); + if (epinfo.fb_log) { + order = get_order(epinfo.fb_size); + adr = (unsigned long)epinfo.fb_log; + size = epinfo.fb_size; + psize = 1 << order ; + do { + adr += psize; + ClearPageReserved(virt_to_page(adr)); + } while(size -= psize); + free_pages((unsigned long)epinfo.fb_log, order ); + } + DPRINTK("ep93xxfb_release_videomem - exit \n"); +} + +static void ep93xxfb_setinfo(struct fb_info *info) +{ + + info->pseudo_palette = pseudo_palette; + info->var.xres = epinfo.xres; + info->var.yres = epinfo.yres; + info->var.xres_virtual = epinfo.xres; + info->var.yres_virtual = epinfo.yres; + + ep93xxfb_setcol( info, depth ); + + info->var.activate = FB_ACTIVATE_NOW; + info->var.left_margin = epinfo.xbp; + info->var.right_margin = epinfo.xfp; + info->var.upper_margin = epinfo.ybp; + info->var.lower_margin = epinfo.yfp; + info->var.hsync_len = epinfo.xsync; + info->var.vsync_len = epinfo.ysync; + + if( epinfo.pol_xsync == POL_HIGH ) + info->var.sync |= FB_SYNC_HOR_HIGH_ACT; + if( epinfo.pol_ysync == POL_HIGH ) + info->var.sync |= FB_SYNC_VERT_HIGH_ACT; + + info->var.vmode = FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP; + info->fix.smem_start = epinfo.fb_phys; + info->fix.smem_len = epinfo.fb_size; + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.line_length = epinfo.xres * (epinfo.bpp / 8); + info->screen_base = epinfo.fb_log; + info->var.pixclock = epinfo.pixclock; + info->fix.ypanstep = 1; + info->fix.ywrapstep = 1; + +} + +static int ep93xxfb_config(struct fb_info *info) +{ + unsigned long attribs; + + DPRINTK("ep93xxfb_config - enter\n"); + + ep93xxfb_get_par( info ); + if( ep93xxfb_alloc_videomem() != 0 ) { + printk("Unable to allocate video memory\n"); + return -ENOMEM; + } + + if( ep93xxfb_setclk() != 0 ) { + printk("Unable to set pixel clock\n"); + ep93xxfb_release_videomem(); + return -ENODEV; + } + + SysconSetLocked(SYSCON_DEVCFG, inl(SYSCON_DEVCFG) | SYSCON_DEVCFG_RasOnP3); + ep93xxfb_timing_signal_generation(); + + /* set video memory parameters */ + outl(epinfo.fb_phys, VIDSCRNPAGE); + outl(epinfo.yres , SCRNLINES); + outl(((epinfo.xres * epinfo.bpp) / 32) - 1, LINELENGTH); + outl((epinfo.xres * epinfo.bpp) / 32, VLINESTEP); + + + /* set pixel mode */ + ep93xxfb_pixelmod(depth); + + attribs = 0; + +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + if(epinfo.clk_edge == EDGE_RISING) + attribs |= VIDEOATTRIBS_INVCLK; + if(epinfo.pol_blank == POL_HIGH) + attribs |= VIDEOATTRIBS_BLKPOL; + if(epinfo.pol_xsync == POL_HIGH) + attribs |= VIDEOATTRIBS_HSPOL; + if(epinfo.pol_ysync == POL_HIGH) + attribs |= VIDEOATTRIBS_VCPOL; + + ep93xxfb_outl(attribs, VIDEOATTRIBS); + ep93xxfb_setinfo( info ); + + if(epinfo.configure) + (epinfo.configure)( epinfo.automods ); + + ep93xxfb_blank( 0 , info ); + + DPRINTK("ep93xxfb_config - exit\n"); + return 0; +} + +int ep93xxfb_ioctl(struct fb_info *info,unsigned int cmd, unsigned long arg) +{ + struct fb_fillrect fill; + struct fb_copyarea cparea; + struct fb_image img; + struct ep93xx_line line; + struct ep93xx_cursor cursor; + unsigned long copy_ret = 0; + + switch (cmd) { + case FBIO_EP93XX_CURSOR: + copy_ret = copy_from_user(&cursor, (void *)arg, sizeof(struct ep93xx_cursor)); + ep93xxfb_cursor(info,&cursor); + break; + case FBIO_EP93XX_LINE: + copy_ret = copy_from_user(&line, (void *)arg, sizeof(struct ep93xx_line)); + ep93xxfb_line(info,&line); + break; + case FBIO_EP93XX_FILL: + copy_ret = copy_from_user(&fill, (void *)arg, sizeof(struct fb_fillrect)); + ep93xxfb_fillrect(info,&fill); + break; + case FBIO_EP93XX_BLIT: + copy_ret = copy_from_user(&img, (void *)arg, sizeof(struct fb_image)); + ep93xxfb_imageblit(info, &img); + break; + case FBIO_EP93XX_COPY: + copy_ret = copy_from_user(&cparea, (void *)arg, sizeof(struct fb_copyarea)); + ep93xxfb_copyarea(info,&cparea); + break; + default: + return -EFAULT; + } + if (copy_ret != 0) + return -1; + else + return 0; +} + + +static struct fb_ops ep93xxfb_ops = { + .owner = THIS_MODULE, + .fb_setcolreg = ep93xxfb_setcolreg, + .fb_check_var = ep93xxfb_check_var, + .fb_set_par = ep93xxfb_set_par, + .fb_blank = ep93xxfb_blank, + .fb_pan_display = ep93xx_pan_display, + .fb_fillrect = ep93xxfb_fillrect, + .fb_copyarea = ep93xxfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_cursor = ep93xxfb_cursor, + .fb_ioctl = ep93xxfb_ioctl, + .fb_mmap = ep93xxfb_mmap, +}; + + +static struct resource ep93xxfb_raster_resources = { + .start = EP93XX_RASTER_PHYS_BASE, + .end = EP93XX_RASTER_PHYS_BASE + 0x1ffff, + .flags = IORESOURCE_MEM, +}; + + +static int __init ep93xxfb_probe(struct platform_device *device) +{ + struct fb_info *info = NULL; + struct resource *res = NULL; + int ret = 0; + int arb = 0; + + DPRINTK("ep93xxfb_probe - enter \n"); + + + if(!device) { + printk("error : to_platform_device\n"); + return -ENODEV; + } + res = platform_get_resource( device, IORESOURCE_MEM, 0); + if(!res) { + printk("error : platform_get_resource \n"); + return -ENODEV; + } + cursor_data = kmalloc( 64 * 64 * 2, GFP_KERNEL ); + memset( cursor_data, 0x00, 64 * 64 * 2 ); + if(!cursor_data) { + printk("Unable to allocate memory for hw_cursor\n"); + return -ENOMEM; + } + if (!request_mem_region(res->start,res->end - res->start + 1, FBDEV_NAME )) + return -EBUSY; + + info = framebuffer_alloc(sizeof(u32) * 256, &device->dev); + + if(!info) { + printk("Unable to allocate memory for frame buffer\n"); + return -ENOMEM; + } + + info->flags = FBINFO_DEFAULT; + strncpy(info->fix.id, FBDEV_NAME, sizeof(info->fix.id)); + info->fix.mmio_start = res->start; + info->fix.mmio_len = res->end - res->start + 1; + info->fbops = &ep93xxfb_ops; + info->pseudo_palette = info->par; + info->state = FBINFO_STATE_RUNNING; + + if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { + ret = -ENOMEM; + goto fbuff; + } + + if ((ret = ep93xxfb_config(info)) < 0) + goto clmap; + + if (register_framebuffer(info) < 0) { + printk(KERN_ERR "Unable to register ep93xxfb frame buffer\n"); + ret = -EINVAL; + goto clmap; + } + platform_set_drvdata(device, info); + printk(KERN_INFO "fb%d: EP93xx frame buffer at %dx%dx%dbpp\n", info->node, + info->var.xres, info->var.yres, info->var.bits_per_pixel); + + register_reboot_notifier(&cx25871_notifier); + + /*change the raster arb to the highest one--Bo*/ + arb = inl(SYSCON_BMAR); + arb = (arb & 0x3f8) | 0x01; + outl(arb,SYSCON_BMAR); + + DPRINTK("ep93xxfb_probe - exit \n"); + return 0; + +clmap: + fb_dealloc_cmap(&info->cmap); + +fbuff: + framebuffer_release(info); + return ret; +} + +static int ep93xxfb_remove(struct platform_device *device) +{ + struct resource *res; + struct fb_info *info; + struct ep93xx_cursor cursor; + + DPRINTK("ep93xxfb_remove - enter \n"); + + info = platform_get_drvdata(device); + + ep93xxfb_release_videomem(); + + res = platform_get_resource( device, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + + platform_set_drvdata(device, NULL); + unregister_framebuffer(info); + + fb_dealloc_cmap(&info->cmap); + framebuffer_release(info); + + cursor.flags = CURSOR_OFF; + ep93xxfb_cursor(info,&cursor); + if(cursor_data!=NULL) + kfree(cursor_data); + + unregister_reboot_notifier(&cx25871_notifier); + ep93xxfb_blank( 1, info ); + + DPRINTK("ep93xxfb_remove - exit \n"); + return 0; +} + +static void ep93xxfb_platform_release(struct device *device) +{ + DPRINTK("ep93xxfb_platform_release - enter\n"); +} + +static int ep93xxfb_check_param(void) +{ + + switch(vout) { + case CRT_OUT: + if( vmode >=(sizeof(ep93xxfb_vmods)/sizeof(ep93xxfb_vmods[0]))){ + vmode = 1; + depth = DEFAULT_BPP; + return 0; + } + break; + case LCD_OUT: + DPRINTK("ep93xxfb_check_param: LCD_OUT\n"); + if(depth != 16) { + DPRINTK("ep93xxfb_check_param: vmode = %d, depth = %d\n", vmode, depth); + //vmode = 0; /* Not true anymore, could be the QVGA or PrimeView -- TAS */ + depth = DEFAULT_BPP; + return 0; + } + break; + case TV_OUT: + if( vmode >= CXMODES_COUNT ) { + vmode = DEFAULT_MODE; + depth = DEFAULT_BPP; + return 0; + } + break; + default: + vmode = DEFAULT_MODE; + depth = DEFAULT_BPP; + vout = DEFAULT_OUT; + return 0; + break; + } + + if(!((depth == 8) || (depth == 16) || (depth == 24) || (depth == 32))) + depth = DEFAULT_BPP; + + return 1; +} + +int __init ep93xxfb_setup(char *options) +{ + char *opt; + + DPRINTK("ep93xxfb_setup - %s\n",options); + + if (!options || !*options) + return 0; + + while ((opt = strsep(&options, ",")) != NULL) { + if (!strncmp(opt, "vout=", 5)) + vout = simple_strtoul(opt + 5, NULL, 0); + else if (!strncmp(opt, "vmode=", 6)) + vmode = simple_strtoul(opt + 6, NULL, 0); + else if (!strncmp(opt, "depth=", 6)) + depth = simple_strtoul(opt + 6, NULL, 0); + } + ep93xxfb_check_param(); + return 0; +} + + +static struct platform_driver ep93xxfb_driver = { + .probe = ep93xxfb_probe, + .remove = ep93xxfb_remove, + .driver = { + .name = FBDEV_NAME, + }, +}; + +static struct platform_device ep93xxfb_device = { + .name = FBDEV_NAME, + .id = -1, + .dev = { + .release = ep93xxfb_platform_release, + }, + .num_resources = 1, + .resource = &ep93xxfb_raster_resources, +}; + +int __init ep93xxfb_init(void) +{ + int ret = 0; + char *option = NULL; + + DPRINTK("ep93xxfb_init - enter\n"); + + if (fb_get_options("ep93xxfb", &option)) + return -ENODEV; + ep93xxfb_setup(option); + + + if( !ep93xxfb_check_param() ) { + printk("Unsupported format \n"); + return -1; + } + + ret = platform_driver_register(&ep93xxfb_driver); + + if (!ret) { + ret = platform_device_register(&ep93xxfb_device); + if (ret) + platform_driver_unregister(&ep93xxfb_driver); + } + outl(0x00000000, BLOCKCTRL); + request_irq(IRQ_EP93XX_GRAPHICS, ep93xxfb_irq_handler, SA_INTERRUPT, + "graphics",NULL); + + DPRINTK("ep93xxfb_init - exit\n"); + return ret; +} + + + +static void __exit ep93xxfb_exit(void) +{ + DPRINTK("ep93xxfb_exit - enter\n"); + platform_driver_unregister(&ep93xxfb_driver); + platform_device_unregister(&ep93xxfb_device); + DPRINTK("ep93xxfb_exit - exit\n"); +} + +module_init(ep93xxfb_init); +module_exit(ep93xxfb_exit); + + +module_param( vmode, int, 1); +MODULE_PARM_DESC(vmode, "Specify the video mode number that should be used"); +module_param( vout , int , 0 ); +MODULE_PARM_DESC(vout ,"Specify video output (0 = CRT ,1 = LCD , 2 = TV)"); +module_param( depth , int, 16); +MODULE_PARM_DESC(depth ,"Color depth (8,16,24,32)"); +MODULE_LICENSE("GPL"); diff -urN -x CVS linux-2.6.20/drivers/video/ep93xxfb.c~ linux-2.6.20-AT91/drivers/video/ep93xxfb.c~ --- linux-2.6.20/drivers/video/ep93xxfb.c~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/ep93xxfb.c~ 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,1790 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ep93xxfb.h" +#include "cx25871.h" +#include +#include + +extern int pls_proba; + +#define DEBUG 1 +#ifdef DEBUG +#define DPRINTK( fmt, arg... ) printk( fmt, ##arg ) +#else +#define DPRINTK( fmt, arg... ) +#endif + +#define FBDEV_NAME "ep93xxfb" + +#define ep93xxfb_outl(value, reg) \ +{ \ + outl(RASTER_SWLOCK_VALUE, RASTER_SWLOCK); \ + outl(value, reg); \ +} + +#if defined(CONFIG_FB_EP93XX_CRT) +#define DEFAULT_MODE 1 +#define DEFAULT_OUT CRT_OUT +#elif defined(CONFIG_FB_EP93XX_LCD) +#define DEFAULT_MODE 0 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_LCDWS) /* Wide screen */ +#define DEFAULT_MODE 17 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_QVGA) /* QVGA */ +#define DEFAULT_MODE 16 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_PAL) +#define DEFAULT_MODE 12 +#define DEFAULT_OUT TV_OUT +#elif defined(CONFIG_FB_EP93XX_NTSC) +#define DEFAULT_MODE 0 +#define DEFAULT_OUT TV_OUT +#else +#define DEFAULT_MODE 0 +#define DEFAULT_OUT LCD_OUT +#endif + +#if defined(CONFIG_FB_EP93XX_8BPP) +#define DEFAULT_BPP 8 +#elif defined(CONFIG_FB_EP93XX_16BPP) +#define DEFAULT_BPP 16 +#else +#define DEFAULT_BPP 16 +#endif + +static DECLARE_WAIT_QUEUE_HEAD(ep93xxfb_wait_in); + +static unsigned int pseudo_palette[256]; +static unsigned long *cursor_data = NULL; +static struct ep93xxfb_info epinfo; + +static int vout = DEFAULT_OUT; +static int vmode = DEFAULT_MODE; +static int depth = DEFAULT_BPP; + +static int ep93xxfb_setcol(struct fb_info *info, int bpp); + +struct cx25871_vmodes cxmods[CXMODES_COUNT]= +{ + + { "CX25871-NTSC", 0x10, 640, 400, 936, 525, 259, 76, 29454552 }, // 0 + { "CX25871-NTSC", 0x00, 640, 480, 784, 600, 126, 75, 28195793 }, // 1 + { "CX25871-NTSC", 0x40, 640, 480, 770, 645, 113, 100, 29769241 }, // 2 + { "CX25871-NTSC", 0x30, 720, 400, 1053, 525, 291, 76, 33136345 }, // 3 + { "CX25871-NTSC", 0x54, 720, 480, 880, 525, 140, 36, 27692310 }, // 4 + { "CX25871-NTSC", 0x02, 800, 600, 880, 735, 66, 86, 38769241 }, // 5 + { "CX25871-NTSC", 0x22, 800, 600, 1176, 750, 329, 94, 52867138 }, // 6 + { "CX25871-NTSC", 0x42, 800, 600, 1170, 805, 323, 125, 56454552 }, // 7 + { "CX25871-NTSC", 0x50, 800, 600, 1170, 770, 323, 105, 54000000 }, // 8 + { "CX25871-NTSC", 0x12, 1024, 768, 1176, 975, 133, 130,68727276 }, // 9 + { "CX25871-NTSC", 0x32, 1024, 768, 1170, 945, 127, 115, 66272724 }, // 10 + { "CX25871-NTSC", 0x52, 1024, 768, 1170, 1015, 127, 150, 71181793 },// 11 + + { "CX25871-PAL", 0x11, 640, 400, 1160, 500, 363, 64, 28999992 }, // 12 + { "CX25871-PAL", 0x01, 640, 480, 944, 625, 266, 90, 29500008 }, // 13 + { "CX25871-PAL", 0x21, 640, 480, 950, 600, 271,76 , 28500011 }, // 14 + { "CX25871-PAL", 0x41, 640, 480, 950, 650, 271, 104, 30875015 }, // 15 + { "CX25871-PAL-M", 0x56, 640, 480, 784, 600, 126, 75, 28195793 }, // 16 + { "CX25871-PAL-Nc", 0x57, 640, 480, 944, 625, 266, 90, 29500008 }, // 17 + { "CX25871-PAL", 0x31, 720, 400, 1305, 500, 411, 64, 32625000 }, // 18 + { "CX25871-PAL", 0x03, 800, 600, 960, 750, 140, 95, 36000000 }, // 19 + { "CX25871-PAL", 0x23, 800, 600, 950, 775, 131, 109, 36812508 }, // 20 + { "CX25871-PAL", 0x43, 800, 600, 950, 800, 131, 122, 37999992 }, // 21 + { "CX25871-PAL", 0x13, 1024, 768, 1400, 975, 329, 131, 68249989 }, // 22 + { "CX25871-PAL", 0x53, 1024, 768, 1410, 1000, 337, 147, 70499989 },// 23 + +}; + +static int cx25871_reboot(struct notifier_block *this, unsigned long event, void *x) +{ + switch (event) + { + case SYS_HALT: + case SYS_POWER_OFF: + case SYS_RESTART: + write_reg(0xba, 0x80); + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block cx25871_notifier = +{ + cx25871_reboot, + NULL, + 5 +}; + + +int write_reg(unsigned char ucRegAddr, unsigned char ucRegValue) +{ + unsigned long uiVal, uiDDR; + unsigned char ucData, ucIdx, ucBit; + unsigned long ulTimeout; + + uiVal = inl(GPIO_PGDR); + uiDDR = inl(GPIO_PGDDR); + uiVal |= (GPIOG_EEDAT | GPIOG_EECLK); + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiDDR |= (GPIOG_EEDAT | GPIOG_EECLK); + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + uiVal &= ~GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal &= ~GPIOG_EECLK; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + + for (ucIdx = 0; ucIdx < 3; ucIdx++) { + if (ucIdx == 0) + ucData = (unsigned char)CX25871_DEV_ADDRESS; + else if (ucIdx == 1) + ucData = ucRegAddr; + else + ucData = ucRegValue; + + for (ucBit = 0; ucBit < 8; ucBit++) { + if (ucData & 0x80) + uiVal |= GPIOG_EEDAT; + else + uiVal &= ~GPIOG_EEDAT; + + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + outl( (uiVal | GPIOG_EECLK), GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + ucData <<= 1; + } + + uiDDR &= ~GPIOG_EEDAT; + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + outl( (uiVal | GPIOG_EECLK), GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + ulTimeout = 0; + while ( inl(GPIO_PGDR) & GPIOG_EEDAT ) { + udelay( EE_DELAY_USEC ); + ulTimeout++; + if (ulTimeout > EE_READ_TIMEOUT ) + return 1; + } + + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiDDR |= GPIOG_EEDAT; + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + } + + uiVal &= ~GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal |= GPIOG_EECLK; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal |= GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + return 0; +} + +void cx25871_on( unsigned char value ) +{ + write_reg(0x30,0x00); + write_reg(0xBA, 0x20 ); +} + +void cx25871_off( unsigned char value ) +{ + write_reg(0xBA, 0x30); + write_reg(0xC4, 0x00); + write_reg(0x30, 0x02); +} + +void cx25871_config( unsigned char value ) +{ + write_reg(0xBA, CX25871_REGxBA_SRESET); + mdelay(1); + write_reg(0xB8, value); + write_reg(0xBA, CX25871_REGxBA_SLAVER | CX25871_REGxBA_DACOFF); + write_reg(0xC6,(CX25871_REGxC6_INMODE_MASK & 0x3)); + write_reg(0xC4, CX25871_REGxC4_EN_OUT); + write_reg(0xBA, CX25871_REGxBA_SLAVER ); +} + +static struct ep93xxfb_videomodes ep93xxfb_vmods[] = { + { // 0 + "Philips-LB064V02-640x480x60", + 640, 24, 96, 40, 480, 10, 2, 33, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 1 + "CRT-640x480-60", + 640, 24, 96, 40, 480, 11, 2, 32, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 2 + "CRT-640x480-72", + 640, 40, 40, 144, 480, 8, 3, 30, 72, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 3 + "CRT-640x480-75", + 640, 16, 76, 120, 480, 1, 3, 16, 75, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 4 + "CRT-640x480-85", + 640, 56, 56, 80, 480, 1, 3, 25, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 5 + "CTR-640x480-100", + 640, 32, 96, 96, 480, 8, 6, 36, 100, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 6 + "CRT-800x600-56", + 800, 24, 72, 128, 600, 1, 2, 22, 56, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 7 + "CRT-800x600-60", + 800, 40, 128, 88, 600, 1, 4, 23, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 8 + "CRT-800x600-72", + 800, 56, 120, 64, 600, 37, 6, 23, 72, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 9 + "CRT-800x600-85", + 800, 64, 64, 160, 600, 16, 5, 36, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 10 + "CRT-800x600-100", + 800, 64, 64, 160, 600, 4, 6, 30, 100, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 11 + "CRT-1024x768-60", + 1024, 8, 144, 168, 768, 3, 6, 29, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 12 + "CRT-1024x768-70", + 1024, 24, 136, 144, 768, 3, 6, 29, 70, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 13 + "CRT-1024x768-75", + 1024, 16, 96, 176, 768, 1, 3, 28, 75, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 14 + "CRT-1024x768-85", + 1024, 48, 96, 208, 768, 1, 3, 36, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 15 + "CRT-1280x720-60", + 1280, 48, 112, 248, 720, 1, 3, 38, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + /* Add support for the LB040Q02 QVGA and the Primeview PM070WX2 800x480 LCD */ + /* TAS */ + { // 16 + "LB040Q02-QVGA-320x240", + 320, 25, 30, 25, 240, 6, 7, 10, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 17 + "PM070WX2-800x480", + 800, 24, 96, 40, 480, 10, 2, 33, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + } +}; + +static void philips_lb064v02_on(unsigned char value) +{ + DPRINTK("philips_lb064v02_on \n"); + DPRINTK("GPIO pin is set to %d\n", CONFIG_FB_EP93XX_GPIO); + /* The GPIO line that turns on power to the LCD differs + * depending on the board. This has been moved to the + * Kconfig as an option. Currently, the EDB9315A board + * should use 2, the EMAC Thermatron board uses 1. + */ + /*outl(inl(GPIO_PADDR) | 2, GPIO_PADDR); */ + /*outl(inl(GPIO_PADDR) | 1, GPIO_PADDR); */ + outl(inl(GPIO_PADDR) | CONFIG_FB_EP93XX_GPIO, GPIO_PADDR); + /*outl(inl(GPIO_PADR) | 2, GPIO_PADR); */ + /*outl(inl(GPIO_PADR) | 1, GPIO_PADR); */ + outl(inl(GPIO_PADDR) | CONFIG_FB_EP93XX_GPIO, GPIO_PADDR); +} + +static void philips_lb064v02_off(unsigned char value) +{ + DPRINTK("philips_lb064v02_off \n"); + outl(inl(GPIO_PADR) & ~2, GPIO_PADR); +} + +static irqreturn_t ep93xxfb_irq_handler(int i, void *blah, struct pt_regs *regs) +{ + outl(0x00000000, BLOCKCTRL); + wake_up(&ep93xxfb_wait_in); + return IRQ_HANDLED; +} + +static void ep93xxfb_wait(void) +{ + DECLARE_WAITQUEUE(wait, current); + add_wait_queue(&ep93xxfb_wait_in, &wait); + set_current_state(TASK_UNINTERRUPTIBLE); + + while (inl(BLOCKCTRL) & 0x00000001){ + if((pls_proba==1)&&(!in_atomic())) + schedule(); + } + + remove_wait_queue(&ep93xxfb_wait_in, &wait); + set_current_state(TASK_RUNNING); + +} + +void ep93xxfb_fillrect(struct fb_info *p, const struct fb_fillrect *fill) +{ + unsigned long blkdestwidth,tmp; + + if (!fill->width || !fill->height || + (fill->dx >= p->var.xres) || + (fill->dy >= p->var.yres) || + ((fill->dx + fill->width - 1) >= p->var.xres) || + ((fill->dy + fill->height - 1) >= p->var.yres)) + return; + + tmp = (( fill->dx + fill->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (fill->dx * epinfo.bpp) / 32; + + outl(fill->color, BLOCKMASK); + outl( ((fill->dx * epinfo.bpp) & 0x1F) | + ((((fill->dx + fill->width - 1) * epinfo.bpp ) & 0x1F) << 16), + DESTPIXELSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH); + outl( blkdestwidth, BLKDESTWIDTH ); + outl(fill->height - 1, BLKDESTHEIGHT); + outl((epinfo.fb_phys + (fill->dy * epinfo.xres * epinfo.bpp ) / 8 + + (fill->dx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( epinfo.pixformat | 0x0000000B, BLOCKCTRL); + ep93xxfb_wait(); + +} + +void ep93xxfb_copyarea(struct fb_info *p, const struct fb_copyarea *area) +{ + unsigned long startsx,stopsx,startdx,stopdx,startsy,startdy; + unsigned long blksrcwidth,blkdestwidth,tmp; + unsigned long val = 0; + + if( !area->width || !area->width || + (area->sx >= p->var.xres) || (area->sy >= p->var.yres) || + (area->dx >= p->var.xres) || (area->dy >= p->var.yres) || + ((area->dx + area->width - 1) >= p->var.xres) || + ((area->dy + area->height - 1) >= p->var.yres)) + return; + + if(area->sx == area->dx && area->sy == area->dy) + return; + + if ((area->dy == area->sy) && (area->dx > area->sx) && + (area->dx < (area->sx + area->width - 1))) { + startdx = area->dx + area->width - 1; + stopdx = area->dx; + startsx = area->sx + area->width - 1; + stopsx = area->sx; + val |= 0x000000A0; + } + else { + startdx = area->dx; + stopdx = area->dx + area->width - 1; + startsx = area->sx; + stopsx = area->sx + area->width - 1; + } + + if (area->dy <= area->sy) { + startdy = area->dy; + startsy = area->sy; + } + else { + startdy = area->dy + area->height -1; + startsy = area->sy + area->height -1; + val |= 0x00000140; + } + + tmp = (( area->sx + area->width ) * epinfo.bpp ); + blksrcwidth = tmp / 32; + if(blksrcwidth > 0 && (tmp % 32 == 0)) + blksrcwidth--; + blksrcwidth = blksrcwidth - (area->sx * epinfo.bpp) / 32; + tmp = (( area->dx + area->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (area->dx * epinfo.bpp) / 32; + + outl( 0x00000000 , BLOCKCTRL); + + /*** src ***/ + outl((((startsx * epinfo.bpp) & 0x1F) | + (((stopsx * epinfo.bpp ) & 0x1F) << 16)) + , SRCPIXELSTRT); + outl((epinfo.fb_phys + (startsy * epinfo.xres * epinfo.bpp ) / 8 + + (startsx * epinfo.bpp ) / 8 ) + , BLKSRCSTRT); + outl(((epinfo.xres * epinfo.bpp) / 32), SRCLINELENGTH); + outl( blksrcwidth, BLKSRCWIDTH ); + + /*** dest ***/ + outl((((startdx * epinfo.bpp) & 0x1F) | + (((stopdx * epinfo.bpp ) & 0x1F) << 16)) + , DESTPIXELSTRT); + outl((epinfo.fb_phys + (startdy * epinfo.xres * epinfo.bpp ) / 8 + + (startdx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH); + outl( blkdestwidth, BLKDESTWIDTH); + outl( area->height - 1 , BLKDESTHEIGHT); + outl( epinfo.pixformat | val | 0x00000003, BLOCKCTRL); + ep93xxfb_wait(); +} + +void ep93xxfb_imageblit(struct fb_info *p, const struct fb_image *image) +{ +// unsigned long blkdestwidth,tmp; +// void * pucBlitBuf; + cfb_imageblit( p , image ); + return; +/* + if ((image->dx >= p->var.xres) || + (image->dy >= p->var.yres) || + ((image->dx + image->width - 1) >= p->var.xres) || + ((image->dy + image->height - 1) >= p->var.yres)) + return; + if (epinfo.bpp != image->depth ) + return; + + tmp = (( image->dx + image->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (image->dx * epinfo.bpp) / 32; + + pucBlitBuf = kmalloc(1024*8,GFP_KERNEL); + copy_from_user(pucBlitBuf, image->data, 5000); + + outl( 0x00000000 , BLOCKCTRL); + + outl( 0x00000000, SRCPIXELSTRT); + outl( virt_to_phys(pucBlitBuf), BLKSRCSTRT); + outl( (image->width * epinfo.bpp) / 32 , SRCLINELENGTH); + outl(((image->width - 1) * epinfo.bpp) / 32, BLKSRCWIDTH ); + + outl(((image->dx * epinfo.bpp) & 0x1F) | + ((((image->dx + image->width - 1) * epinfo.bpp ) & 0x1F) << 16) + , DESTPIXELSTRT); + outl((epinfo.fb_phys + (image->dy * epinfo.xres * epinfo.bpp ) / 8 + + (image->dx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH ); + outl( blkdestwidth, BLKDESTWIDTH ); + outl( image->height - 1 , BLKDESTHEIGHT); + outl(image->fg_color, BLOCKMASK); + outl(image->bg_color, BACKGROUND); + outl( epinfo.pixformat | 0x00000003, BLOCKCTRL ); + ep93xxfb_wait(); +*/ +} + + +static unsigned long isqrt(unsigned long a) +{ + unsigned long rem = 0; + unsigned long root = 0; + int i; + + for (i = 0; i < 16; i++) { + root <<= 1; + rem = ((rem << 2) + (a >> 30)); + a <<= 2; + root++; + if (root <= rem) { + rem -= root; + root++; + } + else + root--; + } + return root >> 1; +} + +int ep93xxfb_line(struct fb_info *info, struct ep93xx_line *line) +{ + unsigned long value = 0; + long x, y, dx, dy, count, xinc, yinc, xval, yval, incr; + + if ((line->x1 > info->var.xres) || + (line->x2 > info->var.xres) || + (line->y1 > info->var.yres) || + (line->y2 > info->var.yres)) + return -EFAULT; + x = line->x1; + y = line->y1; + dx = line->x2 - line->x1; + dy = line->y2 - line->y1; + + if ( !dx || !dy ) + return -EFAULT; + + if ( dx < 0 && dy < 0 ) { + x = line->x2; + y = line->y2; + dx *= -1; + dy *= -1; + } + else if ( dx < 0 && dy > 0 ){ + dx *= -1; + value = 0x000000A0; + } + else if( dy < 0 && dx > 0 ){ + dy *= -1; + value = 0x00000140; + } + + if (line->flags & LINE_PRECISE) { + count = isqrt(((dy * dy) + (dx * dx)) * 4096); + xinc = (4095 * 64 * dx) / count; + yinc = (4095 * 64 * dy) / count; + xval = 2048; + yval = 2048; + count = 0; + while (dx || dy) { + incr = 0; + xval -= xinc; + if (xval <= 0) { + xval += 4096; + dx--; + incr = 1; + } + yval -= yinc; + if (yval <= 0) { + yval += 4096; + dy--; + incr = 1; + } + count += incr; + } + } + else { + if ( dx == dy ) { + xinc = 4095; + yinc = 4095; + count = dx; + + } + else if ( dx < dy ) { + xinc = ( dx * 4095 ) / dy; + yinc = 4095; + count = dy; + + } + else { + xinc = 4095; + yinc = ( dy * 4095 ) / dx; + count = dx; + } + } + + outl(0x08000800, LINEINIT); + if (line->flags & LINE_PATTERN) + outl(line->pattern, LINEPATTRN); + else + outl(0x000fffff, LINEPATTRN); + outl(epinfo.fb_phys + ((y * epinfo.xres * epinfo.bpp) / 8) + + ((x * epinfo.bpp ) / 8 ), BLKDSTSTRT); + + outl(((x * epinfo.bpp) & 0x1F) | + ((((x + dx - 1) * epinfo.bpp) & 0x1F ) << 16), + DESTPIXELSTRT); + outl((epinfo.xres * epinfo.bpp) / 32, DESTLINELENGTH); + outl(line->fgcolor, BLOCKMASK); + outl(line->bgcolor, BACKGROUND); + outl((yinc << 16) | xinc, LINEINC); + outl( count & 0xFFF, BLKDESTWIDTH); + outl( 0 , BLKDESTHEIGHT); + value |= (line->flags & LINE_BACKGROUND) ? 0x00004000 : 0; + outl(epinfo.pixformat | value | 0x00000013, BLOCKCTRL); + ep93xxfb_wait(); + return 0; +} + + +int ep93xxfb_cursor(struct fb_info *info, struct ep93xx_cursor *cursor) +{ + unsigned long x,y,save,copy_ret; + copy_ret = 0; + + if (cursor->width > 64 || cursor->height > 64) + return -ENXIO; + + if (cursor->flags & CURSOR_OFF) + outl(inl(CURSORXYLOC) & ~0x00008000, CURSORXYLOC); + + if (cursor->flags & CURSOR_SETSHAPE) { + copy_ret = copy_from_user(cursor_data, cursor->data, + cursor->width * cursor->height / 4); + save = inl(CURSORXYLOC); + outl(save & ~0x00008000, CURSORXYLOC); + + outl(virt_to_phys(cursor_data), CURSOR_ADR_START); + outl(virt_to_phys(cursor_data), CURSOR_ADR_RESET); + outl(((cursor->width - 1) & 0x30) << 4 | ((cursor->height - 1) << 2) | + ((cursor->width - 1) >> 4), CURSORSIZE); + outl(save, CURSORXYLOC); + + } + + if (cursor->flags & CURSOR_SETCOLOR) { + outl(cursor->color1, CURSORCOLOR1); + outl(cursor->color2, CURSORCOLOR2); + outl(cursor->blinkcolor1, CURSORBLINK1); + outl(cursor->blinkcolor2, CURSORBLINK2); + } + + if (cursor->flags & CURSOR_BLINK) { + if (cursor->blinkrate) + outl(0x00000100 | cursor->blinkrate, CURSORBLINK); + else + outl(0x0000000FF, CURSORBLINK); + } + + if (cursor->flags & CURSOR_MOVE) { + x = (inl(HACTIVESTRTSTOP) & 0x000007ff) - cursor->dx - 2; + y = (inl(VACTIVESTRTSTOP) & 0x000007ff) - cursor->dy; + outl((inl(CURSORXYLOC) & 0x8000) | (y << 16) | x, CURSORXYLOC); + } + + if(cursor->flags & CURSOR_ON) + outl(inl(CURSORXYLOC) | 0x00008000, CURSORXYLOC); + if (copy_ret != 0) + return -1; + else + return 0; +} + +static inline void +ep93xxfb_palette_write(u_int regno, u_int red, u_int green, + u_int blue, u_int trans) +{ + unsigned int cont, i, pal; + DPRINTK("ep93xxfb_palette_write - enter\n"); + pal = ((red & 0xFF00) << 8) | (green & 0xFF00) | ((blue & 0xFF00) >> 8); + pseudo_palette[regno] = pal; + outl( pal, ( COLOR_LUT + ( regno << 2 ))); + cont = inl( LUTCONT ); + + if (( cont & LUTCONT_STAT && cont & LUTCONT_RAM1 ) || + ( !( cont & LUTCONT_STAT ) && !( cont&LUTCONT_RAM1 ))) { + for ( i = 0; i < 256; i++ ) { + outl( pseudo_palette[i], ( COLOR_LUT + ( i << 2 )) ); + } + outl( cont ^ LUTCONT_RAM1, LUTCONT ); + } +} + +int ep93xxfb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + +#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) + + switch ( info->fix.visual ) + { + case FB_VISUAL_PSEUDOCOLOR: + ep93xxfb_palette_write(regno, red, green, blue, transp); + break; + case FB_VISUAL_TRUECOLOR: + if (regno >= 16) + return 1; + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + ((u32 *)(info->pseudo_palette))[regno] = + (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + return 0; +} + +static int ep93xx_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + DPRINTK("ep93xx_pan_display - enter\n"); + + if (var->yoffset < 0 + || var->yoffset + var->yres > info->var.yres_virtual + || var->xoffset) + return -EINVAL; + + outl(epinfo.fb_phys + info->fix.line_length * var->yoffset + , VIDSCRNPAGE); + + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + + DPRINTK("ep93xx_pan_display - exit\n"); + return 0; +} + + +static int +ep93xxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct fb_var_screeninfo tmp_var; + unsigned long pclk; + DPRINTK("ep93xxfb_check_var - enter\n"); + + memcpy (&tmp_var, var, sizeof (tmp_var)); + + if( (tmp_var.vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED ) { + DPRINTK(" ep93xxfb_check_var - unsupported video mode\n"); + return -EINVAL; + } + + if( ((tmp_var.xres * tmp_var.yres * tmp_var.bits_per_pixel) / 8) > + MAX_FBMEM_SIZE ) { + DPRINTK(" ep93xxfb_check_var - memory error \n"); + return -ENOMEM; + } + + if( ((tmp_var.xres_virtual * tmp_var.yres_virtual * tmp_var.bits_per_pixel) / 8) > + MAX_FBMEM_SIZE ) { + DPRINTK(" ep93xxfb_check_var - memory error \n"); + return -ENOMEM; + } + + pclk = 1000 * (1000000000 / tmp_var.pixclock); + + if( pclk > ep93xx_get_max_video_clk() ) { + DPRINTK(" ep93xxfb_check_var - pixel clock error %lu\n",pclk); + return -EINVAL; + } + + if (var->xres_virtual != var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if (var->xoffset < 0) + var->xoffset = 0; + if (var->yoffset < 0) + var->yoffset = 0; + + switch (tmp_var.bits_per_pixel) { + case 8: + break; + case 16: + break; + case 24: + break; + case 32: + break; + default: + return -EINVAL; + } + + DPRINTK("ep93xxfb_check_var - exit\n"); + return 0; +} + + +static int ep93xxfb_set_par(struct fb_info *info) +{ + struct fb_var_screeninfo tmp_var; + unsigned long attribs; + + DPRINTK("ep93xxfb_set_par - enter\n"); + + if( ep93xxfb_check_var(&info->var,info) < 0 ) + return -EINVAL; + + if( !ep93xxfb_setcol(info,info->var.bits_per_pixel) ) + return -EINVAL; + + + info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8; + + ep93xxfb_blank( 1 , info ); + + memcpy(&tmp_var,&info->var,sizeof(tmp_var)); + + epinfo.xres = tmp_var.xres; + epinfo.xsync = tmp_var.hsync_len; + epinfo.xfp = tmp_var.right_margin; + epinfo.xbp = tmp_var.left_margin; + epinfo.xtotal = epinfo.xres + epinfo.xsync + + epinfo.xfp + epinfo.xbp; + + epinfo.yres = tmp_var.yres; + epinfo.ysync = tmp_var.vsync_len; + epinfo.yfp = tmp_var.lower_margin; + epinfo.ybp = tmp_var.upper_margin; + epinfo.ytotal = epinfo.yres + epinfo.ysync + + epinfo.yfp + epinfo.ybp; + + epinfo.pixclock = tmp_var.pixclock ; + epinfo.refresh = 1000 * (1000000000 / tmp_var.pixclock) ; + + if( epinfo.refresh > ep93xx_get_max_video_clk()) + epinfo.refresh = ep93xx_get_max_video_clk(); + epinfo.bpp = tmp_var.bits_per_pixel; + + ep93xxfb_setclk(); + ep93xxfb_timing_signal_generation(); + + // set video memory parameters + outl(epinfo.fb_phys, VIDSCRNPAGE); + outl(epinfo.yres , SCRNLINES); + outl(((epinfo.xres * epinfo.bpp) / 32) - 1, LINELENGTH); + outl((epinfo.xres * epinfo.bpp) / 32, VLINESTEP); + + // set pixel mode + ep93xxfb_pixelmod(epinfo.bpp); + + attribs = 0; +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + /* We can't set the clock here, we don't know anything + * about it yet. This causes the clock to always be + * rising edge, which distorts the image. It is set if + * needed in the ep93xx_config function. -- TAS */ + //attribs |= VIDEOATTRIBS_INVCLK; + if( tmp_var.sync & FB_SYNC_HOR_HIGH_ACT ) + attribs |= VIDEOATTRIBS_HSPOL; + if( tmp_var.sync & FB_SYNC_VERT_HIGH_ACT ) + attribs |= VIDEOATTRIBS_VCPOL; + + ep93xxfb_outl(attribs, VIDEOATTRIBS); + ep93xxfb_blank( 0 , info ); + + DPRINTK("ep93xxfb_set_par - exit\n"); + + return 0; +} + + +static int ep93xxfb_blank(int blank_mode,struct fb_info *info) +{ + unsigned long attribs; + DPRINTK("ep93xxfb_blank - enter\n"); + attribs = inl(VIDEOATTRIBS); + +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + if (blank_mode) { + if (epinfo.off) + (epinfo.off)( 0 ); + + ep93xxfb_outl(attribs & ~(VIDEOATTRIBS_DATAEN | + VIDEOATTRIBS_SYNCEN | VIDEOATTRIBS_PCLKEN | + VIDEOATTRIBS_EN), VIDEOATTRIBS); + } + else { + if (epinfo.clk_src == CLK_INTERNAL) + attribs |= VIDEOATTRIBS_PCLKEN; + else + attribs &= ~VIDEOATTRIBS_PCLKEN; + + ep93xxfb_outl(attribs | VIDEOATTRIBS_DATAEN | + VIDEOATTRIBS_SYNCEN | VIDEOATTRIBS_EN, + VIDEOATTRIBS); + + if (epinfo.configure) + (epinfo.configure)( epinfo.automods ); + if (epinfo.on) + (epinfo.on)( 0 ); + } + return 0; +} + +static int ep93xxfb_mmap(struct fb_info *info,struct vm_area_struct *vma) +{ + unsigned long off, start, len; + + DPRINTK("ep93xxfb_mmap - enter\n"); + + off = vma->vm_pgoff << PAGE_SHIFT; + start = info->fix.smem_start; + len = PAGE_ALIGN(start & ~PAGE_MASK) + info->fix.smem_len; + start &= PAGE_MASK; + if ((vma->vm_end - vma->vm_start + off) > len) + return -EINVAL; + + off += start; + vma->vm_pgoff = off >> PAGE_SHIFT; + + vma->vm_flags |= VM_IO; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + DPRINTK("ep93xxfb_mmap error\n"); + return -EAGAIN; + } + + DPRINTK("ep93xxfb_mmap - exit\n"); + return 0; +} + +static unsigned long ep93xx_get_pll_frequency(unsigned long pll) +{ + unsigned long fb1, fb2, ipd, ps, freq; + + if (pll == 1) + pll = inl(SYSCON_CLKSET1); + else if (pll == 2) + pll = inl(SYSCON_CLKSET2); + else + return 0; + + ps = (pll & SYSCON_CLKSET1_PLL1_PS_MASK) >> SYSCON_CLKSET1_PLL1_PS_SHIFT; + fb1 = ((pll & SYSCON_CLKSET1_PLL1_X1FBD1_MASK) >> SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT); + fb2 = ((pll & SYSCON_CLKSET1_PLL1_X2FBD2_MASK) >> SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT); + ipd = ((pll & SYSCON_CLKSET1_PLL1_X2IPD_MASK) >> SYSCON_CLKSET1_PLL1_X2IPD_SHIFT); + + freq = (((0x00e10000 * (fb1+1)) / (ipd+1)) * (fb2+1)) >> ps; + return freq; +} + +static int ep93xx_get_max_video_clk() +{ + unsigned long f,freq = 0; + + freq = 14745600 / 4; + f = ep93xx_get_pll_frequency(1) / 4; + if ( f > freq ) + freq = f; + f = ep93xx_get_pll_frequency(2) / 4; + if ( f > freq ) + freq = f; + + return freq; +} + +static int ep93xx_set_video_div(unsigned long freq) +{ + unsigned long pdiv = 0, div = 0, psel = 0, esel = 0; + unsigned long err, f, i, j, k; + + err = -1; + + for (i = 0; i < 3; i++) { + if (i == 0) + f = 14745600 * 2; + else if (i == 1) + f = ep93xx_get_pll_frequency(1) * 2; + else + f = ep93xx_get_pll_frequency(2) * 2; + + for (j = 4; j <= 6; j++) { + k = f / (freq * j); + if (k < 2) + continue; + + if (abs(((f / (j * k))) - freq ) < err ) { + pdiv = j - 3; + div = k; + psel = (i == 2) ? 1 : 0; + esel = (i == 0) ? 0 : 1; + err = (f / (j * k)) - freq; + } + } + } + + if (err == -1) + return -1; + + outl(0xaa, SYSCON_SWLOCK); + outl(SYSCON_VIDDIV_VENA | (esel ? SYSCON_VIDDIV_ESEL : 0) | + (psel ? SYSCON_VIDDIV_PSEL : 0) | + (pdiv << SYSCON_VIDDIV_PDIV_SHIFT) | + (div << SYSCON_VIDDIV_VDIV_SHIFT), SYSCON_VIDDIV); + + return freq + err; +} + +static void ep93xxfb_pixelmod(int bpp) +{ + unsigned long tmpdata = 0; + + DPRINTK("ep93xxfb_pixelmod %dbpp -enter\n",bpp); + switch(bpp) { + case 8: + tmpdata = PIXELMODE_P_8BPP | + PIXELMODE_S_1PPCMAPPED | + PIXELMODE_C_LUT; + epinfo.pixformat = PIXEL_FORMAT_8; + break; + case 16: + tmpdata = PIXELMODE_P_16BPP | + PIXELMODE_S_1PPCMAPPED | + PIXELMODE_C_565; + epinfo.pixformat = PIXEL_FORMAT_16; + break; + case 24: + tmpdata = PIXELMODE_P_24BPP | + PIXELMODE_S_1PPC | + PIXELMODE_C_888; + epinfo.pixformat = PIXEL_FORMAT_24; + break; + case 32: + tmpdata = PIXELMODE_P_32BPP | + PIXELMODE_S_1PPC | + PIXELMODE_C_888; + epinfo.pixformat = PIXEL_FORMAT_32; + break; + default: + break; + } + outl(tmpdata,PIXELMODE); +} + +static void ep93xxfb_timing_signal_generation(void) +{ + unsigned long vlinestotal,vsyncstart,vsyncstop, + vactivestart,vactivestop, + vblankstart,vblankstop, + vclkstart,vclkstop; + + unsigned long hclkstotal,hsyncstart,hsyncstop, + hactivestart,hactivestop, + hblankstart,hblankstop, + hclkstart,hclkstop; + + DPRINTK("ep93xxfb_timing_signal_generation - enter\n"); + + vlinestotal = epinfo.ytotal - 1; + vsyncstart = vlinestotal; + vsyncstop = vlinestotal - epinfo.ysync; + vblankstart = vlinestotal - epinfo.ysync - epinfo.ybp; + vblankstop = epinfo.yfp - 1; + vactivestart = vblankstart; + vactivestop = vblankstop; + vclkstart = vlinestotal; + vclkstop = vlinestotal + 1; + + hclkstotal = epinfo.xtotal - 1; + hsyncstart = hclkstotal; + hsyncstop = hclkstotal - epinfo.xsync; + hblankstart = hclkstotal - epinfo.xsync - epinfo.xbp; + hblankstop = epinfo.xfp - 1; + hactivestart = hblankstart; + hactivestop = hblankstop; + hclkstart = hclkstotal ; + hclkstop = hclkstotal ; + + ep93xxfb_outl(0, VIDEOATTRIBS); + + ep93xxfb_outl( vlinestotal , VLINESTOTAL ); + ep93xxfb_outl( vsyncstart + (vsyncstop << 16), VSYNCSTRTSTOP ); + ep93xxfb_outl( vactivestart + (vactivestop << 16), VACTIVESTRTSTOP ); + ep93xxfb_outl( vblankstart + (vblankstop << 16), VBLANKSTRTSTOP ); + ep93xxfb_outl( vclkstart + (vclkstop << 16), VCLKSTRTSTOP ); + + ep93xxfb_outl( hclkstotal , HCLKSTOTAL ); + ep93xxfb_outl( hsyncstart + (hsyncstop << 16), HSYNCSTRTSTOP ); + ep93xxfb_outl( hactivestart + (hactivestop << 16) , HACTIVESTRTSTOP ); + ep93xxfb_outl( hblankstart + (hblankstop << 16) , HBLANKSTRTSTOP ); + ep93xxfb_outl( hclkstart + (hclkstop << 16) , HCLKSTRTSTOP ); + + ep93xxfb_outl(0, LINECARRY); + +} + +static int ep93xxfb_setcol(struct fb_info *info, int bpp) +{ + + DPRINTK("ep93xxfb_setcol %dbpp\n",bpp); + switch(bpp) { + case 8: + info->var.bits_per_pixel = 8; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + break; + case 16: + info->var.bits_per_pixel = 16; + info->var.red.offset = 11; + info->var.red.length = 5; + info->var.green.offset = 5; + info->var.green.length = 6; + info->var.blue.offset = 0; + info->var.blue.length = 5; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + case 24: + info->var.bits_per_pixel = 24; + info->var.red.length = 8; + info->var.blue.length = 8; + info->var.green.length = 8; + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + case 32: + info->var.bits_per_pixel = 32; + info->var.red.length = 8; + info->var.blue.length = 8; + info->var.green.length = 8; + info->var.transp.length = 0; + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.transp.offset = 0; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + default: + return 0; + } + return 1; +} + +static int ep93xxfb_setclk() +{ + unsigned long calc_clk,act_clk; + + if ( epinfo.clk_src == CLK_INTERNAL ) { + outl(0xaa, SYSCON_SWLOCK); + outl(inl(SYSCON_DEVCFG) & ~SYSCON_DEVCFG_EXVC, SYSCON_DEVCFG); + calc_clk = epinfo.refresh; + act_clk = ep93xx_set_video_div( calc_clk ); + if ( act_clk == -1 ) + return -ENODEV; + + epinfo.refresh = act_clk; + epinfo.pixclock = 1000000000 / (act_clk / 1000); + } + else { + outl(0xaa, SYSCON_SWLOCK); + outl(0, SYSCON_VIDDIV); + outl(0xaa, SYSCON_SWLOCK); + outl(inl(SYSCON_DEVCFG) | SYSCON_DEVCFG_EXVC, SYSCON_DEVCFG); + } + + return 0; +} + + +static void ep93xxfb_get_par(struct fb_info *info) +{ + + DPRINTK("ep93xxfb_get_par - enter\n"); + epinfo.configure = NULL; + epinfo.on = NULL; + epinfo.off = NULL; + + switch( vout ) { + case LCD_OUT: + epinfo.on = philips_lb064v02_on; + epinfo.off = philips_lb064v02_off; + + case CRT_OUT: + epinfo.xres = ep93xxfb_vmods[vmode].hres; + epinfo.xsync = ep93xxfb_vmods[vmode].hsync; + epinfo.xfp = ep93xxfb_vmods[vmode].hfp; + epinfo.xbp = ep93xxfb_vmods[vmode].hbp; + epinfo.xtotal = epinfo.xres + epinfo.xsync + + epinfo.xfp + epinfo.xbp; + + epinfo.yres = ep93xxfb_vmods[vmode].vres; + epinfo.ysync = ep93xxfb_vmods[vmode].vsync; + epinfo.yfp = ep93xxfb_vmods[vmode].vfp; + epinfo.ybp = ep93xxfb_vmods[vmode].vbp; + epinfo.ytotal = epinfo.yres + epinfo.ysync + + epinfo.yfp + epinfo.ybp; + + epinfo.refresh = ep93xxfb_vmods[vmode].refresh; + epinfo.refresh = epinfo.xtotal * epinfo.ytotal * epinfo.refresh; + epinfo.pixclock = 1000000000 / ( epinfo.refresh / 1000); + epinfo.bpp = depth; + + epinfo.clk_src = ep93xxfb_vmods[vmode].clk_src; + epinfo.clk_edge = ep93xxfb_vmods[vmode].clk_edge; + epinfo.pol_blank = ep93xxfb_vmods[vmode].pol_blank; + epinfo.pol_xsync = ep93xxfb_vmods[vmode].pol_hsync; + epinfo.pol_ysync = ep93xxfb_vmods[vmode].pol_vsync; + break; + + case TV_OUT: + epinfo.xres = cxmods[vmode].hres; + epinfo.xsync = 4; + epinfo.xbp = cxmods[vmode].hblank; + epinfo.xfp = cxmods[vmode].hclktotal - epinfo.xbp - + cxmods[vmode].hres - 4; + epinfo.xtotal = cxmods[vmode].hclktotal; + + epinfo.yres = cxmods[vmode].vres; + epinfo.ysync = 2; + epinfo.ybp = cxmods[vmode].vblank; + epinfo.yfp = cxmods[vmode].vclktotal - epinfo.ybp - + cxmods[vmode].vres - 2; + epinfo.ytotal = cxmods[vmode].vclktotal; + epinfo.bpp = depth; + + epinfo.clk_src = CLK_EXTERNAL; + epinfo.automods = cxmods[vmode].automode; + epinfo.clk_edge = EDGE_FALLING; + epinfo.pol_blank = POL_LOW; + epinfo.pol_xsync = POL_LOW, + epinfo.pol_ysync = POL_LOW; + + epinfo.refresh = cxmods[vmode].clkfrequency ; + epinfo.pixclock = 1000000000 / ( epinfo.refresh / 1000); + + epinfo.configure = cx25871_config; + epinfo.on = cx25871_on; + epinfo.off = cx25871_off; + break; + } +} + +static int ep93xxfb_alloc_videomem(void) +{ + unsigned long adr,size,pgsize; + int order; + + DPRINTK("ep93xxfb_alloc_videomem - enter \n"); + + epinfo.fb_log = NULL; + epinfo.fb_size = PAGE_ALIGN( MAX_FBMEM_SIZE ); + order = get_order( epinfo.fb_size ); + order = ( ( (1 << order)*PAGE_SIZE ) < epinfo.fb_size ) ? (order+1) : order; + epinfo.fb_log = (void*) __get_free_pages( GFP_KERNEL, order ); + + if (epinfo.fb_log) { + epinfo.fb_phys = __virt_to_phys((int) epinfo.fb_log ); +/** + adr = (unsigned long)epinfo.fb_log; + size = epinfo.fb_size; + pgsize = 1 << order; + do { + adr += pgsize; + SetPageReserved(virt_to_page(adr)); + } while(size -= pgsize); +**/ + } + else + return -ENOMEM; + memset(epinfo.fb_log,0x00,epinfo.fb_size); + DPRINTK(" fb_log_addres = 0x%x\n",epinfo.fb_log); + DPRINTK(" fb_phys_address = 0x%x\n",epinfo.fb_phys); + DPRINTK(" fb_size = %lu\n",epinfo.fb_size); + DPRINTK(" fb_page_order = %d\n",order); + + DPRINTK("ep93xxfb_alloc_videomem - exit \n"); + return 0; +} + +static void ep93xxfb_release_videomem(void) +{ + unsigned long adr,size,psize; + int order; + + DPRINTK("ep93xxfb_release_videomem - enter \n"); + if (epinfo.fb_log) { + order = get_order(epinfo.fb_size); + adr = (unsigned long)epinfo.fb_log; + size = epinfo.fb_size; + psize = 1 << order ; + do { + adr += psize; + ClearPageReserved(virt_to_page(adr)); + } while(size -= psize); + free_pages((unsigned long)epinfo.fb_log, order ); + } + DPRINTK("ep93xxfb_release_videomem - exit \n"); +} + +static void ep93xxfb_setinfo(struct fb_info *info) +{ + + info->pseudo_palette = pseudo_palette; + info->var.xres = epinfo.xres; + info->var.yres = epinfo.yres; + info->var.xres_virtual = epinfo.xres; + info->var.yres_virtual = epinfo.yres; + + ep93xxfb_setcol( info, depth ); + + info->var.activate = FB_ACTIVATE_NOW; + info->var.left_margin = epinfo.xbp; + info->var.right_margin = epinfo.xfp; + info->var.upper_margin = epinfo.ybp; + info->var.lower_margin = epinfo.yfp; + info->var.hsync_len = epinfo.xsync; + info->var.vsync_len = epinfo.ysync; + + if( epinfo.pol_xsync == POL_HIGH ) + info->var.sync |= FB_SYNC_HOR_HIGH_ACT; + if( epinfo.pol_ysync == POL_HIGH ) + info->var.sync |= FB_SYNC_VERT_HIGH_ACT; + + info->var.vmode = FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP; + info->fix.smem_start = epinfo.fb_phys; + info->fix.smem_len = epinfo.fb_size; + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.line_length = epinfo.xres * (epinfo.bpp / 8); + info->screen_base = epinfo.fb_log; + info->var.pixclock = epinfo.pixclock; + info->fix.ypanstep = 1; + info->fix.ywrapstep = 1; + +} + +static int ep93xxfb_config(struct fb_info *info) +{ + unsigned long attribs; + + DPRINTK("ep93xxfb_config - enter\n"); + + ep93xxfb_get_par( info ); + if( ep93xxfb_alloc_videomem() != 0 ) { + printk("Unable to allocate video memory\n"); + return -ENOMEM; + } + + if( ep93xxfb_setclk() != 0 ) { + printk("Unable to set pixel clock\n"); + ep93xxfb_release_videomem(); + return -ENODEV; + } + + SysconSetLocked(SYSCON_DEVCFG, inl(SYSCON_DEVCFG) | SYSCON_DEVCFG_RasOnP3); + ep93xxfb_timing_signal_generation(); + + /* set video memory parameters */ + outl(epinfo.fb_phys, VIDSCRNPAGE); + outl(epinfo.yres , SCRNLINES); + outl(((epinfo.xres * epinfo.bpp) / 32) - 1, LINELENGTH); + outl((epinfo.xres * epinfo.bpp) / 32, VLINESTEP); + + + /* set pixel mode */ + ep93xxfb_pixelmod(depth); + + attribs = 0; + +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + if(epinfo.clk_edge == EDGE_RISING) + attribs |= VIDEOATTRIBS_INVCLK; + if(epinfo.pol_blank == POL_HIGH) + attribs |= VIDEOATTRIBS_BLKPOL; + if(epinfo.pol_xsync == POL_HIGH) + attribs |= VIDEOATTRIBS_HSPOL; + if(epinfo.pol_ysync == POL_HIGH) + attribs |= VIDEOATTRIBS_VCPOL; + + ep93xxfb_outl(attribs, VIDEOATTRIBS); + ep93xxfb_setinfo( info ); + + if(epinfo.configure) + (epinfo.configure)( epinfo.automods ); + + ep93xxfb_blank( 0 , info ); + + DPRINTK("ep93xxfb_config - exit\n"); + return 0; +} + +int ep93xxfb_ioctl(struct fb_info *info,unsigned int cmd, unsigned long arg) +{ + struct fb_fillrect fill; + struct fb_copyarea cparea; + struct fb_image img; + struct ep93xx_line line; + struct ep93xx_cursor cursor; + unsigned long copy_ret = 0; + + switch (cmd) { + case FBIO_EP93XX_CURSOR: + copy_ret = copy_from_user(&cursor, (void *)arg, sizeof(struct ep93xx_cursor)); + ep93xxfb_cursor(info,&cursor); + break; + case FBIO_EP93XX_LINE: + copy_ret = copy_from_user(&line, (void *)arg, sizeof(struct ep93xx_line)); + ep93xxfb_line(info,&line); + break; + case FBIO_EP93XX_FILL: + copy_ret = copy_from_user(&fill, (void *)arg, sizeof(struct fb_fillrect)); + ep93xxfb_fillrect(info,&fill); + break; + case FBIO_EP93XX_BLIT: + copy_ret = copy_from_user(&img, (void *)arg, sizeof(struct fb_image)); + ep93xxfb_imageblit(info, &img); + break; + case FBIO_EP93XX_COPY: + copy_ret = copy_from_user(&cparea, (void *)arg, sizeof(struct fb_copyarea)); + ep93xxfb_copyarea(info,&cparea); + break; + default: + return -EFAULT; + } + if (copy_ret != 0) + return -1; + else + return 0; +} + + +static struct fb_ops ep93xxfb_ops = { + .owner = THIS_MODULE, + .fb_setcolreg = ep93xxfb_setcolreg, + .fb_check_var = ep93xxfb_check_var, + .fb_set_par = ep93xxfb_set_par, + .fb_blank = ep93xxfb_blank, + .fb_pan_display = ep93xx_pan_display, + .fb_fillrect = ep93xxfb_fillrect, + .fb_copyarea = ep93xxfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_cursor = ep93xxfb_cursor, + .fb_ioctl = ep93xxfb_ioctl, + .fb_mmap = ep93xxfb_mmap, +}; + + +static struct resource ep93xxfb_raster_resources = { + .start = EP93XX_RASTER_PHYS_BASE, + .end = EP93XX_RASTER_PHYS_BASE + 0x1ffff, + .flags = IORESOURCE_MEM, +}; + + +static int __init ep93xxfb_probe(struct platform_device *device) +{ + struct fb_info *info = NULL; + struct resource *res = NULL; + int ret = 0; + int arb = 0; + + DPRINTK("ep93xxfb_probe - enter \n"); + + + if(!device) { + printk("error : to_platform_device\n"); + return -ENODEV; + } + res = platform_get_resource( device, IORESOURCE_MEM, 0); + if(!res) { + printk("error : platform_get_resource \n"); + return -ENODEV; + } + cursor_data = kmalloc( 64 * 64 * 2, GFP_KERNEL ); + memset( cursor_data, 0x00, 64 * 64 * 2 ); + if(!cursor_data) { + printk("Unable to allocate memory for hw_cursor\n"); + return -ENOMEM; + } + if (!request_mem_region(res->start,res->end - res->start + 1, FBDEV_NAME )) + return -EBUSY; + + info = framebuffer_alloc(sizeof(u32) * 256, &device->dev); + + if(!info) { + printk("Unable to allocate memory for frame buffer\n"); + return -ENOMEM; + } + + info->flags = FBINFO_DEFAULT; + strncpy(info->fix.id, FBDEV_NAME, sizeof(info->fix.id)); + info->fix.mmio_start = res->start; + info->fix.mmio_len = res->end - res->start + 1; + info->fbops = &ep93xxfb_ops; + info->pseudo_palette = info->par; + info->state = FBINFO_STATE_RUNNING; + + if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { + ret = -ENOMEM; + goto fbuff; + } + + if ((ret = ep93xxfb_config(info)) < 0) + goto clmap; + + if (register_framebuffer(info) < 0) { + printk(KERN_ERR "Unable to register ep93xxfb frame buffer\n"); + ret = -EINVAL; + goto clmap; + } + platform_set_drvdata(device, info); + printk(KERN_INFO "fb%d: EP93xx frame buffer at %dx%dx%dbpp\n", info->node, + info->var.xres, info->var.yres, info->var.bits_per_pixel); + + register_reboot_notifier(&cx25871_notifier); + + /*change the raster arb to the highest one--Bo*/ + arb = inl(SYSCON_BMAR); + arb = (arb & 0x3f8) | 0x01; + outl(arb,SYSCON_BMAR); + + DPRINTK("ep93xxfb_probe - exit \n"); + return 0; + +clmap: + fb_dealloc_cmap(&info->cmap); + +fbuff: + framebuffer_release(info); + return ret; +} + +static int ep93xxfb_remove(struct platform_device *device) +{ + struct resource *res; + struct fb_info *info; + struct ep93xx_cursor cursor; + + DPRINTK("ep93xxfb_remove - enter \n"); + + info = platform_get_drvdata(device); + + ep93xxfb_release_videomem(); + + res = platform_get_resource( device, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + + platform_set_drvdata(device, NULL); + unregister_framebuffer(info); + + fb_dealloc_cmap(&info->cmap); + framebuffer_release(info); + + cursor.flags = CURSOR_OFF; + ep93xxfb_cursor(info,&cursor); + if(cursor_data!=NULL) + kfree(cursor_data); + + unregister_reboot_notifier(&cx25871_notifier); + ep93xxfb_blank( 1, info ); + + DPRINTK("ep93xxfb_remove - exit \n"); + return 0; +} + +static void ep93xxfb_platform_release(struct device *device) +{ + DPRINTK("ep93xxfb_platform_release - enter\n"); +} + +static int ep93xxfb_check_param(void) +{ + + switch(vout) { + case CRT_OUT: + if( vmode >=(sizeof(ep93xxfb_vmods)/sizeof(ep93xxfb_vmods[0]))){ + vmode = 1; + depth = DEFAULT_BPP; + return 0; + } + break; + case LCD_OUT: + DPRINTK("ep93xxfb_check_param: LCD_OUT\n"); + if(depth != 16) { + DPRINTK("ep93xxfb_check_param: vmode = %d, depth = %d\n", vmode, depth); + //vmode = 0; /* Not true anymore, could be the QVGA or PrimeView -- TAS */ + depth = DEFAULT_BPP; + return 0; + } + break; + case TV_OUT: + if( vmode >= CXMODES_COUNT ) { + vmode = DEFAULT_MODE; + depth = DEFAULT_BPP; + return 0; + } + break; + default: + vmode = DEFAULT_MODE; + depth = DEFAULT_BPP; + vout = DEFAULT_OUT; + return 0; + break; + } + + if(!((depth == 8) || (depth == 16) || (depth == 24) || (depth == 32))) + depth = DEFAULT_BPP; + + return 1; +} + +int __init ep93xxfb_setup(char *options) +{ + char *opt; + + DPRINTK("ep93xxfb_setup - %s\n",options); + + if (!options || !*options) + return 0; + + while ((opt = strsep(&options, ",")) != NULL) { + if (!strncmp(opt, "vout=", 5)) + vout = simple_strtoul(opt + 5, NULL, 0); + else if (!strncmp(opt, "vmode=", 6)) + vmode = simple_strtoul(opt + 6, NULL, 0); + else if (!strncmp(opt, "depth=", 6)) + depth = simple_strtoul(opt + 6, NULL, 0); + } + ep93xxfb_check_param(); + return 0; +} + + +static struct platform_driver ep93xxfb_driver = { + .probe = ep93xxfb_probe, + .remove = ep93xxfb_remove, + .driver = { + .name = FBDEV_NAME, + }, +}; + +static struct platform_device ep93xxfb_device = { + .name = FBDEV_NAME, + .id = -1, + .dev = { + .release = ep93xxfb_platform_release, + }, + .num_resources = 1, + .resource = &ep93xxfb_raster_resources, +}; + +int __init ep93xxfb_init(void) +{ + int ret = 0; + char *option = NULL; + + DPRINTK("ep93xxfb_init - enter\n"); + + if (fb_get_options("ep93xxfb", &option)) + return -ENODEV; + ep93xxfb_setup(option); + + + if( !ep93xxfb_check_param() ) { + printk("Unsupported format \n"); + return -1; + } + + ret = platform_driver_register(&ep93xxfb_driver); + + if (!ret) { + ret = platform_device_register(&ep93xxfb_device); + if (ret) + platform_driver_unregister(&ep93xxfb_driver); + } + outl(0x00000000, BLOCKCTRL); + request_irq(IRQ_EP93XX_GRAPHICS, ep93xxfb_irq_handler, SA_INTERRUPT, + "graphics",NULL); + + DPRINTK("ep93xxfb_init - exit\n"); + return ret; +} + + + +static void __exit ep93xxfb_exit(void) +{ + DPRINTK("ep93xxfb_exit - enter\n"); + platform_driver_unregister(&ep93xxfb_driver); + platform_device_unregister(&ep93xxfb_device); + DPRINTK("ep93xxfb_exit - exit\n"); +} + +module_init(ep93xxfb_init); +module_exit(ep93xxfb_exit); + + +module_param( vmode, int, 1); +MODULE_PARM_DESC(vmode, "Specify the video mode number that should be used"); +module_param( vout , int , 0 ); +MODULE_PARM_DESC(vout ,"Specify video output (0 = CRT ,1 = LCD , 2 = TV)"); +module_param( depth , int, 16); +MODULE_PARM_DESC(depth ,"Color depth (8,16,24,32)"); +MODULE_LICENSE("GPL"); diff -urN -x CVS linux-2.6.20/drivers/video/ep93xxfb.c.orig linux-2.6.20-AT91/drivers/video/ep93xxfb.c.orig --- linux-2.6.20/drivers/video/ep93xxfb.c.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/ep93xxfb.c.orig 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,1788 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ep93xxfb.h" +#include "cx25871.h" +#include +#include + +extern int pls_proba; + +#define DEBUG 1 +#ifdef DEBUG +#define DPRINTK( fmt, arg... ) printk( fmt, ##arg ) +#else +#define DPRINTK( fmt, arg... ) +#endif + +#define FBDEV_NAME "ep93xxfb" + +#define ep93xxfb_outl(value, reg) \ +{ \ + outl(RASTER_SWLOCK_VALUE, RASTER_SWLOCK); \ + outl(value, reg); \ +} + +#if defined(CONFIG_FB_EP93XX_CRT) +#define DEFAULT_MODE 1 +#define DEFAULT_OUT CRT_OUT +#elif defined(CONFIG_FB_EP93XX_LCD) +#define DEFAULT_MODE 0 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_LCDWS) /* Wide screen */ +#define DEFAULT_MODE 17 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_QVGA) /* QVGA */ +#define DEFAULT_MODE 16 +#define DEFAULT_OUT LCD_OUT +#elif defined(CONFIG_FB_EP93XX_PAL) +#define DEFAULT_MODE 12 +#define DEFAULT_OUT TV_OUT +#elif defined(CONFIG_FB_EP93XX_NTSC) +#define DEFAULT_MODE 0 +#define DEFAULT_OUT TV_OUT +#else +#define DEFAULT_MODE 0 +#define DEFAULT_OUT LCD_OUT +#endif + +#if defined(CONFIG_FB_EP93XX_8BPP) +#define DEFAULT_BPP 8 +#elif defined(CONFIG_FB_EP93XX_16BPP) +#define DEFAULT_BPP 16 +#else +#define DEFAULT_BPP 16 +#endif + +static DECLARE_WAIT_QUEUE_HEAD(ep93xxfb_wait_in); + +static unsigned int pseudo_palette[256]; +static unsigned long *cursor_data = NULL; +static struct ep93xxfb_info epinfo; + +static int vout = DEFAULT_OUT; +static int vmode = DEFAULT_MODE; +static int depth = DEFAULT_BPP; + +static int ep93xxfb_setcol(struct fb_info *info, int bpp); + +struct cx25871_vmodes cxmods[CXMODES_COUNT]= +{ + + { "CX25871-NTSC", 0x10, 640, 400, 936, 525, 259, 76, 29454552 }, // 0 + { "CX25871-NTSC", 0x00, 640, 480, 784, 600, 126, 75, 28195793 }, // 1 + { "CX25871-NTSC", 0x40, 640, 480, 770, 645, 113, 100, 29769241 }, // 2 + { "CX25871-NTSC", 0x30, 720, 400, 1053, 525, 291, 76, 33136345 }, // 3 + { "CX25871-NTSC", 0x54, 720, 480, 880, 525, 140, 36, 27692310 }, // 4 + { "CX25871-NTSC", 0x02, 800, 600, 880, 735, 66, 86, 38769241 }, // 5 + { "CX25871-NTSC", 0x22, 800, 600, 1176, 750, 329, 94, 52867138 }, // 6 + { "CX25871-NTSC", 0x42, 800, 600, 1170, 805, 323, 125, 56454552 }, // 7 + { "CX25871-NTSC", 0x50, 800, 600, 1170, 770, 323, 105, 54000000 }, // 8 + { "CX25871-NTSC", 0x12, 1024, 768, 1176, 975, 133, 130,68727276 }, // 9 + { "CX25871-NTSC", 0x32, 1024, 768, 1170, 945, 127, 115, 66272724 }, // 10 + { "CX25871-NTSC", 0x52, 1024, 768, 1170, 1015, 127, 150, 71181793 },// 11 + + { "CX25871-PAL", 0x11, 640, 400, 1160, 500, 363, 64, 28999992 }, // 12 + { "CX25871-PAL", 0x01, 640, 480, 944, 625, 266, 90, 29500008 }, // 13 + { "CX25871-PAL", 0x21, 640, 480, 950, 600, 271,76 , 28500011 }, // 14 + { "CX25871-PAL", 0x41, 640, 480, 950, 650, 271, 104, 30875015 }, // 15 + { "CX25871-PAL-M", 0x56, 640, 480, 784, 600, 126, 75, 28195793 }, // 16 + { "CX25871-PAL-Nc", 0x57, 640, 480, 944, 625, 266, 90, 29500008 }, // 17 + { "CX25871-PAL", 0x31, 720, 400, 1305, 500, 411, 64, 32625000 }, // 18 + { "CX25871-PAL", 0x03, 800, 600, 960, 750, 140, 95, 36000000 }, // 19 + { "CX25871-PAL", 0x23, 800, 600, 950, 775, 131, 109, 36812508 }, // 20 + { "CX25871-PAL", 0x43, 800, 600, 950, 800, 131, 122, 37999992 }, // 21 + { "CX25871-PAL", 0x13, 1024, 768, 1400, 975, 329, 131, 68249989 }, // 22 + { "CX25871-PAL", 0x53, 1024, 768, 1410, 1000, 337, 147, 70499989 },// 23 + +}; + +static int cx25871_reboot(struct notifier_block *this, unsigned long event, void *x) +{ + switch (event) + { + case SYS_HALT: + case SYS_POWER_OFF: + case SYS_RESTART: + write_reg(0xba, 0x80); + default: + return NOTIFY_DONE; + } +} + +static struct notifier_block cx25871_notifier = +{ + cx25871_reboot, + NULL, + 5 +}; + + +int write_reg(unsigned char ucRegAddr, unsigned char ucRegValue) +{ + unsigned long uiVal, uiDDR; + unsigned char ucData, ucIdx, ucBit; + unsigned long ulTimeout; + + uiVal = inl(GPIO_PGDR); + uiDDR = inl(GPIO_PGDDR); + uiVal |= (GPIOG_EEDAT | GPIOG_EECLK); + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiDDR |= (GPIOG_EEDAT | GPIOG_EECLK); + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + uiVal &= ~GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal &= ~GPIOG_EECLK; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + + for (ucIdx = 0; ucIdx < 3; ucIdx++) { + if (ucIdx == 0) + ucData = (unsigned char)CX25871_DEV_ADDRESS; + else if (ucIdx == 1) + ucData = ucRegAddr; + else + ucData = ucRegValue; + + for (ucBit = 0; ucBit < 8; ucBit++) { + if (ucData & 0x80) + uiVal |= GPIOG_EEDAT; + else + uiVal &= ~GPIOG_EEDAT; + + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + outl( (uiVal | GPIOG_EECLK), GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + ucData <<= 1; + } + + uiDDR &= ~GPIOG_EEDAT; + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + outl( (uiVal | GPIOG_EECLK), GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + ulTimeout = 0; + while ( inl(GPIO_PGDR) & GPIOG_EEDAT ) { + udelay( EE_DELAY_USEC ); + ulTimeout++; + if (ulTimeout > EE_READ_TIMEOUT ) + return 1; + } + + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiDDR |= GPIOG_EEDAT; + outl( uiDDR, GPIO_PGDDR ); + udelay( EE_DELAY_USEC ); + } + + uiVal &= ~GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal |= GPIOG_EECLK; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + uiVal |= GPIOG_EEDAT; + outl( uiVal, GPIO_PGDR ); + udelay( EE_DELAY_USEC ); + return 0; +} + +void cx25871_on( unsigned char value ) +{ + write_reg(0x30,0x00); + write_reg(0xBA, 0x20 ); +} + +void cx25871_off( unsigned char value ) +{ + write_reg(0xBA, 0x30); + write_reg(0xC4, 0x00); + write_reg(0x30, 0x02); +} + +void cx25871_config( unsigned char value ) +{ + write_reg(0xBA, CX25871_REGxBA_SRESET); + mdelay(1); + write_reg(0xB8, value); + write_reg(0xBA, CX25871_REGxBA_SLAVER | CX25871_REGxBA_DACOFF); + write_reg(0xC6,(CX25871_REGxC6_INMODE_MASK & 0x3)); + write_reg(0xC4, CX25871_REGxC4_EN_OUT); + write_reg(0xBA, CX25871_REGxBA_SLAVER ); +} + +static struct ep93xxfb_videomodes ep93xxfb_vmods[] = { + { // 0 + "Philips-LB064V02-640x480x60", + 640, 24, 96, 40, 480, 10, 2, 33, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 1 + "CRT-640x480-60", + 640, 24, 96, 40, 480, 11, 2, 32, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 2 + "CRT-640x480-72", + 640, 40, 40, 144, 480, 8, 3, 30, 72, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 3 + "CRT-640x480-75", + 640, 16, 76, 120, 480, 1, 3, 16, 75, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 4 + "CRT-640x480-85", + 640, 56, 56, 80, 480, 1, 3, 25, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 5 + "CTR-640x480-100", + 640, 32, 96, 96, 480, 8, 6, 36, 100, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 6 + "CRT-800x600-56", + 800, 24, 72, 128, 600, 1, 2, 22, 56, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 7 + "CRT-800x600-60", + 800, 40, 128, 88, 600, 1, 4, 23, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 8 + "CRT-800x600-72", + 800, 56, 120, 64, 600, 37, 6, 23, 72, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 9 + "CRT-800x600-85", + 800, 64, 64, 160, 600, 16, 5, 36, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 10 + "CRT-800x600-100", + 800, 64, 64, 160, 600, 4, 6, 30, 100, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 11 + "CRT-1024x768-60", + 1024, 8, 144, 168, 768, 3, 6, 29, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 12 + "CRT-1024x768-70", + 1024, 24, 136, 144, 768, 3, 6, 29, 70, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 13 + "CRT-1024x768-75", + 1024, 16, 96, 176, 768, 1, 3, 28, 75, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 14 + "CRT-1024x768-85", + 1024, 48, 96, 208, 768, 1, 3, 36, 85, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + { // 15 + "CRT-1280x720-60", + 1280, 48, 112, 248, 720, 1, 3, 38, 60, + CLK_INTERNAL, EDGE_RISING, POL_LOW, POL_HIGH, POL_HIGH, + }, + /* Add support for the LB040Q02 QVGA and the Primeview PM070WX2 800x480 LCD */ + /* TAS */ + { // 16 + "LB040Q02-QVGA-320x240", + 320, 25, 30, 25, 240, 6, 7, 10, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + }, + { // 17 + "PM070WX2-800x480", + 800, 24, 96, 40, 480, 10, 2, 33, 60, + CLK_INTERNAL, EDGE_FALLING, POL_LOW, POL_LOW, POL_LOW, + } +}; + +static void philips_lb064v02_on(unsigned char value) +{ + DPRINTK("philips_lb064v02_on \n"); + DPRINTK("GPIO pin is set to %d\n", CONFIG_FB_EP93XX_GPIO); + /* The GPIO line that turns on power to the LCD differs + * depending on the board. This has been moved to the + * Kconfig as an option. Currently, the EDB9315A board + * should use 2, the EMAC Thermatron board uses 1. + */ + /*outl(inl(GPIO_PADDR) | 2, GPIO_PADDR); */ + /*outl(inl(GPIO_PADDR) | 1, GPIO_PADDR); */ + outl(inl(GPIO_PADDR) | CONFIG_FB_EP93XX_GPIO, GPIO_PADDR); + /*outl(inl(GPIO_PADR) | 2, GPIO_PADR); */ + /*outl(inl(GPIO_PADR) | 1, GPIO_PADR); */ + outl(inl(GPIO_PADDR) | CONFIG_FB_EP93XX_GPIO, GPIO_PADDR); +} + +static void philips_lb064v02_off(unsigned char value) +{ + DPRINTK("philips_lb064v02_off \n"); + outl(inl(GPIO_PADR) & ~2, GPIO_PADR); +} + +static irqreturn_t ep93xxfb_irq_handler(int i, void *blah, struct pt_regs *regs) +{ + outl(0x00000000, BLOCKCTRL); + wake_up(&ep93xxfb_wait_in); + return IRQ_HANDLED; +} + +static void ep93xxfb_wait(void) +{ + DECLARE_WAITQUEUE(wait, current); + add_wait_queue(&ep93xxfb_wait_in, &wait); + set_current_state(TASK_UNINTERRUPTIBLE); + + while (inl(BLOCKCTRL) & 0x00000001){ + if((pls_proba==1)&&(!in_atomic())) + schedule(); + } + + remove_wait_queue(&ep93xxfb_wait_in, &wait); + set_current_state(TASK_RUNNING); + +} + +void ep93xxfb_fillrect(struct fb_info *p, const struct fb_fillrect *fill) +{ + unsigned long blkdestwidth,tmp; + + if (!fill->width || !fill->height || + (fill->dx >= p->var.xres) || + (fill->dy >= p->var.yres) || + ((fill->dx + fill->width - 1) >= p->var.xres) || + ((fill->dy + fill->height - 1) >= p->var.yres)) + return; + + tmp = (( fill->dx + fill->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (fill->dx * epinfo.bpp) / 32; + + outl(fill->color, BLOCKMASK); + outl( ((fill->dx * epinfo.bpp) & 0x1F) | + ((((fill->dx + fill->width - 1) * epinfo.bpp ) & 0x1F) << 16), + DESTPIXELSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH); + outl( blkdestwidth, BLKDESTWIDTH ); + outl(fill->height - 1, BLKDESTHEIGHT); + outl((epinfo.fb_phys + (fill->dy * epinfo.xres * epinfo.bpp ) / 8 + + (fill->dx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( epinfo.pixformat | 0x0000000B, BLOCKCTRL); + ep93xxfb_wait(); + +} + +void ep93xxfb_copyarea(struct fb_info *p, const struct fb_copyarea *area) +{ + unsigned long startsx,stopsx,startdx,stopdx,startsy,startdy; + unsigned long blksrcwidth,blkdestwidth,tmp; + unsigned long val = 0; + + if( !area->width || !area->width || + (area->sx >= p->var.xres) || (area->sy >= p->var.yres) || + (area->dx >= p->var.xres) || (area->dy >= p->var.yres) || + ((area->dx + area->width - 1) >= p->var.xres) || + ((area->dy + area->height - 1) >= p->var.yres)) + return; + + if(area->sx == area->dx && area->sy == area->dy) + return; + + if ((area->dy == area->sy) && (area->dx > area->sx) && + (area->dx < (area->sx + area->width - 1))) { + startdx = area->dx + area->width - 1; + stopdx = area->dx; + startsx = area->sx + area->width - 1; + stopsx = area->sx; + val |= 0x000000A0; + } + else { + startdx = area->dx; + stopdx = area->dx + area->width - 1; + startsx = area->sx; + stopsx = area->sx + area->width - 1; + } + + if (area->dy <= area->sy) { + startdy = area->dy; + startsy = area->sy; + } + else { + startdy = area->dy + area->height -1; + startsy = area->sy + area->height -1; + val |= 0x00000140; + } + + tmp = (( area->sx + area->width ) * epinfo.bpp ); + blksrcwidth = tmp / 32; + if(blksrcwidth > 0 && (tmp % 32 == 0)) + blksrcwidth--; + blksrcwidth = blksrcwidth - (area->sx * epinfo.bpp) / 32; + + tmp = (( area->dx + area->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (area->dx * epinfo.bpp) / 32; + + outl( 0x00000000 , BLOCKCTRL); + + /*** src ***/ + outl((((startsx * epinfo.bpp) & 0x1F) | + (((stopsx * epinfo.bpp ) & 0x1F) << 16)) + , SRCPIXELSTRT); + outl((epinfo.fb_phys + (startsy * epinfo.xres * epinfo.bpp ) / 8 + + (startsx * epinfo.bpp ) / 8 ) + , BLKSRCSTRT); + outl(((epinfo.xres * epinfo.bpp) / 32), SRCLINELENGTH); + outl( blksrcwidth, BLKSRCWIDTH ); + + /*** dest ***/ + outl((((startdx * epinfo.bpp) & 0x1F) | + (((stopdx * epinfo.bpp ) & 0x1F) << 16)) + , DESTPIXELSTRT); + outl((epinfo.fb_phys + (startdy * epinfo.xres * epinfo.bpp ) / 8 + + (startdx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH); + outl( blkdestwidth, BLKDESTWIDTH); + outl( area->height - 1 , BLKDESTHEIGHT); + outl( epinfo.pixformat | val | 0x00000003, BLOCKCTRL); + ep93xxfb_wait(); +} + +void ep93xxfb_imageblit(struct fb_info *p, const struct fb_image *image) +{ +// unsigned long blkdestwidth,tmp; +// void * pucBlitBuf; + cfb_imageblit( p , image ); + return; +/* + if ((image->dx >= p->var.xres) || + (image->dy >= p->var.yres) || + ((image->dx + image->width - 1) >= p->var.xres) || + ((image->dy + image->height - 1) >= p->var.yres)) + return; + if (epinfo.bpp != image->depth ) + return; + + tmp = (( image->dx + image->width ) * epinfo.bpp ); + blkdestwidth = tmp / 32; + if(blkdestwidth > 0 && (tmp % 32 == 0)) + blkdestwidth--; + blkdestwidth = blkdestwidth - (image->dx * epinfo.bpp) / 32; + + pucBlitBuf = kmalloc(1024*8,GFP_KERNEL); + copy_from_user(pucBlitBuf, image->data, 5000); + + outl( 0x00000000 , BLOCKCTRL); + + outl( 0x00000000, SRCPIXELSTRT); + outl( virt_to_phys(pucBlitBuf), BLKSRCSTRT); + outl( (image->width * epinfo.bpp) / 32 , SRCLINELENGTH); + outl(((image->width - 1) * epinfo.bpp) / 32, BLKSRCWIDTH ); + + outl(((image->dx * epinfo.bpp) & 0x1F) | + ((((image->dx + image->width - 1) * epinfo.bpp ) & 0x1F) << 16) + , DESTPIXELSTRT); + outl((epinfo.fb_phys + (image->dy * epinfo.xres * epinfo.bpp ) / 8 + + (image->dx * epinfo.bpp ) / 8 ) + , BLKDSTSTRT); + outl( ((epinfo.xres * epinfo.bpp) / 32), DESTLINELENGTH ); + outl( blkdestwidth, BLKDESTWIDTH ); + outl( image->height - 1 , BLKDESTHEIGHT); + outl(image->fg_color, BLOCKMASK); + outl(image->bg_color, BACKGROUND); + outl( epinfo.pixformat | 0x00000003, BLOCKCTRL ); + ep93xxfb_wait(); +*/ +} + + +static unsigned long isqrt(unsigned long a) +{ + unsigned long rem = 0; + unsigned long root = 0; + int i; + + for (i = 0; i < 16; i++) { + root <<= 1; + rem = ((rem << 2) + (a >> 30)); + a <<= 2; + root++; + if (root <= rem) { + rem -= root; + root++; + } + else + root--; + } + return root >> 1; +} + +int ep93xxfb_line(struct fb_info *info, struct ep93xx_line *line) +{ + unsigned long value = 0; + long x, y, dx, dy, count, xinc, yinc, xval, yval, incr; + + if ((line->x1 > info->var.xres) || + (line->x2 > info->var.xres) || + (line->y1 > info->var.yres) || + (line->y2 > info->var.yres)) + return -EFAULT; + x = line->x1; + y = line->y1; + dx = line->x2 - line->x1; + dy = line->y2 - line->y1; + + if ( !dx || !dy ) + return -EFAULT; + + if ( dx < 0 && dy < 0 ) { + x = line->x2; + y = line->y2; + dx *= -1; + dy *= -1; + } + else if ( dx < 0 && dy > 0 ){ + dx *= -1; + value = 0x000000A0; + } + else if( dy < 0 && dx > 0 ){ + dy *= -1; + value = 0x00000140; + } + + if (line->flags & LINE_PRECISE) { + count = isqrt(((dy * dy) + (dx * dx)) * 4096); + xinc = (4095 * 64 * dx) / count; + yinc = (4095 * 64 * dy) / count; + xval = 2048; + yval = 2048; + count = 0; + while (dx || dy) { + incr = 0; + xval -= xinc; + if (xval <= 0) { + xval += 4096; + dx--; + incr = 1; + } + yval -= yinc; + if (yval <= 0) { + yval += 4096; + dy--; + incr = 1; + } + count += incr; + } + } + else { + if ( dx == dy ) { + xinc = 4095; + yinc = 4095; + count = dx; + + } + else if ( dx < dy ) { + xinc = ( dx * 4095 ) / dy; + yinc = 4095; + count = dy; + + } + else { + xinc = 4095; + yinc = ( dy * 4095 ) / dx; + count = dx; + } + } + + outl(0x08000800, LINEINIT); + if (line->flags & LINE_PATTERN) + outl(line->pattern, LINEPATTRN); + else + outl(0x000fffff, LINEPATTRN); + outl(epinfo.fb_phys + ((y * epinfo.xres * epinfo.bpp) / 8) + + ((x * epinfo.bpp ) / 8 ), BLKDSTSTRT); + + outl(((x * epinfo.bpp) & 0x1F) | + ((((x + dx - 1) * epinfo.bpp) & 0x1F ) << 16), + DESTPIXELSTRT); + outl((epinfo.xres * epinfo.bpp) / 32, DESTLINELENGTH); + outl(line->fgcolor, BLOCKMASK); + outl(line->bgcolor, BACKGROUND); + outl((yinc << 16) | xinc, LINEINC); + outl( count & 0xFFF, BLKDESTWIDTH); + outl( 0 , BLKDESTHEIGHT); + value |= (line->flags & LINE_BACKGROUND) ? 0x00004000 : 0; + outl(epinfo.pixformat | value | 0x00000013, BLOCKCTRL); + ep93xxfb_wait(); + return 0; +} + + +int ep93xxfb_cursor(struct fb_info *info, struct ep93xx_cursor *cursor) +{ + unsigned long x,y,save,copy_ret; + copy_ret = 0; + + if (cursor->width > 64 || cursor->height > 64) + return -ENXIO; + + if (cursor->flags & CURSOR_OFF) + outl(inl(CURSORXYLOC) & ~0x00008000, CURSORXYLOC); + + if (cursor->flags & CURSOR_SETSHAPE) { + copy_ret = copy_from_user(cursor_data, cursor->data, + cursor->width * cursor->height / 4); + save = inl(CURSORXYLOC); + outl(save & ~0x00008000, CURSORXYLOC); + + outl(virt_to_phys(cursor_data), CURSOR_ADR_START); + outl(virt_to_phys(cursor_data), CURSOR_ADR_RESET); + outl(((cursor->width - 1) & 0x30) << 4 | ((cursor->height - 1) << 2) | + ((cursor->width - 1) >> 4), CURSORSIZE); + outl(save, CURSORXYLOC); + + } + + if (cursor->flags & CURSOR_SETCOLOR) { + outl(cursor->color1, CURSORCOLOR1); + outl(cursor->color2, CURSORCOLOR2); + outl(cursor->blinkcolor1, CURSORBLINK1); + outl(cursor->blinkcolor2, CURSORBLINK2); + } + + if (cursor->flags & CURSOR_BLINK) { + if (cursor->blinkrate) + outl(0x00000100 | cursor->blinkrate, CURSORBLINK); + else + outl(0x0000000FF, CURSORBLINK); + } + + if (cursor->flags & CURSOR_MOVE) { + x = (inl(HACTIVESTRTSTOP) & 0x000007ff) - cursor->dx - 2; + y = (inl(VACTIVESTRTSTOP) & 0x000007ff) - cursor->dy; + outl((inl(CURSORXYLOC) & 0x8000) | (y << 16) | x, CURSORXYLOC); + } + + if(cursor->flags & CURSOR_ON) + outl(inl(CURSORXYLOC) | 0x00008000, CURSORXYLOC); + if (copy_ret != 0) + return -1; + else + return 0; +} + +static inline void +ep93xxfb_palette_write(u_int regno, u_int red, u_int green, + u_int blue, u_int trans) +{ + unsigned int cont, i, pal; + DPRINTK("ep93xxfb_palette_write - enter\n"); + pal = ((red & 0xFF00) << 8) | (green & 0xFF00) | ((blue & 0xFF00) >> 8); + pseudo_palette[regno] = pal; + outl( pal, ( COLOR_LUT + ( regno << 2 ))); + cont = inl( LUTCONT ); + + if (( cont & LUTCONT_STAT && cont & LUTCONT_RAM1 ) || + ( !( cont & LUTCONT_STAT ) && !( cont&LUTCONT_RAM1 ))) { + for ( i = 0; i < 256; i++ ) { + outl( pseudo_palette[i], ( COLOR_LUT + ( i << 2 )) ); + } + outl( cont ^ LUTCONT_RAM1, LUTCONT ); + } +} + +int ep93xxfb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + +#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) + + switch ( info->fix.visual ) + { + case FB_VISUAL_PSEUDOCOLOR: + ep93xxfb_palette_write(regno, red, green, blue, transp); + break; + case FB_VISUAL_TRUECOLOR: + if (regno >= 16) + return 1; + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + ((u32 *)(info->pseudo_palette))[regno] = + (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + return 0; +} + +static int ep93xx_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + DPRINTK("ep93xx_pan_display - enter\n"); + + if (var->yoffset < 0 + || var->yoffset + var->yres > info->var.yres_virtual + || var->xoffset) + return -EINVAL; + + outl(epinfo.fb_phys + info->fix.line_length * var->yoffset + , VIDSCRNPAGE); + + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + + DPRINTK("ep93xx_pan_display - exit\n"); + return 0; +} + + +static int +ep93xxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct fb_var_screeninfo tmp_var; + unsigned long pclk; + DPRINTK("ep93xxfb_check_var - enter\n"); + + memcpy (&tmp_var, var, sizeof (tmp_var)); + + if( (tmp_var.vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED ) { + DPRINTK(" ep93xxfb_check_var - unsupported video mode\n"); + return -EINVAL; + } + + if( ((tmp_var.xres * tmp_var.yres * tmp_var.bits_per_pixel) / 8) > + MAX_FBMEM_SIZE ) { + DPRINTK(" ep93xxfb_check_var - memory error \n"); + return -ENOMEM; + } + + if( ((tmp_var.xres_virtual * tmp_var.yres_virtual * tmp_var.bits_per_pixel) / 8) > + MAX_FBMEM_SIZE ) { + DPRINTK(" ep93xxfb_check_var - memory error \n"); + return -ENOMEM; + } + + pclk = 1000 * (1000000000 / tmp_var.pixclock); + + if( pclk > ep93xx_get_max_video_clk() ) { + DPRINTK(" ep93xxfb_check_var - pixel clock error %lu\n",pclk); + return -EINVAL; + } + + if (var->xres_virtual != var->xres) + var->xres_virtual = var->xres; + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + + if (var->xoffset < 0) + var->xoffset = 0; + if (var->yoffset < 0) + var->yoffset = 0; + + switch (tmp_var.bits_per_pixel) { + case 8: + break; + case 16: + break; + case 24: + break; + case 32: + break; + default: + return -EINVAL; + } + + DPRINTK("ep93xxfb_check_var - exit\n"); + return 0; +} + + +static int ep93xxfb_set_par(struct fb_info *info) +{ + struct fb_var_screeninfo tmp_var; + unsigned long attribs; + + DPRINTK("ep93xxfb_set_par - enter\n"); + + if( ep93xxfb_check_var(&info->var,info) < 0 ) + return -EINVAL; + + if( !ep93xxfb_setcol(info,info->var.bits_per_pixel) ) + return -EINVAL; + + + info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8; + + ep93xxfb_blank( 1 , info ); + + memcpy(&tmp_var,&info->var,sizeof(tmp_var)); + + epinfo.xres = tmp_var.xres; + epinfo.xsync = tmp_var.hsync_len; + epinfo.xfp = tmp_var.right_margin; + epinfo.xbp = tmp_var.left_margin; + epinfo.xtotal = epinfo.xres + epinfo.xsync + + epinfo.xfp + epinfo.xbp; + + epinfo.yres = tmp_var.yres; + epinfo.ysync = tmp_var.vsync_len; + epinfo.yfp = tmp_var.lower_margin; + epinfo.ybp = tmp_var.upper_margin; + epinfo.ytotal = epinfo.yres + epinfo.ysync + + epinfo.yfp + epinfo.ybp; + + epinfo.pixclock = tmp_var.pixclock ; + epinfo.refresh = 1000 * (1000000000 / tmp_var.pixclock) ; + + if( epinfo.refresh > ep93xx_get_max_video_clk()) + epinfo.refresh = ep93xx_get_max_video_clk(); + epinfo.bpp = tmp_var.bits_per_pixel; + + ep93xxfb_setclk(); + ep93xxfb_timing_signal_generation(); + + // set video memory parameters + outl(epinfo.fb_phys, VIDSCRNPAGE); + outl(epinfo.yres , SCRNLINES); + outl(((epinfo.xres * epinfo.bpp) / 32) - 1, LINELENGTH); + outl((epinfo.xres * epinfo.bpp) / 32, VLINESTEP); + + // set pixel mode + ep93xxfb_pixelmod(epinfo.bpp); + + attribs = 0; +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + /* We can't set the clock here, we don't know anything + * about it yet. This causes the clock to always be + * rising edge, which distorts the image. It is set if + * needed in the ep93xx_config function. -- TAS */ + //attribs |= VIDEOATTRIBS_INVCLK; + if( tmp_var.sync & FB_SYNC_HOR_HIGH_ACT ) + attribs |= VIDEOATTRIBS_HSPOL; + if( tmp_var.sync & FB_SYNC_VERT_HIGH_ACT ) + attribs |= VIDEOATTRIBS_VCPOL; + + ep93xxfb_outl(attribs, VIDEOATTRIBS); + ep93xxfb_blank( 0 , info ); + + DPRINTK("ep93xxfb_set_par - exit\n"); + + return 0; +} + + +static int ep93xxfb_blank(int blank_mode,struct fb_info *info) +{ + unsigned long attribs; + DPRINTK("ep93xxfb_blank - enter\n"); + attribs = inl(VIDEOATTRIBS); + +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + if (blank_mode) { + if (epinfo.off) + (epinfo.off)( 0 ); + + ep93xxfb_outl(attribs & ~(VIDEOATTRIBS_DATAEN | + VIDEOATTRIBS_SYNCEN | VIDEOATTRIBS_PCLKEN | + VIDEOATTRIBS_EN), VIDEOATTRIBS); + } + else { + if (epinfo.clk_src == CLK_INTERNAL) + attribs |= VIDEOATTRIBS_PCLKEN; + else + attribs &= ~VIDEOATTRIBS_PCLKEN; + + ep93xxfb_outl(attribs | VIDEOATTRIBS_DATAEN | + VIDEOATTRIBS_SYNCEN | VIDEOATTRIBS_EN, + VIDEOATTRIBS); + + if (epinfo.configure) + (epinfo.configure)( epinfo.automods ); + if (epinfo.on) + (epinfo.on)( 0 ); + } + return 0; +} + +static int ep93xxfb_mmap(struct fb_info *info,struct vm_area_struct *vma) +{ + unsigned long off, start, len; + + DPRINTK("ep93xxfb_mmap - enter\n"); + + off = vma->vm_pgoff << PAGE_SHIFT; + start = info->fix.smem_start; + len = PAGE_ALIGN(start & ~PAGE_MASK) + info->fix.smem_len; + start &= PAGE_MASK; + if ((vma->vm_end - vma->vm_start + off) > len) + return -EINVAL; + + off += start; + vma->vm_pgoff = off >> PAGE_SHIFT; + + vma->vm_flags |= VM_IO; + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + + if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) { + DPRINTK("ep93xxfb_mmap error\n"); + return -EAGAIN; + } + + DPRINTK("ep93xxfb_mmap - exit\n"); + return 0; +} + +static unsigned long ep93xx_get_pll_frequency(unsigned long pll) +{ + unsigned long fb1, fb2, ipd, ps, freq; + + if (pll == 1) + pll = inl(SYSCON_CLKSET1); + else if (pll == 2) + pll = inl(SYSCON_CLKSET2); + else + return 0; + + ps = (pll & SYSCON_CLKSET1_PLL1_PS_MASK) >> SYSCON_CLKSET1_PLL1_PS_SHIFT; + fb1 = ((pll & SYSCON_CLKSET1_PLL1_X1FBD1_MASK) >> SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT); + fb2 = ((pll & SYSCON_CLKSET1_PLL1_X2FBD2_MASK) >> SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT); + ipd = ((pll & SYSCON_CLKSET1_PLL1_X2IPD_MASK) >> SYSCON_CLKSET1_PLL1_X2IPD_SHIFT); + + freq = (((0x00e10000 * (fb1+1)) / (ipd+1)) * (fb2+1)) >> ps; + return freq; +} + +static int ep93xx_get_max_video_clk() +{ + unsigned long f,freq = 0; + + freq = 14745600 / 4; + f = ep93xx_get_pll_frequency(1) / 4; + if ( f > freq ) + freq = f; + f = ep93xx_get_pll_frequency(2) / 4; + if ( f > freq ) + freq = f; + + return freq; +} + +static int ep93xx_set_video_div(unsigned long freq) +{ + unsigned long pdiv = 0, div = 0, psel = 0, esel = 0; + unsigned long err, f, i, j, k; + + err = -1; + + for (i = 0; i < 3; i++) { + if (i == 0) + f = 14745600 * 2; + else if (i == 1) + f = ep93xx_get_pll_frequency(1) * 2; + else + f = ep93xx_get_pll_frequency(2) * 2; + + for (j = 4; j <= 6; j++) { + k = f / (freq * j); + if (k < 2) + continue; + + if (abs(((f / (j * k))) - freq ) < err ) { + pdiv = j - 3; + div = k; + psel = (i == 2) ? 1 : 0; + esel = (i == 0) ? 0 : 1; + err = (f / (j * k)) - freq; + } + } + } + + if (err == -1) + return -1; + + outl(0xaa, SYSCON_SWLOCK); + outl(SYSCON_VIDDIV_VENA | (esel ? SYSCON_VIDDIV_ESEL : 0) | + (psel ? SYSCON_VIDDIV_PSEL : 0) | + (pdiv << SYSCON_VIDDIV_PDIV_SHIFT) | + (div << SYSCON_VIDDIV_VDIV_SHIFT), SYSCON_VIDDIV); + + return freq + err; +} + +static void ep93xxfb_pixelmod(int bpp) +{ + unsigned long tmpdata = 0; + + DPRINTK("ep93xxfb_pixelmod %dbpp -enter\n",bpp); + switch(bpp) { + case 8: + tmpdata = PIXELMODE_P_8BPP | + PIXELMODE_S_1PPCMAPPED | + PIXELMODE_C_LUT; + epinfo.pixformat = PIXEL_FORMAT_8; + break; + case 16: + tmpdata = PIXELMODE_P_16BPP | + PIXELMODE_S_1PPCMAPPED | + PIXELMODE_C_565; + epinfo.pixformat = PIXEL_FORMAT_16; + break; + case 24: + tmpdata = PIXELMODE_P_24BPP | + PIXELMODE_S_1PPC | + PIXELMODE_C_888; + epinfo.pixformat = PIXEL_FORMAT_24; + break; + case 32: + tmpdata = PIXELMODE_P_32BPP | + PIXELMODE_S_1PPC | + PIXELMODE_C_888; + epinfo.pixformat = PIXEL_FORMAT_32; + break; + default: + break; + } + outl(tmpdata,PIXELMODE); +} + +static void ep93xxfb_timing_signal_generation(void) +{ + unsigned long vlinestotal,vsyncstart,vsyncstop, + vactivestart,vactivestop, + vblankstart,vblankstop, + vclkstart,vclkstop; + + unsigned long hclkstotal,hsyncstart,hsyncstop, + hactivestart,hactivestop, + hblankstart,hblankstop, + hclkstart,hclkstop; + + DPRINTK("ep93xxfb_timing_signal_generation - enter\n"); + + vlinestotal = epinfo.ytotal - 1; + vsyncstart = vlinestotal; + vsyncstop = vlinestotal - epinfo.ysync; + vblankstart = vlinestotal - epinfo.ysync - epinfo.ybp; + vblankstop = epinfo.yfp - 1; + vactivestart = vblankstart; + vactivestop = vblankstop; + vclkstart = vlinestotal; + vclkstop = vlinestotal + 1; + + hclkstotal = epinfo.xtotal - 1; + hsyncstart = hclkstotal; + hsyncstop = hclkstotal - epinfo.xsync; + hblankstart = hclkstotal - epinfo.xsync - epinfo.xbp; + hblankstop = epinfo.xfp - 1; + hactivestart = hblankstart; + hactivestop = hblankstop; + hclkstart = hclkstotal ; + hclkstop = hclkstotal ; + + ep93xxfb_outl(0, VIDEOATTRIBS); + + ep93xxfb_outl( vlinestotal , VLINESTOTAL ); + ep93xxfb_outl( vsyncstart + (vsyncstop << 16), VSYNCSTRTSTOP ); + ep93xxfb_outl( vactivestart + (vactivestop << 16), VACTIVESTRTSTOP ); + ep93xxfb_outl( vblankstart + (vblankstop << 16), VBLANKSTRTSTOP ); + ep93xxfb_outl( vclkstart + (vclkstop << 16), VCLKSTRTSTOP ); + + ep93xxfb_outl( hclkstotal , HCLKSTOTAL ); + ep93xxfb_outl( hsyncstart + (hsyncstop << 16), HSYNCSTRTSTOP ); + ep93xxfb_outl( hactivestart + (hactivestop << 16) , HACTIVESTRTSTOP ); + ep93xxfb_outl( hblankstart + (hblankstop << 16) , HBLANKSTRTSTOP ); + ep93xxfb_outl( hclkstart + (hclkstop << 16) , HCLKSTRTSTOP ); + + ep93xxfb_outl(0, LINECARRY); + +} + +static int ep93xxfb_setcol(struct fb_info *info, int bpp) +{ + + DPRINTK("ep93xxfb_setcol %dbpp\n",bpp); + switch(bpp) { + case 8: + info->var.bits_per_pixel = 8; + info->var.red.length = 8; + info->var.green.length = 8; + info->var.blue.length = 8; + info->fix.visual = FB_VISUAL_PSEUDOCOLOR; + break; + case 16: + info->var.bits_per_pixel = 16; + info->var.red.offset = 11; + info->var.red.length = 5; + info->var.green.offset = 5; + info->var.green.length = 6; + info->var.blue.offset = 0; + info->var.blue.length = 5; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + case 24: + info->var.bits_per_pixel = 24; + info->var.red.length = 8; + info->var.blue.length = 8; + info->var.green.length = 8; + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + case 32: + info->var.bits_per_pixel = 32; + info->var.red.length = 8; + info->var.blue.length = 8; + info->var.green.length = 8; + info->var.transp.length = 0; + info->var.red.offset = 16; + info->var.green.offset = 8; + info->var.blue.offset = 0; + info->var.transp.offset = 0; + info->fix.visual = FB_VISUAL_TRUECOLOR; + break; + default: + return 0; + } + return 1; +} + +static int ep93xxfb_setclk() +{ + unsigned long calc_clk,act_clk; + + if ( epinfo.clk_src == CLK_INTERNAL ) { + outl(0xaa, SYSCON_SWLOCK); + outl(inl(SYSCON_DEVCFG) & ~SYSCON_DEVCFG_EXVC, SYSCON_DEVCFG); + calc_clk = epinfo.refresh; + act_clk = ep93xx_set_video_div( calc_clk ); + if ( act_clk == -1 ) + return -ENODEV; + + epinfo.refresh = act_clk; + epinfo.pixclock = 1000000000 / (act_clk / 1000); + } + else { + outl(0xaa, SYSCON_SWLOCK); + outl(0, SYSCON_VIDDIV); + outl(0xaa, SYSCON_SWLOCK); + outl(inl(SYSCON_DEVCFG) | SYSCON_DEVCFG_EXVC, SYSCON_DEVCFG); + } + + return 0; +} + + +static void ep93xxfb_get_par(struct fb_info *info) +{ + + DPRINTK("ep93xxfb_get_par - enter\n"); + epinfo.configure = NULL; + epinfo.on = NULL; + epinfo.off = NULL; + + switch( vout ) { + case LCD_OUT: + epinfo.on = philips_lb064v02_on; + epinfo.off = philips_lb064v02_off; + + case CRT_OUT: + epinfo.xres = ep93xxfb_vmods[vmode].hres; + epinfo.xsync = ep93xxfb_vmods[vmode].hsync; + epinfo.xfp = ep93xxfb_vmods[vmode].hfp; + epinfo.xbp = ep93xxfb_vmods[vmode].hbp; + epinfo.xtotal = epinfo.xres + epinfo.xsync + + epinfo.xfp + epinfo.xbp; + + epinfo.yres = ep93xxfb_vmods[vmode].vres; + epinfo.ysync = ep93xxfb_vmods[vmode].vsync; + epinfo.yfp = ep93xxfb_vmods[vmode].vfp; + epinfo.ybp = ep93xxfb_vmods[vmode].vbp; + epinfo.ytotal = epinfo.yres + epinfo.ysync + + epinfo.yfp + epinfo.ybp; + + epinfo.refresh = ep93xxfb_vmods[vmode].refresh; + epinfo.refresh = epinfo.xtotal * epinfo.ytotal * epinfo.refresh; + epinfo.pixclock = 1000000000 / ( epinfo.refresh / 1000); + epinfo.bpp = depth; + + epinfo.clk_src = ep93xxfb_vmods[vmode].clk_src; + epinfo.clk_edge = ep93xxfb_vmods[vmode].clk_edge; + epinfo.pol_blank = ep93xxfb_vmods[vmode].pol_blank; + epinfo.pol_xsync = ep93xxfb_vmods[vmode].pol_hsync; + epinfo.pol_ysync = ep93xxfb_vmods[vmode].pol_vsync; + break; + + case TV_OUT: + epinfo.xres = cxmods[vmode].hres; + epinfo.xsync = 4; + epinfo.xbp = cxmods[vmode].hblank; + epinfo.xfp = cxmods[vmode].hclktotal - epinfo.xbp - + cxmods[vmode].hres - 4; + epinfo.xtotal = cxmods[vmode].hclktotal; + + epinfo.yres = cxmods[vmode].vres; + epinfo.ysync = 2; + epinfo.ybp = cxmods[vmode].vblank; + epinfo.yfp = cxmods[vmode].vclktotal - epinfo.ybp - + cxmods[vmode].vres - 2; + epinfo.ytotal = cxmods[vmode].vclktotal; + epinfo.bpp = depth; + + epinfo.clk_src = CLK_EXTERNAL; + epinfo.automods = cxmods[vmode].automode; + epinfo.clk_edge = EDGE_FALLING; + epinfo.pol_blank = POL_LOW; + epinfo.pol_xsync = POL_LOW, + epinfo.pol_ysync = POL_LOW; + + epinfo.refresh = cxmods[vmode].clkfrequency ; + epinfo.pixclock = 1000000000 / ( epinfo.refresh / 1000); + + epinfo.configure = cx25871_config; + epinfo.on = cx25871_on; + epinfo.off = cx25871_off; + break; + } +} + +static int ep93xxfb_alloc_videomem(void) +{ + unsigned long adr,size,pgsize; + int order; + + DPRINTK("ep93xxfb_alloc_videomem - enter \n"); + + epinfo.fb_log = NULL; + epinfo.fb_size = PAGE_ALIGN( MAX_FBMEM_SIZE ); + order = get_order( epinfo.fb_size ); + epinfo.fb_log = (void*) __get_free_pages( GFP_KERNEL, order ); + + if (epinfo.fb_log) { + epinfo.fb_phys = __virt_to_phys((int) epinfo.fb_log ); + adr = (unsigned long)epinfo.fb_log; + size = epinfo.fb_size; + pgsize = 1 << order; + do { + adr += pgsize; + SetPageReserved(virt_to_page(adr)); + } while(size -= pgsize); + } + else + return -ENOMEM; + + memset(epinfo.fb_log,0x00,epinfo.fb_size); + DPRINTK(" fb_log_addres = 0x%x\n",epinfo.fb_log); + DPRINTK(" fb_phys_address = 0x%x\n",epinfo.fb_phys); + DPRINTK(" fb_size = %lu\n",epinfo.fb_size); + DPRINTK(" fb_page_order = %d\n",order); + DPRINTK("ep93xxfb_alloc_videomem - exit \n"); + return 0; +} + +static void ep93xxfb_release_videomem(void) +{ + unsigned long adr,size,psize; + int order; + + DPRINTK("ep93xxfb_release_videomem - enter \n"); + if (epinfo.fb_log) { + order = get_order(epinfo.fb_size); + adr = (unsigned long)epinfo.fb_log; + size = epinfo.fb_size; + psize = 1 << order ; + do { + adr += psize; + ClearPageReserved(virt_to_page(adr)); + } while(size -= psize); + free_pages((unsigned long)epinfo.fb_log, order ); + } + DPRINTK("ep93xxfb_release_videomem - exit \n"); +} + +static void ep93xxfb_setinfo(struct fb_info *info) +{ + + info->pseudo_palette = pseudo_palette; + info->var.xres = epinfo.xres; + info->var.yres = epinfo.yres; + info->var.xres_virtual = epinfo.xres; + info->var.yres_virtual = epinfo.yres; + + ep93xxfb_setcol( info, depth ); + + info->var.activate = FB_ACTIVATE_NOW; + info->var.left_margin = epinfo.xbp; + info->var.right_margin = epinfo.xfp; + info->var.upper_margin = epinfo.ybp; + info->var.lower_margin = epinfo.yfp; + info->var.hsync_len = epinfo.xsync; + info->var.vsync_len = epinfo.ysync; + + if( epinfo.pol_xsync == POL_HIGH ) + info->var.sync |= FB_SYNC_HOR_HIGH_ACT; + if( epinfo.pol_ysync == POL_HIGH ) + info->var.sync |= FB_SYNC_VERT_HIGH_ACT; + + info->var.vmode = FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP; + info->fix.smem_start = epinfo.fb_phys; + info->fix.smem_len = epinfo.fb_size; + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.line_length = epinfo.xres * (epinfo.bpp / 8); + info->screen_base = epinfo.fb_log; + info->var.pixclock = epinfo.pixclock; + info->fix.ypanstep = 1; + info->fix.ywrapstep = 1; + +} + +static int ep93xxfb_config(struct fb_info *info) +{ + unsigned long attribs; + + DPRINTK("ep93xxfb_config - enter\n"); + + ep93xxfb_get_par( info ); + if( ep93xxfb_alloc_videomem() != 0 ) { + printk("Unable to allocate video memory\n"); + return -ENOMEM; + } + + if( ep93xxfb_setclk() != 0 ) { + printk("Unable to set pixel clock\n"); + ep93xxfb_release_videomem(); + return -ENODEV; + } + + SysconSetLocked(SYSCON_DEVCFG, inl(SYSCON_DEVCFG) | SYSCON_DEVCFG_RasOnP3); + ep93xxfb_timing_signal_generation(); + + /* set video memory parameters */ + outl(epinfo.fb_phys, VIDSCRNPAGE); + outl(epinfo.yres , SCRNLINES); + outl(((epinfo.xres * epinfo.bpp) / 32) - 1, LINELENGTH); + outl((epinfo.xres * epinfo.bpp) / 32, VLINESTEP); + + + /* set pixel mode */ + ep93xxfb_pixelmod(depth); + + attribs = 0; + +#ifdef CONFIG_EP93XX_SDCS0 + attribs |= 0 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS1 + attribs |= 1 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS2 + attribs |= 2 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif +#ifdef CONFIG_EP93XX_SDCS3 + attribs |= 3 << VIDEOATTRIBS_SDSEL_SHIFT; +#endif + + if(epinfo.clk_edge == EDGE_RISING) + attribs |= VIDEOATTRIBS_INVCLK; + if(epinfo.pol_blank == POL_HIGH) + attribs |= VIDEOATTRIBS_BLKPOL; + if(epinfo.pol_xsync == POL_HIGH) + attribs |= VIDEOATTRIBS_HSPOL; + if(epinfo.pol_ysync == POL_HIGH) + attribs |= VIDEOATTRIBS_VCPOL; + + ep93xxfb_outl(attribs, VIDEOATTRIBS); + ep93xxfb_setinfo( info ); + + if(epinfo.configure) + (epinfo.configure)( epinfo.automods ); + + ep93xxfb_blank( 0 , info ); + + DPRINTK("ep93xxfb_config - exit\n"); + return 0; +} + +int ep93xxfb_ioctl(struct fb_info *info,unsigned int cmd, unsigned long arg) +{ + struct fb_fillrect fill; + struct fb_copyarea cparea; + struct fb_image img; + struct ep93xx_line line; + struct ep93xx_cursor cursor; + unsigned long copy_ret = 0; + + switch (cmd) { + case FBIO_EP93XX_CURSOR: + copy_ret = copy_from_user(&cursor, (void *)arg, sizeof(struct ep93xx_cursor)); + ep93xxfb_cursor(info,&cursor); + break; + case FBIO_EP93XX_LINE: + copy_ret = copy_from_user(&line, (void *)arg, sizeof(struct ep93xx_line)); + ep93xxfb_line(info,&line); + break; + case FBIO_EP93XX_FILL: + copy_ret = copy_from_user(&fill, (void *)arg, sizeof(struct fb_fillrect)); + ep93xxfb_fillrect(info,&fill); + break; + case FBIO_EP93XX_BLIT: + copy_ret = copy_from_user(&img, (void *)arg, sizeof(struct fb_image)); + ep93xxfb_imageblit(info, &img); + break; + case FBIO_EP93XX_COPY: + copy_ret = copy_from_user(&cparea, (void *)arg, sizeof(struct fb_copyarea)); + ep93xxfb_copyarea(info,&cparea); + break; + default: + return -EFAULT; + } + if (copy_ret != 0) + return -1; + else + return 0; +} + + +static struct fb_ops ep93xxfb_ops = { + .owner = THIS_MODULE, + .fb_setcolreg = ep93xxfb_setcolreg, + .fb_check_var = ep93xxfb_check_var, + .fb_set_par = ep93xxfb_set_par, + .fb_blank = ep93xxfb_blank, + .fb_pan_display = ep93xx_pan_display, + .fb_fillrect = ep93xxfb_fillrect, + .fb_copyarea = ep93xxfb_copyarea, + .fb_imageblit = cfb_imageblit, + .fb_cursor = ep93xxfb_cursor, + .fb_ioctl = ep93xxfb_ioctl, + .fb_mmap = ep93xxfb_mmap, +}; + + +static struct resource ep93xxfb_raster_resources = { + .start = EP93XX_RASTER_PHYS_BASE, + .end = EP93XX_RASTER_PHYS_BASE + 0x1ffff, + .flags = IORESOURCE_MEM, +}; + + +static int __init ep93xxfb_probe(struct platform_device *device) +{ + struct fb_info *info = NULL; + struct resource *res = NULL; + int ret = 0; + int arb = 0; + + DPRINTK("ep93xxfb_probe - enter \n"); + + + if(!device) { + printk("error : to_platform_device\n"); + return -ENODEV; + } + res = platform_get_resource( device, IORESOURCE_MEM, 0); + if(!res) { + printk("error : platform_get_resource \n"); + return -ENODEV; + } + cursor_data = kmalloc( 64 * 64 * 2, GFP_KERNEL ); + memset( cursor_data, 0x00, 64 * 64 * 2 ); + if(!cursor_data) { + printk("Unable to allocate memory for hw_cursor\n"); + return -ENOMEM; + } + if (!request_mem_region(res->start,res->end - res->start + 1, FBDEV_NAME )) + return -EBUSY; + + info = framebuffer_alloc(sizeof(u32) * 256, &device->dev); + + if(!info) { + printk("Unable to allocate memory for frame buffer\n"); + return -ENOMEM; + } + + info->flags = FBINFO_DEFAULT; + strncpy(info->fix.id, FBDEV_NAME, sizeof(info->fix.id)); + info->fix.mmio_start = res->start; + info->fix.mmio_len = res->end - res->start + 1; + info->fbops = &ep93xxfb_ops; + info->pseudo_palette = info->par; + info->state = FBINFO_STATE_RUNNING; + + if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { + ret = -ENOMEM; + goto fbuff; + } + + if ((ret = ep93xxfb_config(info)) < 0) + goto clmap; + + if (register_framebuffer(info) < 0) { + printk(KERN_ERR "Unable to register ep93xxfb frame buffer\n"); + ret = -EINVAL; + goto clmap; + } + platform_set_drvdata(device, info); + printk(KERN_INFO "fb%d: EP93xx frame buffer at %dx%dx%dbpp\n", info->node, + info->var.xres, info->var.yres, info->var.bits_per_pixel); + + register_reboot_notifier(&cx25871_notifier); + + /*change the raster arb to the highest one--Bo*/ + arb = inl(SYSCON_BMAR); + arb = (arb & 0x3f8) | 0x01; + outl(arb,SYSCON_BMAR); + + DPRINTK("ep93xxfb_probe - exit \n"); + return 0; + +clmap: + fb_dealloc_cmap(&info->cmap); + +fbuff: + framebuffer_release(info); + return ret; +} + +static int ep93xxfb_remove(struct platform_device *device) +{ + struct resource *res; + struct fb_info *info; + struct ep93xx_cursor cursor; + + DPRINTK("ep93xxfb_remove - enter \n"); + + info = platform_get_drvdata(device); + + ep93xxfb_release_videomem(); + + res = platform_get_resource( device, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + + platform_set_drvdata(device, NULL); + unregister_framebuffer(info); + + fb_dealloc_cmap(&info->cmap); + framebuffer_release(info); + + cursor.flags = CURSOR_OFF; + ep93xxfb_cursor(info,&cursor); + if(cursor_data!=NULL) + kfree(cursor_data); + + unregister_reboot_notifier(&cx25871_notifier); + ep93xxfb_blank( 1, info ); + + DPRINTK("ep93xxfb_remove - exit \n"); + return 0; +} + +static void ep93xxfb_platform_release(struct device *device) +{ + DPRINTK("ep93xxfb_platform_release - enter\n"); +} + +static int ep93xxfb_check_param(void) +{ + + switch(vout) { + case CRT_OUT: + if( vmode >=(sizeof(ep93xxfb_vmods)/sizeof(ep93xxfb_vmods[0]))){ + vmode = 1; + depth = DEFAULT_BPP; + return 0; + } + break; + case LCD_OUT: + DPRINTK("ep93xxfb_check_param: LCD_OUT\n"); + if(depth != 16) { + DPRINTK("ep93xxfb_check_param: vmode = %d, depth = %d\n", vmode, depth); + //vmode = 0; /* Not true anymore, could be the QVGA or PrimeView -- TAS */ + depth = DEFAULT_BPP; + return 0; + } + break; + case TV_OUT: + if( vmode >= CXMODES_COUNT ) { + vmode = DEFAULT_MODE; + depth = DEFAULT_BPP; + return 0; + } + break; + default: + vmode = DEFAULT_MODE; + depth = DEFAULT_BPP; + vout = DEFAULT_OUT; + return 0; + break; + } + + if(!((depth == 8) || (depth == 16) || (depth == 24) || (depth == 32))) + depth = DEFAULT_BPP; + + return 1; +} + +int __init ep93xxfb_setup(char *options) +{ + char *opt; + + DPRINTK("ep93xxfb_setup - %s\n",options); + + if (!options || !*options) + return 0; + + while ((opt = strsep(&options, ",")) != NULL) { + if (!strncmp(opt, "vout=", 5)) + vout = simple_strtoul(opt + 5, NULL, 0); + else if (!strncmp(opt, "vmode=", 6)) + vmode = simple_strtoul(opt + 6, NULL, 0); + else if (!strncmp(opt, "depth=", 6)) + depth = simple_strtoul(opt + 6, NULL, 0); + } + ep93xxfb_check_param(); + return 0; +} + + +static struct platform_driver ep93xxfb_driver = { + .probe = ep93xxfb_probe, + .remove = ep93xxfb_remove, + .driver = { + .name = FBDEV_NAME, + }, +}; + +static struct platform_device ep93xxfb_device = { + .name = FBDEV_NAME, + .id = -1, + .dev = { + .release = ep93xxfb_platform_release, + }, + .num_resources = 1, + .resource = &ep93xxfb_raster_resources, +}; + +int __init ep93xxfb_init(void) +{ + int ret = 0; + char *option = NULL; + + DPRINTK("ep93xxfb_init - enter\n"); + + if (fb_get_options("ep93xxfb", &option)) + return -ENODEV; + ep93xxfb_setup(option); + + + if( !ep93xxfb_check_param() ) { + printk("Unsupported format \n"); + return -1; + } + + ret = platform_driver_register(&ep93xxfb_driver); + + if (!ret) { + ret = platform_device_register(&ep93xxfb_device); + if (ret) + platform_driver_unregister(&ep93xxfb_driver); + } + outl(0x00000000, BLOCKCTRL); + request_irq(IRQ_EP93XX_GRAPHICS, ep93xxfb_irq_handler, SA_INTERRUPT, + "graphics",NULL); + + DPRINTK("ep93xxfb_init - exit\n"); + return ret; +} + + + +static void __exit ep93xxfb_exit(void) +{ + DPRINTK("ep93xxfb_exit - enter\n"); + platform_driver_unregister(&ep93xxfb_driver); + platform_device_unregister(&ep93xxfb_device); + DPRINTK("ep93xxfb_exit - exit\n"); +} + +module_init(ep93xxfb_init); +module_exit(ep93xxfb_exit); + + +module_param( vmode, int, 1); +MODULE_PARM_DESC(vmode, "Specify the video mode number that should be used"); +module_param( vout , int , 0 ); +MODULE_PARM_DESC(vout ,"Specify video output (0 = CRT ,1 = LCD , 2 = TV)"); +module_param( depth , int, 16); +MODULE_PARM_DESC(depth ,"Color depth (8,16,24,32)"); +MODULE_LICENSE("GPL"); diff -urN -x CVS linux-2.6.20/drivers/video/ep93xxfb.h linux-2.6.20-AT91/drivers/video/ep93xxfb.h --- linux-2.6.20/drivers/video/ep93xxfb.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/ep93xxfb.h 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,236 @@ +#ifndef __EP93XXFB_H__ +#define __EP93XXFB_H__ + + +#define POL_HIGH 1 +#define POL_LOW 0 +#define EDGE_RISING 1 +#define EDGE_FALLING 0 +#define CLK_INTERNAL 1 +#define CLK_EXTERNAL 0 + +#define CRT_OUT 0 +#define LCD_OUT 1 +#define TV_OUT 2 + +#define MAX_XRES 1280 +#define MAX_YRES 1024 +#define MAX_BPP 16 +#define MAX_FBMEM_SIZE 1920000 + +#define MAX_XRES_CRT MAX_XRES +#define MAX_YRES_CRT MAX_YRES +#define MAX_XRES_SVIDEO 1024 +#define MAX_YRES_SVIDEO 768 + +#define PIXEL_FORMAT_SHIFT 17 +#define PIXEL_FORMAT_4 ( 1 << PIXEL_FORMAT_SHIFT ) +#define PIXEL_FORMAT_8 ( 2 << PIXEL_FORMAT_SHIFT ) +#define PIXEL_FORMAT_16 ( 4 << PIXEL_FORMAT_SHIFT ) +#define PIXEL_FORMAT_24 ( 6 << PIXEL_FORMAT_SHIFT ) +#define PIXEL_FORMAT_32 ( 7 << PIXEL_FORMAT_SHIFT ) + + +struct ep93xxfb_videomodes +{ + const char *name; + + unsigned long hres; // Horizontal Valid + unsigned long hfp; // Horizontal Front Porch + unsigned long hsync; // Horizontal Sync Width + unsigned long hbp; // Horizontal Back Porch + + unsigned long vres; // Vertical Valid + unsigned long vfp; // Vertical Front Porch + unsigned long vsync; // Vertical Sync Width + unsigned long vbp; // Vertical Back Porch + + unsigned long refresh; // Vertical Sync Frequency + + unsigned long clk_src; + unsigned long clk_edge; + unsigned long pol_blank; + unsigned long pol_hsync; + unsigned long pol_vsync; +}; + + +struct ep93xxfb_info +{ + + + dma_addr_t fb_phys; + void *fb_log; + unsigned long fb_size; + unsigned long fb_actsize; + + unsigned long xtotal; + unsigned long ytotal; + + unsigned int xres; + unsigned int xfp; + unsigned int xsync; + unsigned int xbp; + + unsigned int yres; + unsigned int yfp; + unsigned int ysync; + unsigned int ybp; + unsigned int bpp; + + unsigned long refresh; + unsigned long pixclock; + unsigned long pixformat; + + unsigned int clk_src; + unsigned int clk_edge; + unsigned int pol_blank; + unsigned int pol_xsync; + unsigned int pol_ysync; + + unsigned char automods; + + void (*configure)(unsigned char value); + void (*on)(unsigned char value); + void (*off)(unsigned char value); +}; + +static int ep93xxfb_setclk(void); +static int ep93xx_get_max_video_clk(void); +static void ep93xxfb_pixelmod(int bpp); +static void ep93xxfb_timing_signal_generation(void); +static int ep93xxfb_blank(int blank_mode,struct fb_info *info); + +#define EE_DELAY_USEC 2 +#define EE_READ_TIMEOUT 100 +#define CX25871_DEV_ADDRESS 0x88 +#define GPIOG_EEDAT 2 +#define GPIOG_EECLK 1 +#define CXMODES_COUNT 24 + +struct cx25871_vmodes +{ + + const char *name; + unsigned char automode; + unsigned int hres; + unsigned int vres; + unsigned int hclktotal; + unsigned int vclktotal; + unsigned int hblank; + unsigned int vblank; + unsigned long clkfrequency; + +}; + + +int write_reg(unsigned char ucRegAddr, unsigned char ucRegValue); +void cx25871_on(unsigned char value); +void cx25871_off(unsigned char value); +void cx25871_config(unsigned char value); + +static void philips_lb064v02_on(unsigned char value); +static void philips_lb064v02_off(unsigned char value); + + +#define FBIO_EP93XX_CURSOR 0x000046c1 +#define FBIO_EP93XX_LINE 0x000046c2 +#define FBIO_EP93XX_FILL 0x000046c3 +#define FBIO_EP93XX_BLIT 0x000046c4 +#define FBIO_EP93XX_COPY 0x000046c5 + + +#define CURSOR_BLINK 0x00000001 +#define CURSOR_MOVE 0x00000002 +#define CURSOR_SETSHAPE 0x00000004 +#define CURSOR_SETCOLOR 0x00000008 +#define CURSOR_ON 0x00000010 +#define CURSOR_OFF 0x00000020 + + +/* +* ioctl(fd, FBIO_EP93XX_CURSOR, ep93xx_cursor *) +* +* "data" points to an array of pixels that define the cursor; each row should +* be a multiple of 32-bit values (i.e. 16 pixels). Each pixel is two bits, +* where the values are: +* +* 00 => transparent 01 => invert 10 => color1 11 => color2 +* +* The data is arranged as follows (per word): +* +* bits: |31-30|29-28|27-26|25-24|23-22|21-20|19-18|17-16| +* pixel: | 12 | 13 | 14 | 15 | 8 | 9 | 10 | 11 | +* bits: |15-14|13-12|11-10| 9-8 | 7-6 | 5-4 | 3-2 | 1-0 | +* pixel: | 4 | 5 | 6 | 7 | 0 | 1 | 2 | 3 | +* +* Regardless of the frame buffer color depth, "color1", "color2", +* "blinkcolor1", and "blinkcolor2" are 24-bit colors since the cursor is +* injected into the data stream right before the video DAC. +* +* When "blinkrate" is not zero, pixel value 10 will alternate between "color1" +* and "blinkcolor1" (similar for pixel value 11 and "color2"/"blinkcolor2"). +* +* "blinkrate" ranges between 0 and 255. When 0, blinking is disabled. 255 is +* the fastest blink rate and 1 is the slowest. +* +* Both "width" and "height" must be between 1 and 64; it is preferable to have +* "width" a multiple of 16. +*/ +struct ep93xx_cursor { + unsigned long flags; + unsigned long dx; // Only used if CURSOR_MOVE is set + unsigned long dy; // Only used if CURSOR_MOVE is set + unsigned long width; // Only used if CURSOR_SETSHAPE is set + unsigned long height; // Only used if CURSOR_SETSHAPE is set + const char *data; // Only used if CURSOR_SETSHAPE is set + unsigned long blinkrate; // Only used if CURSOR_BLINK is set + unsigned long color1; // Only used if CURSOR_SETCOLOR is set + unsigned long color2; // Only used if CURSOR_SETCOLOR is set + unsigned long blinkcolor1; // Only used if CURSOR_SETCOLOR is set + unsigned long blinkcolor2; // Only used if CURSOR_SETCOLOR is set +}; + + +/* + * The bits in the flags field of ep93xx_line. +*/ +/* +* ioctl(fd, FBIO_EP93XX_LINE, ep93xx_line *) +* +* The line starts at ("x1","y1") and ends at ("x2","y2"). This means that +* when using a pattern, the two coordinates are not transitive (i.e. swapping +* ("x1","y1") with ("x2","y2") will not necessarily draw the exact same line, +* pattern-wise). +* +* "pattern" is a 2 to 16 bit pattern (since a 1 bit pattern isn't much of a +* pattern). The lower 16 bits define the pattern (1 being foreground, 0 being +* background or transparent), and bits 19-16 define the length of the pattern +* (as pattern length - 1). So, for example, "0xf00ff" defines a 16 bit +* with the first 8 pixels in the foreground color and the next 8 pixels in the +* background color or transparent. +* +* LINE_PRECISE is used to apply angularly corrected patterns to line. It +* should only be used when LINE_PATTERN is also set. The pattern will be +* applied along the length of the line, instead of along the length of the +* major axis. This may result in the loss of fine details in the pattern, and +* will take more time to draw the line in most cases. +*/ + +#define LINE_PATTERN 0x00000001 +#define LINE_PRECISE 0x00000002 +#define LINE_BACKGROUND 0x00000004 + +struct ep93xx_line { + unsigned long flags; + unsigned long x1; + unsigned long y1; + unsigned long x2; + unsigned long y2; + unsigned long fgcolor; + unsigned long bgcolor; // Only used if LINE_BACKGROUND is set + unsigned long pattern; // Only used if LINE_PATTERN is set +}; + +#endif /* __EP93XXFB_H__ */ + diff -urN -x CVS linux-2.6.20/drivers/video/Kconfig linux-2.6.20-AT91/drivers/video/Kconfig --- linux-2.6.20/drivers/video/Kconfig 2007-07-13 11:48:43.000000000 -0500 +++ linux-2.6.20-AT91/drivers/video/Kconfig 2007-07-12 14:43:37.000000000 -0500 @@ -144,6 +144,40 @@ Say N unless you have such a graphics board or plan to get one before you next recompile the kernel. +config FB_EP93XX + tristate "EP93xx frame buffer support" + depends on FB + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + + ---help--- + This is the frame buffer device driver for the internal raster engine + on certain members of the EP93xx family. + +config FB_EP93XX_GPIO + int "GPIO Address for LCD Power" + depends on FB_EP93XX + default "2" + help + This option is used to configure which GPIO line will be used + to Enable the LCD and backlight power. This is not the actual + line, but the decimal value that the address will be OR'd with + to select the line. Set this to "2" if you have a Cirrus + EDB9315A board. Some EMAC boards use "1". + +config FB_EP93XX_LCDWS + bool "Wide Screen LCD display" + depends on FB_EP93XX + help + Use the Primeview PM070WX2 800x480 LCD connected to the board. + +config FB_EP93XX_QVGA + bool "Quarter VGA LCD display" + depends on FB_EP93XX + help + Use the LB040Q02 320x240 connected to the board. + config FB_PM2 tristate "Permedia2 support" depends on FB && ((AMIGA && BROKEN) || PCI) diff -urN -x CVS linux-2.6.20/drivers/video/Kconfig.orig linux-2.6.20-AT91/drivers/video/Kconfig.orig --- linux-2.6.20/drivers/video/Kconfig.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/Kconfig.orig 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,1696 @@ +# +# Video configuration +# + +menu "Graphics support" + +config FIRMWARE_EDID + bool "Enable firmware EDID" + default y + ---help--- + This enables access to the EDID transferred from the firmware. + On the i386, this is from the Video BIOS. Enable this if DDC/I2C + transfers do not work for your driver and if you are using + nvidiafb, i810fb or savagefb. + + In general, choosing Y for this option is safe. If you + experience extremely long delays while booting before you get + something on your display, try setting this to N. Matrox cards in + combination with certain motherboards and monitors are known to + suffer from this problem. + +config FB + tristate "Support for frame buffer devices" + ---help--- + The frame buffer device provides an abstraction for the graphics + hardware. It represents the frame buffer of some video hardware and + allows application software to access the graphics hardware through + a well-defined interface, so the software doesn't need to know + anything about the low-level (hardware register) stuff. + + Frame buffer devices work identically across the different + architectures supported by Linux and make the implementation of + application programs easier and more portable; at this point, an X + server exists which uses the frame buffer device exclusively. + On several non-X86 architectures, the frame buffer device is the + only way to use the graphics hardware. + + The device is accessed through special device nodes, usually located + in the /dev directory, i.e. /dev/fb*. + + You need an utility program called fbset to make full use of frame + buffer devices. Please read + and the Framebuffer-HOWTO at + for more + information. + + Say Y here and to the driver for your graphics board below if you + are compiling a kernel for a non-x86 architecture. + + If you are compiling for the x86 architecture, you can say Y if you + want to play with it, but it is not essential. Please note that + running graphical applications that directly touch the hardware + (e.g. an accelerated X server) and that are not frame buffer + device-aware may cause unexpected results. If unsure, say N. + +config FB_DDC + tristate + depends on FB && I2C && I2C_ALGOBIT + default n + +config FB_CFB_FILLRECT + tristate + depends on FB + default n + ---help--- + Include the cfb_fillrect function for generic software rectangle + filling. This is used by drivers that don't provide their own + (accelerated) version. + +config FB_CFB_COPYAREA + tristate + depends on FB + default n + ---help--- + Include the cfb_copyarea function for generic software area copying. + This is used by drivers that don't provide their own (accelerated) + version. + +config FB_CFB_IMAGEBLIT + tristate + depends on FB + default n + ---help--- + Include the cfb_imageblit function for generic software image + blitting. This is used by drivers that don't provide their own + (accelerated) version. + +config FB_MACMODES + tristate + depends on FB + default n + +config FB_BACKLIGHT + bool + depends on FB + select BACKLIGHT_LCD_SUPPORT + select BACKLIGHT_CLASS_DEVICE + default n + +config FB_MODE_HELPERS + bool "Enable Video Mode Handling Helpers" + depends on FB + default n + ---help--- + This enables functions for handling video modes using the + Generalized Timing Formula and the EDID parser. A few drivers rely + on this feature such as the radeonfb, rivafb, and the i810fb. If + your driver does not take advantage of this feature, choosing Y will + just increase the kernel size by about 5K. + +config FB_TILEBLITTING + bool "Enable Tile Blitting Support" + depends on FB + default n + ---help--- + This enables tile blitting. Tile blitting is a drawing technique + where the screen is divided into rectangular sections (tiles), whereas + the standard blitting divides the screen into pixels. Because the + default drawing element is a tile, drawing functions will be passed + parameters in terms of number of tiles instead of number of pixels. + For example, to draw a single character, instead of using bitmaps, + an index to an array of bitmaps will be used. To clear or move a + rectangular section of a screen, the rectangle will be described in + terms of number of tiles in the x- and y-axis. + + This is particularly important to one driver, matroxfb. If + unsure, say N. + +config FB_CIRRUS + tristate "Cirrus Logic support" + depends on FB && (ZORRO || PCI) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + This enables support for Cirrus Logic GD542x/543x based boards on + Amiga: SD64, Piccolo, Picasso II/II+, Picasso IV, or EGS Spectrum. + + If you have a PCI-based system, this enables support for these + chips: GD-543x, GD-544x, GD-5480. + + Please read the file . + + Say N unless you have such a graphics board or plan to get one + before you next recompile the kernel. + +config FB_EP93XX + tristate "EP93xx frame buffer support" + depends on FB + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + + ---help--- + This is the frame buffer device driver for the internal raster engine + on certain members of the EP93xx family. + +config FB_EP93XX_GPIO + int "GPIO Address for LCD Power" + depends on FB_EP93XX + default "2" + help + This option is used to configure which GPIO line will be used + to Enable the LCD and backlight power. This is not the actual + line, but the decimal value that the address will be OR'd with + to select the line. Set this to "2" if you have a Cirrus + EDB9315A board. Some EMAC boards use "1". + +config FB_EP93XX_LCDWS + bool "Wide Screen LCD display" + depends on FB_EP93XX + help + Use the Primeview PM070WX2 800x480 LCD connected to the board. + +config FB_EP93XX_QVGA + bool "Quarter VGA LCD display" + depends on FB_EP93XX + help + Use the LB040Q02 320x240 connected to the board. + +config FB_PM2 + tristate "Permedia2 support" + depends on FB && ((AMIGA && BROKEN) || PCI) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Permedia2 AGP frame + buffer card from ASK, aka `Graphic Blaster Exxtreme'. There is a + product page at + . + +config FB_PM2_FIFO_DISCONNECT + bool "enable FIFO disconnect feature" + depends on FB_PM2 && PCI + help + Support the Permedia2 FIFO disconnect feature (see CONFIG_FB_PM2). + +config FB_ARMCLCD + tristate "ARM PrimeCell PL110 support" + depends on FB && ARM && ARM_AMBA + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This framebuffer device driver is for the ARM PrimeCell PL110 + Colour LCD controller. ARM PrimeCells provide the building + blocks for System on a Chip devices. + + If you want to compile this as a module (=code which can be + inserted into and removed from the running kernel), say M + here and read . The module + will be called amba-clcd. + +choice + + depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X) + prompt "LCD Panel" + default FB_ARMCLCD_SHARP_LQ035Q7DB02 + +config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT + bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC" + help + This is an implementation of the Sharp LQ035Q7DB02, a 3.5" + color QVGA, HRTFT panel. The LogicPD device includes + an integrated HRTFT controller IC. + The native resolution is 240x320. + +config FB_ARMCLCD_SHARP_LQ057Q3DC02 + bool "LogicPD LCD 5.7\" QVGA" + help + This is an implementation of the Sharp LQ057Q3DC02, a 5.7" + color QVGA, TFT panel. The LogicPD device includes an + The native resolution is 320x240. + +config FB_ARMCLCD_SHARP_LQ64D343 + bool "LogicPD LCD 6.4\" VGA" + help + This is an implementation of the Sharp LQ64D343, a 6.4" + color VGA, TFT panel. The LogicPD device includes an + The native resolution is 640x480. + +config FB_ARMCLCD_SHARP_LQ10D368 + bool "LogicPD LCD 10.4\" VGA" + help + This is an implementation of the Sharp LQ10D368, a 10.4" + color VGA, TFT panel. The LogicPD device includes an + The native resolution is 640x480. + + +config FB_ARMCLCD_SHARP_LQ121S1DG41 + bool "LogicPD LCD 12.1\" SVGA" + help + This is an implementation of the Sharp LQ121S1DG41, a 12.1" + color SVGA, TFT panel. The LogicPD device includes an + The native resolution is 800x600. + + This panel requires a clock rate may be an integer fraction + of the base LCDCLK frequency. The driver will select the + highest frequency available that is lower than the maximum + allowed. The panel may flicker if the clock rate is + slower than the recommended minimum. + +config FB_ARMCLCD_AUO_A070VW01_WIDE + bool "AU Optronics A070VW01 LCD 7.0\" WIDE" + help + This is an implementation of the AU Optronics, a 7.0" + WIDE Color. The native resolution is 234x480. + +config FB_ARMCLCD_HITACHI + bool "Hitachi Wide Screen 800x480" + help + This is an implementation of the Hitachi 800x480. + +endchoice + + +config FB_ACORN + bool "Acorn VIDC support" + depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Acorn VIDC graphics + hardware found in Acorn RISC PCs and other ARM-based machines. If + unsure, say N. + +config FB_CLPS711X + bool "CLPS711X LCD support" + depends on (FB = y) && ARM && ARCH_CLPS711X + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Say Y to enable the Framebuffer driver for the CLPS7111 and + EP7212 processors. + +config FB_SA1100 + bool "SA-1100 LCD support" + depends on (FB = y) && ARM && ARCH_SA1100 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is a framebuffer device for the SA-1100 LCD Controller. + See for information on framebuffer + devices. + + If you plan to use the LCD display with your SA-1100 system, say + Y here. + +config FB_IMX + tristate "Motorola i.MX LCD support" + depends on FB && ARM && ARCH_IMX + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + +config FB_CYBER2000 + tristate "CyberPro 2000/2010/5000 support" + depends on FB && PCI && (BROKEN || !SPARC64) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This enables support for the Integraphics CyberPro 20x0 and 5000 + VGA chips used in the Rebel.com Netwinder and other machines. + Say Y if you have a NetWinder or a graphics card containing this + device, otherwise say N. + +config FB_APOLLO + bool + depends on (FB = y) && APOLLO + default y + select FB_CFB_FILLRECT + select FB_CFB_IMAGEBLIT + +config FB_Q40 + bool + depends on (FB = y) && Q40 + default y + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + +config FB_AMIGA + tristate "Amiga native chipset support" + depends on FB && AMIGA + help + This is the frame buffer device driver for the builtin graphics + chipset found in Amigas. + + To compile this driver as a module, choose M here: the + module will be called amifb. + +config FB_AMIGA_OCS + bool "Amiga OCS chipset support" + depends on FB_AMIGA + help + This enables support for the original Agnus and Denise video chips, + found in the Amiga 1000 and most A500's and A2000's. If you intend + to run Linux on any of these systems, say Y; otherwise say N. + +config FB_AMIGA_ECS + bool "Amiga ECS chipset support" + depends on FB_AMIGA + help + This enables support for the Enhanced Chip Set, found in later + A500's, later A2000's, the A600, the A3000, the A3000T and CDTV. If + you intend to run Linux on any of these systems, say Y; otherwise + say N. + +config FB_AMIGA_AGA + bool "Amiga AGA chipset support" + depends on FB_AMIGA + help + This enables support for the Advanced Graphics Architecture (also + known as the AGA or AA) Chip Set, found in the A1200, A4000, A4000T + and CD32. If you intend to run Linux on any of these systems, say Y; + otherwise say N. + +config FB_CYBER + tristate "Amiga CyberVision 64 support" + depends on FB && ZORRO && BROKEN + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This enables support for the Cybervision 64 graphics card from + Phase5. Please note that its use is not all that intuitive (i.e. if + you have any questions, be sure to ask!). Say N unless you have a + Cybervision 64 or plan to get one before you next recompile the + kernel. Please note that this driver DOES NOT support the + Cybervision 64/3D card, as they use incompatible video chips. + +config FB_VIRGE + bool "Amiga CyberVision 64/3D support " + depends on (FB = y) && ZORRO && BROKEN + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This enables support for the Cybervision 64/3D graphics card from + Phase5. Please note that its use is not all that intuitive (i.e. if + you have any questions, be sure to ask!). Say N unless you have a + Cybervision 64/3D or plan to get one before you next recompile the + kernel. Please note that this driver DOES NOT support the older + Cybervision 64 card, as they use incompatible video chips. + +config FB_RETINAZ3 + tristate "Amiga Retina Z3 support" + depends on (FB = y) && ZORRO && BROKEN + help + This enables support for the Retina Z3 graphics card. Say N unless + you have a Retina Z3 or plan to get one before you next recompile + the kernel. + +config FB_FM2 + bool "Amiga FrameMaster II/Rainbow II support" + depends on (FB = y) && ZORRO + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Amiga FrameMaster + card from BSC (exhibited 1992 but not shipped as a CBM product). + +config FB_ARC + tristate "Arc Monochrome LCD board support" + depends on FB && X86 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This enables support for the Arc Monochrome LCD board. The board + is based on the KS-108 lcd controller and is typically a matrix + of 2*n chips. This driver was tested with a 128x64 panel. This + driver supports it for use with x86 SBCs through a 16 bit GPIO + interface (8 bit data, 8 bit control). If you anticipate using + this driver, say Y or M; otherwise say N. You must specify the + GPIO IO address to be used for setting control and data. + +config FB_ATARI + bool "Atari native chipset support" + depends on (FB = y) && ATARI && BROKEN + help + This is the frame buffer device driver for the builtin graphics + chipset found in Ataris. + +config FB_OF + bool "Open Firmware frame buffer device support" + depends on (FB = y) && (PPC64 || PPC_OF) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES + help + Say Y if you want support with Open Firmware for your graphics + board. + +config FB_CONTROL + bool "Apple \"control\" display support" + depends on (FB = y) && PPC_PMAC && PPC32 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES + help + This driver supports a frame buffer for the graphics adapter in the + Power Macintosh 7300 and others. + +config FB_PLATINUM + bool "Apple \"platinum\" display support" + depends on (FB = y) && PPC_PMAC && PPC32 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES + help + This driver supports a frame buffer for the "platinum" graphics + adapter in some Power Macintoshes. + +config FB_VALKYRIE + bool "Apple \"valkyrie\" display support" + depends on (FB = y) && (MAC || (PPC_PMAC && PPC32)) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES + help + This driver supports a frame buffer for the "valkyrie" graphics + adapter in some Power Macintoshes. + +config FB_CT65550 + bool "Chips 65550 display support" + depends on (FB = y) && PPC32 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Chips & Technologies + 65550 graphics chip in PowerBooks. + +config FB_ASILIANT + bool "Asiliant (Chips) 69000 display support" + depends on (FB = y) && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Asiliant 69030 chipset + +config FB_IMSTT + bool "IMS Twin Turbo display support" + depends on (FB = y) && PCI + select FB_CFB_IMAGEBLIT + select FB_MACMODES if PPC + help + The IMS Twin Turbo is a PCI-based frame buffer card bundled with + many Macintosh and compatible computers. + +config FB_VGA16 + tristate "VGA 16-color graphics support" + depends on FB && (X86 || PPC) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for VGA 16 color graphic + cards. Say Y if you have such a card. + + To compile this driver as a module, choose M here: the + module will be called vga16fb. + +config FB_STI + tristate "HP STI frame buffer device support" + depends on FB && PARISC + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + default y + ---help--- + STI refers to the HP "Standard Text Interface" which is a set of + BIOS routines contained in a ROM chip in HP PA-RISC based machines. + Enabling this option will implement the linux framebuffer device + using calls to the STI BIOS routines for initialisation. + + If you enable this option, you will get a planar framebuffer device + /dev/fb which will work on the most common HP graphic cards of the + NGLE family, including the artist chips (in the 7xx and Bxxx series), + HCRX, HCRX24, CRX, CRX24 and VisEG series. + + It is safe to enable this option, so you should probably say "Y". + +config FB_MAC + bool "Generic Macintosh display support" + depends on (FB = y) && MAC + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES + +# bool ' Apple DAFB display support' CONFIG_FB_DAFB +config FB_HP300 + bool + depends on (FB = y) && HP300 + select FB_CFB_FILLRECT + select FB_CFB_IMAGEBLIT + default y + +config FB_TGA + tristate "TGA framebuffer support" + depends on FB && ALPHA + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select BITREVERSE + help + This is the frame buffer device driver for generic TGA graphic + cards. Say Y if you have one of those. + +config FB_VESA + bool "VESA VGA graphics support" + depends on (FB = y) && X86 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select VIDEO_SELECT + help + This is the frame buffer device driver for generic VESA 2.0 + compliant graphic cards. The older VESA 1.2 cards are not supported. + You will get a boot time penguin logo at no additional cost. Please + read . If unsure, say Y. + +config FB_IMAC + bool "Intel-based Macintosh Framebuffer Support" + depends on (FB = y) && X86 && EFI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Intel-based Macintosh + +config FB_HGA + tristate "Hercules mono graphics support" + depends on FB && X86 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Say Y here if you have a Hercules mono graphics card. + + To compile this driver as a module, choose M here: the + module will be called hgafb. + + As this card technology is 15 years old, most people will answer N + here. + +config FB_HGA_ACCEL + bool "Hercules mono Acceleration functions (EXPERIMENTAL)" + depends on FB_HGA && EXPERIMENTAL + ---help--- + This will compile the Hercules mono graphics with + acceleration functions. + +config FB_SGIVW + tristate "SGI Visual Workstation framebuffer support" + depends on FB && X86_VISWS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + SGI Visual Workstation support for framebuffer graphics. + +config FB_GBE + bool "SGI Graphics Backend frame buffer support" + depends on (FB = y) && (SGI_IP32 || X86_VISWS) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for SGI Graphics Backend. + This chip is used in SGI O2 and Visual Workstation 320/540. + +config FB_GBE_MEM + int "Video memory size in MB" + depends on FB_GBE + default 4 + help + This is the amount of memory reserved for the framebuffer, + which can be any value between 1MB and 8MB. + +config FB_SUN3 + bool "Sun3 framebuffer support" + depends on (FB = y) && (SUN3 || SUN3X) && BROKEN + +config FB_SBUS + bool "SBUS and UPA framebuffers" + depends on (FB = y) && SPARC + help + Say Y if you want support for SBUS or UPA based frame buffer device. + +config FB_BW2 + bool "BWtwo support" + depends on (FB = y) && (SPARC && FB_SBUS || (SUN3 || SUN3X) && FB_SUN3) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the BWtwo frame buffer. + +config FB_CG3 + bool "CGthree support" + depends on (FB = y) && (SPARC && FB_SBUS || (SUN3 || SUN3X) && FB_SUN3) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the CGthree frame buffer. + +config FB_CG6 + bool "CGsix (GX,TurboGX) support" + depends on (FB = y) && (SPARC && FB_SBUS || (SUN3 || SUN3X) && FB_SUN3) + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the CGsix (GX, TurboGX) + frame buffer. + +config FB_PVR2 + tristate "NEC PowerVR 2 display support" + depends on FB && SH_DREAMCAST + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Say Y here if you have a PowerVR 2 card in your box. If you plan to + run linux on your Dreamcast, you will have to say Y here. + This driver may or may not work on other PowerVR 2 cards, but is + totally untested. Use at your own risk. If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called pvr2fb. + + You can pass several parameters to the driver at boot time or at + module load time. The parameters look like "video=pvr2:XXX", where + the meaning of XXX can be found at the end of the main source file + (). Please see the file + . + +config FB_EPSON1355 + bool "Epson 1355 framebuffer support" + depends on (FB = y) && (SUPERH || ARCH_CEIVA) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Build in support for the SED1355 Epson Research Embedded RAMDAC + LCD/CRT Controller (since redesignated as the S1D13505) as a + framebuffer. Product specs at + . + +config FB_S1D13XXX + tristate "Epson S1D13XXX framebuffer support" + depends on FB + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Support for S1D13XXX framebuffer device family (currently only + working with S1D13806). Product specs at + + +config FB_NVIDIA + tristate "nVidia Framebuffer Support" + depends on FB && PCI + select I2C_ALGOBIT if FB_NVIDIA_I2C + select I2C if FB_NVIDIA_I2C + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select BITREVERSE + help + This driver supports graphics boards with the nVidia chips, TNT + and newer. For very old chipsets, such as the RIVA128, then use + the rivafb. + Say Y if you have such a graphics board. + + To compile this driver as a module, choose M here: the + module will be called nvidiafb. + +config FB_NVIDIA_I2C + bool "Enable DDC Support" + depends on FB_NVIDIA + help + This enables I2C support for nVidia Chipsets. This is used + only for getting EDID information from the attached display + allowing for robust video mode handling and switching. + + Because fbdev-2.6 requires that drivers must be able to + independently validate video mode parameters, you should say Y + here. + +config FB_NVIDIA_BACKLIGHT + bool "Support for backlight control" + depends on FB_NVIDIA && PMAC_BACKLIGHT + select FB_BACKLIGHT + default y + help + Say Y here if you want to control the backlight of your display. + +config FB_RIVA + tristate "nVidia Riva support" + depends on FB && PCI + select I2C_ALGOBIT if FB_RIVA_I2C + select I2C if FB_RIVA_I2C + select FB_DDC if FB_RIVA_I2C + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select BITREVERSE + help + This driver supports graphics boards with the nVidia Riva/Geforce + chips. + Say Y if you have such a graphics board. + + To compile this driver as a module, choose M here: the + module will be called rivafb. + +config FB_RIVA_I2C + bool "Enable DDC Support" + depends on FB_RIVA + help + This enables I2C support for nVidia Chipsets. This is used + only for getting EDID information from the attached display + allowing for robust video mode handling and switching. + + Because fbdev-2.6 requires that drivers must be able to + independently validate video mode parameters, you should say Y + here. + +config FB_RIVA_DEBUG + bool "Lots of debug output from Riva(nVidia) driver" + depends on FB_RIVA + default n + help + Say Y here if you want the Riva driver to output all sorts + of debugging information to provide to the maintainer when + something goes wrong. + +config FB_RIVA_BACKLIGHT + bool "Support for backlight control" + depends on FB_RIVA && PMAC_BACKLIGHT + select FB_BACKLIGHT + default y + help + Say Y here if you want to control the backlight of your display. + +config FB_I810 + tristate "Intel 810/815 support (EXPERIMENTAL)" + depends on FB && EXPERIMENTAL && PCI && X86_32 + select AGP + select AGP_INTEL + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This driver supports the on-board graphics built in to the Intel 810 + and 815 chipsets. Say Y if you have and plan to use such a board. + + To compile this driver as a module, choose M here: the + module will be called i810fb. + + For more information, please read + + +config FB_I810_GTF + bool "use VESA Generalized Timing Formula" + depends on FB_I810 + help + If you say Y, then the VESA standard, Generalized Timing Formula + or GTF, will be used to calculate the required video timing values + per video mode. Since the GTF allows nondiscrete timings + (nondiscrete being a range of values as opposed to discrete being a + set of values), you'll be able to use any combination of horizontal + and vertical resolutions, and vertical refresh rates without having + to specify your own timing parameters. This is especially useful + to maximize the performance of an aging display, or if you just + have a display with nonstandard dimensions. A VESA compliant + monitor is recommended, but can still work with non-compliant ones. + If you need or want this, then select this option. The timings may + not be compliant with Intel's recommended values. Use at your own + risk. + + If you say N, the driver will revert to discrete video timings + using a set recommended by Intel in their documentation. + + If unsure, say N. + +config FB_I810_I2C + bool "Enable DDC Support" + depends on FB_I810 && FB_I810_GTF + select I2C + select I2C_ALGOBIT + select FB_DDC + help + +config FB_INTEL + tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)" + depends on FB && EXPERIMENTAL && PCI && X86 + select AGP + select AGP_INTEL + select I2C_ALGOBIT if FB_INTEL_I2C + select I2C if FB_INTEL_I2C + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This driver supports the on-board graphics built in to the Intel + 830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM chipsets. + Say Y if you have and plan to use such a board. + + If you say Y here and want DDC/I2C support you must first say Y to + "I2C support" and "I2C bit-banging support" in the character devices + section. + + If you say M here then "I2C support" and "I2C bit-banging support" + can be build either as modules or built-in. + + To compile this driver as a module, choose M here: the + module will be called intelfb. + + For more information, please read + +config FB_INTEL_DEBUG + bool "Intel driver Debug Messages" + depends on FB_INTEL + ---help--- + Say Y here if you want the Intel driver to output all sorts + of debugging information to provide to the maintainer when + something goes wrong. + +config FB_INTEL_I2C + bool "DDC/I2C for Intel framebuffer support" + depends on FB_INTEL + default y + help + Say Y here if you want DDC/I2C support for your on-board Intel graphics. + +config FB_MATROX + tristate "Matrox acceleration" + depends on FB && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_TILEBLITTING + select FB_MACMODES if PPC_PMAC + ---help--- + Say Y here if you have a Matrox Millennium, Matrox Millennium II, + Matrox Mystique, Matrox Mystique 220, Matrox Productiva G100, Matrox + Mystique G200, Matrox Millennium G200, Matrox Marvel G200 video, + Matrox G400, G450 or G550 card in your box. + + To compile this driver as a module, choose M here: the + module will be called matroxfb. + + You can pass several parameters to the driver at boot time or at + module load time. The parameters look like "video=matrox:XXX", and + are described in . + +config FB_MATROX_MILLENIUM + bool "Millennium I/II support" + depends on FB_MATROX + help + Say Y here if you have a Matrox Millennium or Matrox Millennium II + video card. If you select "Advanced lowlevel driver options" below, + you should check 4 bpp packed pixel, 8 bpp packed pixel, 16 bpp + packed pixel, 24 bpp packed pixel and 32 bpp packed pixel. You can + also use font widths different from 8. + +config FB_MATROX_MYSTIQUE + bool "Mystique support" + depends on FB_MATROX + help + Say Y here if you have a Matrox Mystique or Matrox Mystique 220 + video card. If you select "Advanced lowlevel driver options" below, + you should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp + packed pixel and 32 bpp packed pixel. You can also use font widths + different from 8. + +config FB_MATROX_G + bool "G100/G200/G400/G450/G550 support" + depends on FB_MATROX + ---help--- + Say Y here if you have a Matrox G100, G200, G400, G450 or G550 based + video card. If you select "Advanced lowlevel driver options", you + should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp packed + pixel and 32 bpp packed pixel. You can also use font widths + different from 8. + + If you need support for G400 secondary head, you must first say Y to + "I2C support" in the character devices section, and then to + "Matrox I2C support" and "G400 second head support" here in the + framebuffer section. G450/G550 secondary head and digital output + are supported without additional modules. + + The driver starts in monitor mode. You must use the matroxset tool + (available at ) to + swap primary and secondary head outputs, or to change output mode. + Secondary head driver always start in 640x480 resolution and you + must use fbset to change it. + + Do not forget that second head supports only 16 and 32 bpp + packed pixels, so it is a good idea to compile them into the kernel + too. You can use only some font widths, as the driver uses generic + painting procedures (the secondary head does not use acceleration + engine). + + G450/G550 hardware can display TV picture only from secondary CRTC, + and it performs no scaling, so picture must have 525 or 625 lines. + +config FB_MATROX_I2C + tristate "Matrox I2C support" + depends on FB_MATROX && I2C + select I2C_ALGOBIT + ---help--- + This drivers creates I2C buses which are needed for accessing the + DDC (I2C) bus present on all Matroxes, an I2C bus which + interconnects Matrox optional devices, like MGA-TVO on G200 and + G400, and the secondary head DDC bus, present on G400 only. + + You can say Y or M here if you want to experiment with monitor + detection code. You must say Y or M here if you want to use either + second head of G400 or MGA-TVO on G200 or G400. + + If you compile it as module, it will create a module named + i2c-matroxfb. + +config FB_MATROX_MAVEN + tristate "G400 second head support" + depends on FB_MATROX_G && FB_MATROX_I2C + ---help--- + WARNING !!! This support does not work with G450 !!! + + Say Y or M here if you want to use a secondary head (meaning two + monitors in parallel) on G400 or MGA-TVO add-on on G200. Secondary + head is not compatible with accelerated XFree 3.3.x SVGA servers - + secondary head output is blanked while you are in X. With XFree + 3.9.17 preview you can use both heads if you use SVGA over fbdev or + the fbdev driver on first head and the fbdev driver on second head. + + If you compile it as module, two modules are created, + matroxfb_crtc2 and matroxfb_maven. Matroxfb_maven is needed for + both G200 and G400, matroxfb_crtc2 is needed only by G400. You must + also load i2c-matroxfb to get it to run. + + The driver starts in monitor mode and you must use the matroxset + tool (available at + ) to switch it to + PAL or NTSC or to swap primary and secondary head outputs. + Secondary head driver also always start in 640x480 resolution, you + must use fbset to change it. + + Also do not forget that second head supports only 16 and 32 bpp + packed pixels, so it is a good idea to compile them into the kernel + too. You can use only some font widths, as the driver uses generic + painting procedures (the secondary head does not use acceleration + engine). + +config FB_MATROX_MULTIHEAD + bool "Multihead support" + depends on FB_MATROX + ---help--- + Say Y here if you have more than one (supported) Matrox device in + your computer and you want to use all of them for different monitors + ("multihead"). If you have only one device, you should say N because + the driver compiled with Y is larger and a bit slower, especially on + ia32 (ix86). + + If you said M to "Matrox unified accelerated driver" and N here, you + will still be able to use several Matrox devices simultaneously: + insert several instances of the module matroxfb into the kernel + with insmod, supplying the parameter "dev=N" where N is 0, 1, etc. + for the different Matrox devices. This method is slightly faster but + uses 40 KB of kernel memory per Matrox card. + + There is no need for enabling 'Matrox multihead support' if you have + only one Matrox card in the box. + +config FB_RADEON + tristate "ATI Radeon display support" + depends on FB && PCI + select I2C_ALGOBIT if FB_RADEON_I2C + select I2C if FB_RADEON_I2C + select FB_DDC if FB_RADEON_I2C + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES if PPC_OF + help + Choose this option if you want to use an ATI Radeon graphics card as + a framebuffer device. There are both PCI and AGP versions. You + don't need to choose this to run the Radeon in plain VGA mode. + + If you say Y here and want DDC/I2C support you must first say Y to + "I2C support" and "I2C bit-banging support" in the character devices + section. + + If you say M here then "I2C support" and "I2C bit-banging support" + can be build either as modules or built-in. + + There is a product page at + http://apps.ati.com/ATIcompare/ + +config FB_RADEON_I2C + bool "DDC/I2C for ATI Radeon support" + depends on FB_RADEON + default y + help + Say Y here if you want DDC/I2C support for your Radeon board. + +config FB_RADEON_BACKLIGHT + bool "Support for backlight control" + depends on FB_RADEON && PMAC_BACKLIGHT + select FB_BACKLIGHT + default y + help + Say Y here if you want to control the backlight of your display. + +config FB_RADEON_DEBUG + bool "Lots of debug output from Radeon driver" + depends on FB_RADEON + default n + help + Say Y here if you want the Radeon driver to output all sorts + of debugging information to provide to the maintainer when + something goes wrong. + +config FB_ATY128 + tristate "ATI Rage128 display support" + depends on FB && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES if PPC_PMAC + help + This driver supports graphics boards with the ATI Rage128 chips. + Say Y if you have such a graphics board and read + . + + To compile this driver as a module, choose M here: the + module will be called aty128fb. + +config FB_ATY128_BACKLIGHT + bool "Support for backlight control" + depends on FB_ATY128 && PMAC_BACKLIGHT + select FB_BACKLIGHT + default y + help + Say Y here if you want to control the backlight of your display. + +config FB_ATY + tristate "ATI Mach64 display support" if PCI || ATARI + depends on FB && !SPARC32 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + select FB_MACMODES if PPC + help + This driver supports graphics boards with the ATI Mach64 chips. + Say Y if you have such a graphics board. + + To compile this driver as a module, choose M here: the + module will be called atyfb. + +config FB_ATY_CT + bool "Mach64 CT/VT/GT/LT (incl. 3D RAGE) support" + depends on PCI && FB_ATY + default y if SPARC64 && FB_PCI + help + Say Y here to support use of ATI's 64-bit Rage boards (or other + boards based on the Mach64 CT, VT, GT, and LT chipsets) as a + framebuffer device. The ATI product support page for these boards + is at . + +config FB_ATY_GENERIC_LCD + bool "Mach64 generic LCD support (EXPERIMENTAL)" + depends on FB_ATY_CT + help + Say Y if you have a laptop with an ATI Rage LT PRO, Rage Mobility, + Rage XC, or Rage XL chipset. + +config FB_ATY_GX + bool "Mach64 GX support" if PCI + depends on FB_ATY + default y if ATARI + help + Say Y here to support use of the ATI Mach64 Graphics Expression + board (or other boards based on the Mach64 GX chipset) as a + framebuffer device. The ATI product support page for these boards + is at + . + +config FB_ATY_BACKLIGHT + bool "Support for backlight control" + depends on FB_ATY && PMAC_BACKLIGHT + select FB_BACKLIGHT + default y + help + Say Y here if you want to control the backlight of your display. + +config FB_S3TRIO + bool "S3 Trio display support" + depends on (FB = y) && PPC && BROKEN + help + If you have a S3 Trio say Y. Say N for S3 Virge. + +config FB_SAVAGE + tristate "S3 Savage support" + depends on FB && PCI && EXPERIMENTAL + select I2C_ALGOBIT if FB_SAVAGE_I2C + select I2C if FB_SAVAGE_I2C + select FB_DDC if FB_SAVAGE_I2C + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This driver supports notebooks and computers with S3 Savage PCI/AGP + chips. + + Say Y if you have such a graphics card. + + To compile this driver as a module, choose M here; the module + will be called savagefb. + +config FB_SAVAGE_I2C + bool "Enable DDC2 Support" + depends on FB_SAVAGE + help + This enables I2C support for S3 Savage Chipsets. This is used + only for getting EDID information from the attached display + allowing for robust video mode handling and switching. + + Because fbdev-2.6 requires that drivers must be able to + independently validate video mode parameters, you should say Y + here. + +config FB_SAVAGE_ACCEL + bool "Enable Console Acceleration" + depends on FB_SAVAGE + default n + help + This option will compile in console acceleration support. If + the resulting framebuffer console has bothersome glitches, then + choose N here. + +config FB_SIS + tristate "SiS/XGI display support" + depends on FB && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the SiS 300, 315, 330 + and 340 series as well as XGI V3XT, V5, V8, Z7 graphics chipsets. + Specs available at and . + + To compile this driver as a module, choose M here; the module + will be called sisfb. + +config FB_SIS_300 + bool "SiS 300 series support" + depends on FB_SIS + help + Say Y here to support use of the SiS 300/305, 540, 630 and 730. + +config FB_SIS_315 + bool "SiS 315/330/340 series and XGI support" + depends on FB_SIS + help + Say Y here to support use of the SiS 315, 330 and 340 series + (315/H/PRO, 55x, 650, 651, 740, 330, 661, 741, 760, 761) as well + as XGI V3XT, V5, V8 and Z7. + +config FB_NEOMAGIC + tristate "NeoMagic display support" + depends on FB && PCI + select FB_MODE_HELPERS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This driver supports notebooks with NeoMagic PCI chips. + Say Y if you have such a graphics card. + + To compile this driver as a module, choose M here: the + module will be called neofb. + +config FB_KYRO + tristate "IMG Kyro support" + depends on FB && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Say Y here if you have a STG4000 / Kyro / PowerVR 3 based + graphics board. + + To compile this driver as a module, choose M here: the + module will be called kyrofb. + +config FB_3DFX + tristate "3Dfx Banshee/Voodoo3 display support" + depends on FB && PCI + select FB_CFB_IMAGEBLIT + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + help + This driver supports graphics boards with the 3Dfx Banshee/Voodoo3 + chips. Say Y if you have such a graphics board. + + To compile this driver as a module, choose M here: the + module will be called tdfxfb. + +config FB_3DFX_ACCEL + bool "3Dfx Banshee/Voodoo3 Acceleration functions (EXPERIMENTAL)" + depends on FB_3DFX && EXPERIMENTAL + ---help--- + This will compile the 3Dfx Banshee/Voodoo3 frame buffer device + with acceleration functions. + + +config FB_VOODOO1 + tristate "3Dfx Voodoo Graphics (sst1) support" + depends on FB && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or + Voodoo2 (cvg) based graphics card. + + To compile this driver as a module, choose M here: the + module will be called sstfb. + + WARNING: Do not use any application that uses the 3D engine + (namely glide) while using this driver. + Please read the for supported + options and other important info support. + +config FB_CYBLA + tristate "Cyberblade/i1 support" + depends on FB && PCI && X86_32 && !64BIT + select FB_CFB_IMAGEBLIT + select VIDEO_SELECT + ---help--- + This driver is supposed to support the Trident Cyberblade/i1 + graphics core integrated in the VIA VT8601A North Bridge, + also known as VIA Apollo PLE133. + + Status: + - Developed, tested and working on EPIA 5000 and EPIA 800. + - Does work reliable on all systems with CRT/LCD connected to + normal VGA ports. + - Should work on systems that do use the internal LCD port, but + this is absolutely not tested. + + Character imageblit, copyarea and rectangle fill are hw accelerated, + ypan scrolling is used by default. + + Please do read . + + To compile this driver as a module, choose M here: the + module will be called cyblafb. + +config FB_TRIDENT + tristate "Trident support" + depends on FB && PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + This driver is supposed to support graphics boards with the + Trident CyberXXXX/Image/CyberBlade chips mostly found in laptops + but also on some motherboards. For more information, read + + + Cyberblade/i1 support will be removed soon, use the cyblafb driver + instead. + + Say Y if you have such a graphics board. + + + To compile this driver as a module, choose M here: the + module will be called tridentfb. + +config FB_TRIDENT_ACCEL + bool "Trident Acceleration functions (EXPERIMENTAL)" + depends on FB_TRIDENT && EXPERIMENTAL + ---help--- + This will compile the Trident frame buffer device with + acceleration functions. + +config FB_PM3 + tristate "Permedia3 support" + depends on FB && PCI && BROKEN + help + This is the frame buffer device driver for the 3DLabs Permedia3 + chipset, used in Formac ProFormance III, 3DLabs Oxygen VX1 & + similar boards, 3DLabs Permedia3 Create!, Appian Jeronimo 2000 + and maybe other boards. + +config FB_AU1100 + bool "Au1100 LCD Driver" + depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y + +config FB_AU1200 + bool "Au1200 LCD Driver" + depends on FB && MIPS && SOC_AU1200 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the framebuffer driver for the AMD Au1200 SOC. It can drive + various panels and CRTs by passing in kernel cmd line option + au1200fb:panel=. + +source "drivers/video/geode/Kconfig" + +config FB_FFB + bool "Creator/Creator3D/Elite3D support" + depends on FB_SBUS && SPARC64 + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Creator, Creator3D, + and Elite3D graphics boards. + +config FB_TCX + bool "TCX (SS4/SS5 only) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the TCX 24/8bit frame + buffer. + +config FB_CG14 + bool "CGfourteen (SX) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the CGfourteen frame + buffer on Desktop SPARCsystems with the SX graphics option. + +config FB_P9100 + bool "P9100 (Sparcbook 3 only) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the P9100 card + supported on Sparcbook 3 machines. + +config FB_LEO + bool "Leo (ZX) support" + depends on FB_SBUS + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the SBUS-based Sun ZX + (leo) frame buffer cards. + +config FB_PCI + bool "PCI framebuffers" + depends on (FB = y) && PCI && SPARC + +config FB_IGA + bool "IGA 168x display support" + depends on SPARC32 && FB_PCI + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the framebuffer device for the INTERGRAPHICS 1680 and + successor frame buffer cards. + +config FB_HIT + tristate "HD64461 Frame Buffer support" + depends on FB && HD64461 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + This is the frame buffer device driver for the Hitachi HD64461 LCD + frame buffer card. + +config FB_PMAG_AA + bool "PMAG-AA TURBOchannel framebuffer support" + depends on (FB = y) && TC + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Support for the PMAG-AA TURBOchannel framebuffer card (1280x1024x1) + used mainly in the MIPS-based DECstation series. + +config FB_PMAG_BA + bool "PMAG-BA TURBOchannel framebuffer support" + depends on (FB = y) && TC + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Support for the PMAG-BA TURBOchannel framebuffer card (1024x864x8) + used mainly in the MIPS-based DECstation series. + +config FB_PMAGB_B + bool "PMAGB-B TURBOchannel framebuffer support" + depends on (FB = y) && TC + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Support for the PMAGB-B TURBOchannel framebuffer card used mainly + in the MIPS-based DECstation series. The card is currently only + supported in 1280x1024x8 mode. + +config FB_MAXINE + bool "Maxine (Personal DECstation) onboard framebuffer support" + depends on (FB = y) && MACH_DECSTATION + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Support for the onboard framebuffer (1024x768x8) in the Personal + DECstation series (Personal DECstation 5000/20, /25, /33, /50, + Codename "Maxine"). + +config FB_TX3912 + bool "TMPTX3912/PR31700 frame buffer support" + depends on (FB = y) && NINO + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + The TX3912 is a Toshiba RISC processor based on the MIPS 3900 core + see . + + Say Y here to enable kernel support for the on-board framebuffer. + +config FB_G364 + bool "G364 frame buffer support" + depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + The G364 driver is the framebuffer used in MIPS Magnum 4000 and + Olivetti M700-10 systems. + +config FB_68328 + bool "Motorola 68328 native frame buffer support" + depends on FB && (M68328 || M68EZ328 || M68VZ328) + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + help + Say Y here if you want to support the built-in frame buffer of + the Motorola 68328 CPU family. + +config FB_PXA + tristate "PXA LCD framebuffer support" + depends on FB && ARCH_PXA + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Frame buffer driver for the built-in LCD controller in the Intel + PXA2x0 processor. + + This driver is also available as a module ( = code which can be + inserted and removed from the running kernel whenever you want). The + module will be called pxafb. If you want to compile it as a module, + say M here and read . + + If unsure, say N. + +config FB_PXA_PARAMETERS + bool "PXA LCD command line parameters" + default n + depends on FB_PXA + ---help--- + Enable the use of kernel command line or module parameters + to configure the physical properties of the LCD panel when + using the PXA LCD driver. + + This option allows you to override the panel parameters + supplied by the platform in order to support multiple + different models of flatpanel. If you will only be using a + single model of flatpanel then you can safely leave this + option disabled. + + describes the available parameters. + +config FB_MBX + tristate "2700G LCD framebuffer support" + depends on FB && ARCH_PXA + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Framebuffer driver for the Intel 2700G (Marathon) Graphics + Accelerator + +config FB_MBX_DEBUG + bool "Enable debugging info via debugfs" + depends on FB_MBX && DEBUG_FS + default n + ---help--- + Enable this if you want debugging information using the debug + filesystem (debugfs) + + If unsure, say N. + +config FB_W100 + tristate "W100 frame buffer support" + depends on FB && PXA_SHARPSL + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Frame buffer driver for the w100 as found on the Sharp SL-Cxx series. + + This driver is also available as a module ( = code which can be + inserted and removed from the running kernel whenever you want). The + module will be called w100fb. If you want to compile it as a module, + say M here and read . + + If unsure, say N. + +config FB_S3C2410 + tristate "S3C2410 LCD framebuffer support" + depends on FB && ARCH_S3C2410 + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Frame buffer driver for the built-in LCD controller in the Samsung + S3C2410 processor. + + This driver is also available as a module ( = code which can be + inserted and removed from the running kernel whenever you want). The + module will be called s3c2410fb. If you want to compile it as a module, + say M here and read . + + If unsure, say N. +config FB_S3C2410_DEBUG + bool "S3C2410 lcd debug messages" + depends on FB_S3C2410 + help + Turn on debugging messages. Note that you can set/unset at run time + through sysfs + +config FB_PNX4008_DUM + tristate "Display Update Module support on Philips PNX4008 board" + depends on FB && ARCH_PNX4008 + ---help--- + Say Y here to enable support for PNX4008 Display Update Module (DUM) + +config FB_PNX4008_DUM_RGB + tristate "RGB Framebuffer support on Philips PNX4008 board" + depends on FB_PNX4008_DUM + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Say Y here to enable support for PNX4008 RGB Framebuffer + +config FB_IBM_GXT4500 + tristate "Framebuffer support for IBM GXT4500P adaptor" + depends on PPC + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + Say Y here to enable support for the IBM GXT4500P display + adaptor, found on some IBM System P (pSeries) machines. + +config FB_VIRTUAL + tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)" + depends on FB + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT + ---help--- + This is a `virtual' frame buffer device. It operates on a chunk of + unswappable kernel memory instead of on the memory of a graphics + board. This means you cannot see any output sent to this frame + buffer device, while it does consume precious memory. The main use + of this frame buffer device is testing and debugging the frame + buffer subsystem. Do NOT enable it for normal systems! To protect + the innocent, it has to be enabled explicitly at boot time using the + kernel option `video=vfb:'. + + To compile this driver as a module, choose M here: the + module will be called vfb. In order to load it, you must use + the vfb_enable=1 option. + + If unsure, say N. +if VT + source "drivers/video/console/Kconfig" +endif + +if FB || SGI_NEWPORT_CONSOLE + source "drivers/video/logo/Kconfig" +endif + +if SYSFS + source "drivers/video/backlight/Kconfig" +endif + +endmenu + diff -urN -x CVS linux-2.6.20/drivers/video/Makefile linux-2.6.20-AT91/drivers/video/Makefile --- linux-2.6.20/drivers/video/Makefile 2007-07-13 11:48:43.000000000 -0500 +++ linux-2.6.20-AT91/drivers/video/Makefile 2007-07-12 14:43:37.000000000 -0500 @@ -101,6 +101,7 @@ obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o +obj-$(CONFIG_FB_EP93XX) += ep93xxfb.o # Platform or fallback drivers go here obj-$(CONFIG_FB_VESA) += vesafb.o diff -urN -x CVS linux-2.6.20/drivers/video/Makefile.orig linux-2.6.20-AT91/drivers/video/Makefile.orig --- linux-2.6.20/drivers/video/Makefile.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/Makefile.orig 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,111 @@ +# Makefile for the Linux video drivers. +# 5 Aug 1999, James Simmons, +# Rewritten to use lists instead of if-statements. + +# Each configuration option enables a list of files. + +obj-y += fb_notify.o +obj-$(CONFIG_FB) += fb.o +fb-y := fbmem.o fbmon.o fbcmap.o fbsysfs.o \ + modedb.o fbcvt.o +fb-objs := $(fb-y) + +obj-$(CONFIG_VT) += console/ +obj-$(CONFIG_LOGO) += logo/ +obj-$(CONFIG_SYSFS) += backlight/ + +obj-$(CONFIG_FB_CFB_FILLRECT) += cfbfillrect.o +obj-$(CONFIG_FB_CFB_COPYAREA) += cfbcopyarea.o +obj-$(CONFIG_FB_CFB_IMAGEBLIT) += cfbimgblt.o +obj-$(CONFIG_FB_MACMODES) += macmodes.o +obj-$(CONFIG_FB_DDC) += fb_ddc.o + +# Hardware specific drivers go first +obj-$(CONFIG_FB_RETINAZ3) += retz3fb.o +obj-$(CONFIG_FB_AMIGA) += amifb.o c2p.o +obj-$(CONFIG_FB_ARC) += arcfb.o +obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o +obj-$(CONFIG_FB_CYBER) += cyberfb.o +obj-$(CONFIG_FB_CYBER2000) += cyber2000fb.o +obj-$(CONFIG_FB_PM2) += pm2fb.o +obj-$(CONFIG_FB_PM3) += pm3fb.o + +obj-$(CONFIG_FB_MATROX) += matrox/ +obj-$(CONFIG_FB_RIVA) += riva/ vgastate.o +obj-$(CONFIG_FB_NVIDIA) += nvidia/ +obj-$(CONFIG_FB_ATY) += aty/ macmodes.o +obj-$(CONFIG_FB_ATY128) += aty/ macmodes.o +obj-$(CONFIG_FB_RADEON) += aty/ +obj-$(CONFIG_FB_SIS) += sis/ +obj-$(CONFIG_FB_KYRO) += kyro/ +obj-$(CONFIG_FB_SAVAGE) += savage/ +obj-$(CONFIG_FB_GEODE) += geode/ +obj-$(CONFIG_FB_MBX) += mbx/ +obj-$(CONFIG_FB_I810) += vgastate.o +obj-$(CONFIG_FB_NEOMAGIC) += neofb.o vgastate.o +obj-$(CONFIG_FB_VIRGE) += virgefb.o +obj-$(CONFIG_FB_3DFX) += tdfxfb.o +obj-$(CONFIG_FB_CONTROL) += controlfb.o +obj-$(CONFIG_FB_PLATINUM) += platinumfb.o +obj-$(CONFIG_FB_VALKYRIE) += valkyriefb.o +obj-$(CONFIG_FB_CT65550) += chipsfb.o +obj-$(CONFIG_FB_IMSTT) += imsttfb.o +obj-$(CONFIG_FB_S3TRIO) += S3triofb.o +obj-$(CONFIG_FB_FM2) += fm2fb.o +obj-$(CONFIG_FB_CYBLA) += cyblafb.o +obj-$(CONFIG_FB_TRIDENT) += tridentfb.o +obj-$(CONFIG_FB_STI) += stifb.o +obj-$(CONFIG_FB_FFB) += ffb.o sbuslib.o +obj-$(CONFIG_FB_CG6) += cg6.o sbuslib.o +obj-$(CONFIG_FB_CG3) += cg3.o sbuslib.o +obj-$(CONFIG_FB_BW2) += bw2.o sbuslib.o +obj-$(CONFIG_FB_CG14) += cg14.o sbuslib.o +obj-$(CONFIG_FB_P9100) += p9100.o sbuslib.o +obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o +obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o +obj-$(CONFIG_FB_SGIVW) += sgivwfb.o +obj-$(CONFIG_FB_ACORN) += acornfb.o +obj-$(CONFIG_FB_ATARI) += atafb.o +obj-$(CONFIG_FB_MAC) += macfb.o +obj-$(CONFIG_FB_HGA) += hgafb.o +obj-$(CONFIG_FB_IGA) += igafb.o +obj-$(CONFIG_FB_APOLLO) += dnfb.o +obj-$(CONFIG_FB_Q40) += q40fb.o +obj-$(CONFIG_FB_TGA) += tgafb.o +obj-$(CONFIG_FB_HP300) += hpfb.o +obj-$(CONFIG_FB_G364) += g364fb.o +obj-$(CONFIG_FB_SA1100) += sa1100fb.o +obj-$(CONFIG_FB_SUN3) += sun3fb.o +obj-$(CONFIG_FB_HIT) += hitfb.o +obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o +obj-$(CONFIG_FB_PVR2) += pvr2fb.o +obj-$(CONFIG_FB_VOODOO1) += sstfb.o +obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o +obj-$(CONFIG_FB_68328) += 68328fb.o +obj-$(CONFIG_FB_GBE) += gbefb.o +obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o +obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o +obj-$(CONFIG_FB_PXA) += pxafb.o +obj-$(CONFIG_FB_W100) += w100fb.o +obj-$(CONFIG_FB_AU1100) += au1100fb.o +obj-$(CONFIG_FB_AU1200) += au1200fb.o +obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o +obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o +obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o +obj-$(CONFIG_FB_MAXINE) += maxinefb.o +obj-$(CONFIG_FB_TX3912) += tx3912fb.o +obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o +obj-$(CONFIG_FB_IMX) += imxfb.o +obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o +obj-$(CONFIG_FB_PNX4008_DUM) += pnx4008/ +obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/ +obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o + +# Platform or fallback drivers go here +obj-$(CONFIG_FB_VESA) += vesafb.o +obj-$(CONFIG_FB_IMAC) += imacfb.o +obj-$(CONFIG_FB_VGA16) += vga16fb.o vgastate.o +obj-$(CONFIG_FB_OF) += offb.o + +# the test framebuffer is last +obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff -urN -x CVS linux-2.6.20/drivers/video/Makefile.rej linux-2.6.20-AT91/drivers/video/Makefile.rej --- linux-2.6.20/drivers/video/Makefile.rej 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/drivers/video/Makefile.rej 2007-07-12 14:20:46.000000000 -0500 @@ -0,0 +1,16 @@ +*************** +*** 94,99 **** + obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o + obj-$(CONFIG_FB_IMX) += imxfb.o + obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o + + # Platform or fallback drivers go here + obj-$(CONFIG_FB_VESA) += vesafb.o +--- 94,100 ---- + obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o + obj-$(CONFIG_FB_IMX) += imxfb.o + obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o ++ obj-$(CONFIG_FB_EP93XX) += ep93xxfb.o + + # Platform or fallback drivers go here + obj-$(CONFIG_FB_VESA) += vesafb.o diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h --- linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h 2007-07-13 11:48:43.000000000 -0500 +++ linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h 2007-07-12 14:43:37.000000000 -0500 @@ -63,11 +63,16 @@ }; extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); -/* Ethernet (EMAC & MACB) */ + /* Ethernet */ struct at91_eth_data { u8 phy_irq_pin; /* PHY IRQ */ u8 is_rmii; /* using RMII interface? */ }; + +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) +#define eth_platform_data at91_eth_data +#endif + extern void __init at91_add_device_eth(struct at91_eth_data *data); #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) @@ -77,7 +82,7 @@ /* USB Host */ struct at91_usbh_data { u8 ports; /* number of ports on root hub */ - u8 vbus_pin[]; /* port power switch */ + u8 vbus_pin[]; /* port power switch */ }; extern void __init at91_add_device_usbh(struct at91_usbh_data *data); diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h~ linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h~ --- linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h~ 2007-07-12 14:21:22.000000000 -0500 @@ -0,0 +1,131 @@ +/* + * include/asm-arm/arch-at91rm9200/board.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * These are data structures found in platform_device.dev.platform_data, + * and describing board-specific data needed by drivers. For example, + * which pin is used for a given GPIO role. + * + * In 2.6, drivers should strongly avoid board-specific knowledge so + * that supporting new boards normally won't require driver patches. + * Most board-specific knowledge should be in arch/.../board-*.c files. + */ + +#ifndef __ASM_ARCH_BOARD_H +#define __ASM_ARCH_BOARD_H + +#include +#include +#include + + /* USB Device */ +struct at91_udc_data { + u8 vbus_pin; /* high == host powering us */ + u8 pullup_pin; /* high == D+ pulled up */ +}; +extern void __init at91_add_device_udc(struct at91_udc_data *data); + + /* Compact Flash */ +struct at91_cf_data { + u8 irq_pin; /* I/O IRQ */ + u8 det_pin; /* Card detect */ + u8 vcc_pin; /* power switching */ + u8 rst_pin; /* card reset */ + u8 chipselect; /* EBI Chip Select number */ +}; +extern void __init at91_add_device_cf(struct at91_cf_data *data); + + /* MMC / SD */ +struct at91_mmc_data { + u8 det_pin; /* card detect IRQ */ + unsigned slot_b:1; /* uses Slot B */ + unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ + u8 wp_pin; /* (SD) writeprotect detect */ + u8 vcc_pin; /* power switching (high == on) */ +}; +extern void __init at91_add_device_mmc(struct at91_mmc_data *data); + + /* Ethernet */ +struct at91_eth_data { + u8 phy_irq_pin; /* PHY IRQ */ + u8 is_rmii; /* using RMII interface? */ +}; + +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) +#define eth_platform_data at91_eth_data +#endif + +extern void __init at91_add_device_eth(struct at91_eth_data *data); + + /* USB Host */ +struct at91_usbh_data { + u8 ports; /* number of ports on root hub */ +}; +extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + + /* NAND / SmartMedia */ +struct at91_nand_data { + u8 enable_pin; /* chip enable */ + u8 det_pin; /* card detect */ + u8 rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + struct mtd_partition* (*partition_info)(int, int*); +}; +extern void __init at91_add_device_nand(struct at91_nand_data *data); + + /* I2C*/ +extern void __init at91_add_device_i2c(void); + + /* SPI */ +extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); + + /* Serial */ +struct at91_uart_config { + unsigned short console_tty; /* tty number of serial console */ + unsigned short nr_tty; /* number of serial tty's */ + short tty_map[]; /* map UART to tty number */ +}; +extern struct platform_device *atmel_default_console_device; +extern void __init at91_init_serial(struct at91_uart_config *config); + +struct atmel_uart_data { + short use_dma_tx; /* use transmit DMA? */ + short use_dma_rx; /* use receive DMA? */ + void __iomem *regs; /* virtual base address, if any */ +}; +extern void __init at91_add_device_serial(void); + + /* LEDs */ +extern u8 at91_leds_cpu; +extern u8 at91_leds_timer; +extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); + +struct at91_gpio_led { + u8 index; /* index of LED */ + char* name; /* name of LED */ + u8 gpio; /* AT91_PIN_xx */ + u8 flags; /* 1=active-high */ + char* trigger; /* default trigger */ +}; +extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr); + +#endif diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h.orig linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h.orig --- linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h.orig 2007-07-12 14:23:50.000000000 -0500 @@ -0,0 +1,136 @@ +/* + * include/asm-arm/arch-at91rm9200/board.h + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * These are data structures found in platform_device.dev.platform_data, + * and describing board-specific data needed by drivers. For example, + * which pin is used for a given GPIO role. + * + * In 2.6, drivers should strongly avoid board-specific knowledge so + * that supporting new boards normally won't require driver patches. + * Most board-specific knowledge should be in arch/.../board-*.c files. + */ + +#ifndef __ASM_ARCH_BOARD_H +#define __ASM_ARCH_BOARD_H + +#include +#include +#include + + /* USB Device */ +struct at91_udc_data { + u8 vbus_pin; /* high == host powering us */ + u8 pullup_pin; /* high == D+ pulled up */ +}; +extern void __init at91_add_device_udc(struct at91_udc_data *data); + + /* Compact Flash */ +struct at91_cf_data { + u8 irq_pin; /* I/O IRQ */ + u8 det_pin; /* Card detect */ + u8 vcc_pin; /* power switching */ + u8 rst_pin; /* card reset */ + u8 chipselect; /* EBI Chip Select number */ +}; +extern void __init at91_add_device_cf(struct at91_cf_data *data); + + /* MMC / SD */ +struct at91_mmc_data { + u8 det_pin; /* card detect IRQ */ + unsigned slot_b:1; /* uses Slot B */ + unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ + u8 wp_pin; /* (SD) writeprotect detect */ + u8 vcc_pin; /* power switching (high == on) */ +}; +extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); + + /* Ethernet */ +struct at91_eth_data { + u8 phy_irq_pin; /* PHY IRQ */ + u8 is_rmii; /* using RMII interface? */ +}; + +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) +#define eth_platform_data at91_eth_data +#endif + +extern void __init at91_add_device_eth(struct at91_eth_data *data); + +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) +#define eth_platform_data at91_eth_data +#endif + + /* USB Host */ +struct at91_usbh_data { + u8 ports; /* number of ports on root hub */ + u8 vbus_pin[]; /* port power switch */ +}; +extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + + /* NAND / SmartMedia */ +struct at91_nand_data { + u8 enable_pin; /* chip enable */ + u8 det_pin; /* card detect */ + u8 rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + struct mtd_partition* (*partition_info)(int, int*); +}; +extern void __init at91_add_device_nand(struct at91_nand_data *data); + + /* I2C*/ +extern void __init at91_add_device_i2c(void); + + /* SPI */ +extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); + + /* Serial */ +struct at91_uart_config { + unsigned short console_tty; /* tty number of serial console */ + unsigned short nr_tty; /* number of serial tty's */ + short tty_map[]; /* map UART to tty number */ +}; +extern struct platform_device *atmel_default_console_device; +extern void __init at91_init_serial(struct at91_uart_config *config); + +struct atmel_uart_data { + short use_dma_tx; /* use transmit DMA? */ + short use_dma_rx; /* use receive DMA? */ + void __iomem *regs; /* virtual base address, if any */ +}; +extern void __init at91_add_device_serial(void); + + /* LEDs */ +extern u8 at91_leds_cpu; +extern u8 at91_leds_timer; +extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); + +struct at91_gpio_led { + u8 index; /* index of LED */ + char* name; /* name of LED */ + u8 gpio; /* AT91_PIN_xx */ + u8 flags; /* 1=active-high */ + char* trigger; /* default trigger */ +}; +extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr); + +#endif diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h.rej linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h.rej --- linux-2.6.20/include/asm-arm/arch-at91rm9200/board.h.rej 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-at91rm9200/board.h.rej 2007-07-12 14:21:22.000000000 -0500 @@ -0,0 +1,44 @@ +*************** +*** 60,77 **** + u8 wp_pin; /* (SD) writeprotect detect */ + u8 vcc_pin; /* power switching (high == on) */ + }; +- extern void __init at91_add_device_mmc(struct at91_mmc_data *data); + +- /* Ethernet */ + struct at91_eth_data { + u8 phy_irq_pin; /* PHY IRQ */ + u8 is_rmii; /* using RMII interface? */ + }; + extern void __init at91_add_device_eth(struct at91_eth_data *data); + + /* USB Host */ + struct at91_usbh_data { + u8 ports; /* number of ports on root hub */ + }; + extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + +--- 60,82 ---- + u8 wp_pin; /* (SD) writeprotect detect */ + u8 vcc_pin; /* power switching (high == on) */ + }; ++ extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); + ++ /* Ethernet (EMAC & MACB) */ + struct at91_eth_data { + u8 phy_irq_pin; /* PHY IRQ */ + u8 is_rmii; /* using RMII interface? */ + }; + extern void __init at91_add_device_eth(struct at91_eth_data *data); + ++ #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) ++ #define eth_platform_data at91_eth_data ++ #endif ++ + /* USB Host */ + struct at91_usbh_data { + u8 ports; /* number of ports on root hub */ ++ u8 vbus_pin[]; /* port power switch */ + }; + extern void __init at91_add_device_usbh(struct at91_usbh_data *data); + diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h 2007-07-12 14:20:47.000000000 -0500 @@ -15,11 +15,11 @@ */ #define EP93XX_AHB_PHYS_BASE 0x80000000 -#define EP93XX_AHB_VIRT_BASE 0xfef00000 +#define EP93XX_AHB_VIRT_BASE 0xff000000 //0xfef00000 #define EP93XX_AHB_SIZE 0x00100000 #define EP93XX_APB_PHYS_BASE 0x80800000 -#define EP93XX_APB_VIRT_BASE 0xfed00000 +#define EP93XX_APB_VIRT_BASE 0xff800000 //0xfed00000 #define EP93XX_APB_SIZE 0x00200000 @@ -43,7 +43,132 @@ #define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) #define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) +#define EP93XX_IDE_REG(x) (EP93XX_IDE_BASE + (x)) +#define EP93XX_IDE_CTRL EP93XX_IDE_REG(0x0000) +#define EP93XX_IDE_CFG EP93XX_IDE_REG(0x0004) +#define EP93XX_IDE_DATAOUT EP93XX_IDE_REG(0x0010) +#define EP93XX_IDE_DATAIN EP93XX_IDE_REG(0x0014) + +#define EP93XX_IDE_CTRL_CS0n (1L << 0) +#define EP93XX_IDE_CTRL_CS1n (1L << 1) +#define EP93XX_IDE_CTRL_DA_MASK 0x1C +#define EP93XX_IDE_CTRL_DA(x) ((x << 2) & EP93XX_IDE_CTRL_DA_MASK) +#define EP93XX_IDE_CTRL_DA_CS_MASK (EP93XX_IDE_CTRL_DA_MASK | EP93XX_IDE_CTRL_CS0n | EP93XX_IDE_CTRL_CS1n) +#define EP93XX_IDE_CTRL_DA_CS(x) (((x)) & EP93XX_IDE_CTRL_DA_CS_MASK) +#define EP93XX_IDE_CTRL_DIORn (1L << 5) +#define EP93XX_IDE_CTRL_DIOWn (1L << 6) +#define EP93XX_IDE_CTRL_DASPn (1L << 7) +#define EP93XX_IDE_CTRL_DMARQ (1L << 8) +#define EP93XX_IDE_CTRL_INTRQ (1L << 9) +#define EP93XX_IDE_CTRL_IORDY (1L << 10) + +#define EP93XX_IDE_CFG_IDEEN (1L << 0) +#define EP93XX_IDE_CFG_PIO (1L << 1) +#define EP93XX_IDE_CFG_MDMA (1L << 2) +#define EP93XX_IDE_CFG_UDMA (1L << 3) +#define EP93XX_IDE_CFG_MODE(x) ((x & 0x0F) << 4) +#define EP93XX_IDE_CFG_WST(x) ((x & 0x03) << 8) + + + +/* Old IDE DMA defines */ +/* 800A_0000 - 800A_ffff: IDE Interface */ +#define IDE_OFFSET 0x0a0000 +#define IDE_BASE (EP93XX_AHB_VIRT_BASE+IDE_OFFSET) +#define IDECR (IDE_BASE+0x00) +#define IDECFG (IDE_BASE+0x04) +#define IDEMDMAOP (IDE_BASE+0x08) +#define IDEUDMAOP (IDE_BASE+0x0C) +#define IDEDATAOUT (IDE_BASE+0x10) +#define IDEDATAIN (IDE_BASE+0x14) +#define IDEMDMADATAOUT (IDE_BASE+0x18) +#define IDEMDMADATAIN (IDE_BASE+0x1C) +#define IDEUDMADATAOUT (IDE_BASE+0x20) +#define IDEUDMADATAIN (IDE_BASE+0x24) +#define IDEUDMASTATUS (IDE_BASE+0x28) +#define IDEUDMADEBUG (IDE_BASE+0x2C) +#define IDEUDMAWFST (IDE_BASE+0x30) +#define IDEUDMARFST (IDE_BASE+0x34) + +/***************************************************************************** + * + * Bit definitions for use with assembly code for the ide control register. + * + ****************************************************************************/ +#define IDECtrl_CS0n 0x00000001 +#define IDECtrl_CS1n 0x00000002 +#define IDECtrl_DA_MASK 0x0000001c +#define IDECtrl_DA_SHIFT 2 +#define IDECtrl_DIORn 0x00000020 +#define IDECtrl_DIOWn 0x00000040 +#define IDECtrl_DASPn 0x00000080 +#define IDECtrl_DMARQ 0x00000100 +#define IDECtrl_INTRQ 0x00000200 +#define IDECtrl_IORDY 0x00000400 + +#define IDECfg_IDEEN 0x00000001 +#define IDECfg_PIO 0x00000002 +#define IDECfg_MDMA 0x00000004 +#define IDECfg_UDMA 0x00000008 +#define IDECfg_MODE_MASK 0x000000f0 +#define IDECfg_MODE_SHIFT 4 +#define IDECfg_WST_MASK 0x00000300 +#define IDECfg_WST_SHIFT 8 + +#define IDEMDMAOp_MEN 0x00000001 +#define IDEMDMAOp_RWOP 0x00000002 + +#define IDEUDMAOp_UEN 0x00000001 +#define IDEUDMAOp_RWOP 0x00000002 + +#define IDEUDMASts_CS0n 0x00000001 +#define IDEUDMASts_CS1n 0x00000002 +#define IDEUDMASts_DA_MASK 0x0000001c +#define IDEUDMASts_DA_SHIFT 2 +#define IDEUDMASts_HSHD 0x00000020 +#define IDEUDMASts_STOP 0x00000040 +#define IDEUDMASts_DM 0x00000080 +#define IDEUDMASts_DDOE 0x00000100 +#define IDEUDMASts_DMARQ 0x00000200 +#define IDEUDMASts_DSDD 0x00000400 +#define IDEUDMASts_DMAide 0x00010000 +#define IDEUDMASts_INTide 0x00020000 +#define IDEUDMASts_SBUSY 0x00040000 +#define IDEUDMASts_NDO 0x01000000 +#define IDEUDMASts_NDI 0x02000000 +#define IDEUDMASts_N4X 0x04000000 + +#define IDEUDMADebug_RWOE 0x00000001 +#define IDEUDMADebug_RWPTR 0x00000002 +#define IDEUDMADebug_RWDR 0x00000004 +#define IDEUDMADebug_RROE 0x00000008 +#define IDEUDMADebug_RRPTR 0x00000010 +#define IDEUDMADebug_RRDR 0x00000020 + +#define IDEUDMAWrBufSts_HPTR_MASK 0x0000000f +#define IDEUDMAWrBufSts_HPTR_SHIFT 0 +#define IDEUDMAWrBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMAWrBufSts_TPTR_SHIFT 4 +#define IDEUDMAWrBufSts_EMPTY 0x00000100 +#define IDEUDMAWrBufSts_HOM 0x00000200 +#define IDEUDMAWrBufSts_NFULL 0x00000400 +#define IDEUDMAWrBufSts_FULL 0x00000800 +#define IDEUDMAWrBufSts_CRC_MASK 0xffff0000 +#define IDEUDMAWrBufSts_CRC_SHIFT 16 + +#define IDEUDMARdBufSts_HPTR_MASK 0x0000000f +#define IDEUDMARdBufSts_HPTR_SHIFT 0 +#define IDEUDMARdBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMARdBufSts_TPTR_SHIFT 4 +#define IDEUDMARdBufSts_EMPTY 0x00000100 +#define IDEUDMARdBufSts_HOM 0x00000200 +#define IDEUDMARdBufSts_NFULL 0x00000400 +#define IDEUDMARdBufSts_FULL 0x00000800 +#define IDEUDMARdBufSts_CRC_MASK 0xffff0000 +#define IDEUDMARdBufSts_CRC_SHIFT 16 + +/*----------------------------------old-------------------------------*/ #define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) #define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) @@ -67,6 +192,35 @@ #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) +/* Cirrus Defines */ +/* 8081_0000 - 8081_ffff: Timers */ +#define TIMERS_OFFSET 0x010000 +#define TIMERS_BASE (EP93XX_APB_VIRT_BASE+TIMERS_OFFSET) + +#define TIMER1LOAD (TIMERS_BASE+0x00) +#define TIMER1VALUE (TIMERS_BASE+0x04) +#define TIMER1CONTROL (TIMERS_BASE+0x08) +#define TIMER1CLEAR (TIMERS_BASE+0x0C) +#define TIMER1TEST (TIMERS_BASE+0x10) + +#define TIMER2LOAD (TIMERS_BASE+0x20) +#define TIMER2VALUE (TIMERS_BASE+0x24) +#define TIMER2CONTROL (TIMERS_BASE+0x28) +#define TIMER2CLEAR (TIMERS_BASE+0x2C) +#define TIMER2TEST (TIMERS_BASE+0x30) + +#define TIMER3LOAD (TIMERS_BASE+0x80) +#define TIMER3VALUE (TIMERS_BASE+0x84) +#define TIMER3CONTROL (TIMERS_BASE+0x88) +#define TIMER3CLEAR (TIMERS_BASE+0x8C) +#define TIMER3TEST (TIMERS_BASE+0x90) + +#define TTIMERBZCONT (TIMERS_BASE+0x40) + +#define TIMER4VALUELOW (TIMERS_BASE+0x60) +#define TIMER4VALUEHIGH (TIMERS_BASE+0x64) +/* End Cirrus Timer Defines */ + #define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) #define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) @@ -78,11 +232,79 @@ #define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) #define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c) #define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_A_INT_DEBOUNCE EP93XX_GPIO_REG(0xa8) #define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac) #define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0) #define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4) #define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) +#define EP93XX_GPIO_B_INT_DEBOUNCE EP93XX_GPIO_REG(0xc4) + +/* 8084_0000 - 8084_ffff: GPIO -- OLD cirrus GPIO defines */ +#define GPIO_OFFSET 0x040000 +#define GPIO_BASE (EP93XX_APB_VIRT_BASE+GPIO_OFFSET) +#define GPIO_PADR (GPIO_BASE+0x00) +#define GPIO_PBDR (GPIO_BASE+0x04) +#define GPIO_PCDR (GPIO_BASE+0x08) +#define GPIO_PDDR (GPIO_BASE+0x0C) +#define GPIO_PADDR (GPIO_BASE+0x10) +#define GPIO_PBDDR (GPIO_BASE+0x14) +#define GPIO_PCDDR (GPIO_BASE+0x18) +#define GPIO_PDDDR (GPIO_BASE+0x1C) +#define GPIO_PEDR (GPIO_BASE+0x20) +#define GPIO_PEDDR (GPIO_BASE+0x24) +// #define 0x8084.0028 Reserved +// #define 0x8084.002C Reserved +#define GPIO_PFDR (GPIO_BASE+0x30) +#define GPIO_PFDDR (GPIO_BASE+0x34) +#define GPIO_PGDR (GPIO_BASE+0x38) +#define GPIO_PGDDR (GPIO_BASE+0x3C) +#define GPIO_PHDR (GPIO_BASE+0x40) +#define GPIO_PHDDR (GPIO_BASE+0x44) +// #define 0x8084.0048 RAZ RAZ +#define GPIO_FINTTYPE1 (GPIO_BASE+0x4C) +#define GPIO_FINTTYPE2 (GPIO_BASE+0x50) +#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_FINTEN (GPIO_BASE+0x58) +#define GPIO_INTSTATUSF (GPIO_BASE+0x5C) +#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60) +#define GPIO_FDB (GPIO_BASE+0x64) +#define GPIO_PAPINDR (GPIO_BASE+0x68) +#define GPIO_PBPINDR (GPIO_BASE+0x6C) +#define GPIO_PCPINDR (GPIO_BASE+0x70) +#define GPIO_PDPINDR (GPIO_BASE+0x74) +#define GPIO_PEPINDR (GPIO_BASE+0x78) +#define GPIO_PFPINDR (GPIO_BASE+0x7C) +#define GPIO_PGPINDR (GPIO_BASE+0x80) +#define GPIO_PHPINDR (GPIO_BASE+0x84) +#define GPIO_AINTTYPE1 (GPIO_BASE+0x90) +#define GPIO_AINTTYPE2 (GPIO_BASE+0x94) +#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_AINTEN (GPIO_BASE+0x9C) +#define GPIO_INTSTATUSA (GPIO_BASE+0xA0) +#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4) +#define GPIO_ADB (GPIO_BASE+0xA8) +#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC) +#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0) +#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_BINTEN (GPIO_BASE+0xB8) +#define GPIO_INTSTATUSB (GPIO_BASE+0xBC) +#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0) +#define GPIO_BDB (GPIO_BASE+0xC4) +#define GPIO_EEDRIVE (GPIO_BASE+0xC8) +//#define Reserved (GPIO_BASE+0xCC) +#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */ +#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */ +#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */ +#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */ +#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */ +#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */ +#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */ +#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */ +#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */ +#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */ + +/* End of old Cirrus GPIO defines */ #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) @@ -105,6 +327,8 @@ #define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) #define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) +#define EP93XX_PWM_SIZE (0x20) +#define EP93XX_PWM(x) (EP93XX_PWM_BASE + (x*EP93XX_PWM_SIZE)) #define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) @@ -122,7 +346,167 @@ #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) +/* 8093_0000 - 8093_ffff: CSC/Syscon PLL, clock control, & misc. stuff */ +#define SYSCON_OFFSET 0x130000 +#define SYSCON_BASE ((EP93XX_APB_VIRT_BASE)+SYSCON_OFFSET) +#define SYSCON_PWRSR (SYSCON_BASE+0x0000) +#define SYSCON_PWRCNT (SYSCON_BASE+0x0004) +#define SYSCON_HALT (SYSCON_BASE+0x0008) +#define SYSCON_STBY (SYSCON_BASE+0x000c) +#define SYSCON_BLEOI (SYSCON_BASE+0x0010) +#define SYSCON_MCEOI (SYSCON_BASE+0x0014) +#define SYSCON_TEOI (SYSCON_BASE+0x0018) +#define SYSCON_STFCLR (SYSCON_BASE+0x001c) +#define SYSCON_CLKSET1 (SYSCON_BASE+0x0020) +#define SYSCON_CLKSET2 (SYSCON_BASE+0x0024) +#define SYSCON_RESV00 (SYSCON_BASE+0x0028) +#define SYSCON_RESV01 (SYSCON_BASE+0x002c) +#define SYSCON_RESV02 (SYSCON_BASE+0x0030) +#define SYSCON_RESV03 (SYSCON_BASE+0x0034) +#define SYSCON_RESV04 (SYSCON_BASE+0x0038) +#define SYSCON_RESV05 (SYSCON_BASE+0x003c) +#define SYSCON_SCRREG0 (SYSCON_BASE+0x0040) +#define SYSCON_SCRREG1 (SYSCON_BASE+0x0044) +#define SYSCON_CLKTEST (SYSCON_BASE+0x0048) +#define SYSCON_USBRESET (SYSCON_BASE+0x004c) +#define SYSCON_APBWAIT (SYSCON_BASE+0x0050) +#define SYSCON_BMAR (SYSCON_BASE+0x0054) +#define SYSCON_BOOTCLR (SYSCON_BASE+0x0058) +#define SYSCON_DEVCFG (SYSCON_BASE+0x0080) +#define SYSCON_VIDDIV (SYSCON_BASE+0x0084) +#define SYSCON_MIRDIV (SYSCON_BASE+0x0088) +#define SYSCON_I2SDIV (SYSCON_BASE+0x008C) +#define SYSCON_KTDIV (SYSCON_BASE+0x0090) +#define SYSCON_CHIPID (SYSCON_BASE+0x0094) +#define SYSCON_TSTCR (SYSCON_BASE+0x0098) +#define SYSCON_SYSCFG (SYSCON_BASE+0x009C) +#define SYSCON_SWLOCK (SYSCON_BASE+0x00C0) +#define SYSCON_DEVCFG_KEYS 0x00000002 +#define SYSCON_DEVCFG_RasOnP3 0x00000010 +#define SYSCON_DEVCFG_GONK 0x08000000 + +#define SYSCON_KTDIV_KEN 0x00008000 + #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) +/* + * Defines for the ep93xx touchscreen driver + */ + +#define TOUCH_OFFSET 0x100000 +#define TOUCH_BASE (EP93XX_APB_VIRT_BASE+TOUCH_OFFSET) +#define TSSetup (TOUCH_BASE+0x00) /* R/W touchscreen controller setup control register. */ +#define TSXYMaxMin (TOUCH_BASE+0x04) /* R/W touchscreen controller max/min register. */ +#define TSXYResult (TOUCH_BASE+0x08) /* R touchscreen controller result register. */ +#define TSDischarge (TOUCH_BASE+0x0C) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSXSample (TOUCH_BASE+0x10) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSYSample (TOUCH_BASE+0x14) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSDirect (TOUCH_BASE+0x18) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSDetect (TOUCH_BASE+0x1C) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSSWLock (TOUCH_BASE+0x20) /* NA R/W touchscreen software lock register. */ +#define TSSetup2 (TOUCH_BASE+0x24) /* R/W touchscreen setup control register #2. */ + + + +/* 8003_0000 - 8003_ffff: Raster (old sections from Cirrus) */ +#define EP93XX_RASTER_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00030000) +#define RASTER_OFFSET 0x030000 +#define RASTER_BASE (EP93XX_AHB_VIRT_BASE+RASTER_OFFSET) +#define VLINESTOTAL (RASTER_BASE+0x00) +#define VSYNCSTRTSTOP (RASTER_BASE+0x04) +#define VACTIVESTRTSTOP (RASTER_BASE+0x08) +#define VCLKSTRTSTOP (RASTER_BASE+0x0C) +#define HCLKSTOTAL (RASTER_BASE+0x10) +#define HSYNCSTRTSTOP (RASTER_BASE+0x14) +#define HACTIVESTRTSTOP (RASTER_BASE+0x18) +#define HCLKSTRTSTOP (RASTER_BASE+0x1C) +#define BRIGHTNESS (RASTER_BASE+0x20) +#define VIDEOATTRIBS (RASTER_BASE+0x24) +#define VIDSCRNPAGE (RASTER_BASE+0x28) +#define VIDSCRNHPG (RASTER_BASE+0x2C) +#define SCRNLINES (RASTER_BASE+0x30) +#define LINELENGTH (RASTER_BASE+0x34) +#define VLINESTEP (RASTER_BASE+0x38) +#define LINECARRY (RASTER_BASE+0x3C) +#define BLINKRATE (RASTER_BASE+0x40) +#define BLINKMASK (RASTER_BASE+0x44) +#define BLINKPATTRN (RASTER_BASE+0x48) +#define PATTRNMASK (RASTER_BASE+0x4C) +#define BG_OFFSET (RASTER_BASE+0x50) +#define PIXELMODE (RASTER_BASE+0x54) +#define PARLLIFOUT (RASTER_BASE+0x58) +#define PARLLIFIN (RASTER_BASE+0x5C) +#define CURSOR_ADR_START (RASTER_BASE+0x60) +#define CURSOR_ADR_RESET (RASTER_BASE+0x64) +#define CURSORSIZE (RASTER_BASE+0x68) +#define CURSORCOLOR1 (RASTER_BASE+0x6C) +#define CURSORCOLOR2 (RASTER_BASE+0x70) +#define CURSORXYLOC (RASTER_BASE+0x74) +#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78) +#define RASTER_SWLOCK (RASTER_BASE+0x7C) +#define GS_LUT (RASTER_BASE+0x80) +#define RASTER_TCR (RASTER_BASE+0x100) +#define RASTER_TISRA (RASTER_BASE+0x104) +#define RASTER_TISRB (RASTER_BASE+0x108) +#define CURSOR_TISR (RASTER_BASE+0x10C) +#define RASTER_TOCRA (RASTER_BASE+0x110) +#define RASTER_TOCRB (RASTER_BASE+0x114) +#define FIFO_TOCRA (RASTER_BASE+0x118) +#define FIFO_TOCRB (RASTER_BASE+0x11C) +#define BLINK_TISR (RASTER_BASE+0x120) +#define DAC_TISRA (RASTER_BASE+0x124) +#define DAC_TISRB (RASTER_BASE+0x128) +#define SHIFT_TISR (RASTER_BASE+0x12C) +#define DACMUX_TOCRA (RASTER_BASE+0x130) +#define DACMUX_TOCRB (RASTER_BASE+0x134) +#define PELMUX_TOCR (RASTER_BASE+0x138) +#define VIDEO_TOCRA (RASTER_BASE+0x13C) +#define VIDEO_TOCRB (RASTER_BASE+0x140) +#define YCRCB_TOCR (RASTER_BASE+0x144) +#define CURSOR_TOCR (RASTER_BASE+0x148) +#define VIDEO_TOCRC (RASTER_BASE+0x14C) +#define SHIFT_TOCR (RASTER_BASE+0x150) +#define BLINK_TOCR (RASTER_BASE+0x154) +#define RASTER_TCER (RASTER_BASE+0x180) +#define SIGVAL (RASTER_BASE+0x200) +#define SIGCTL (RASTER_BASE+0x204) +#define VSIGSTRTSTOP (RASTER_BASE+0x208) +#define HSIGSTRTSTOP (RASTER_BASE+0x20C) +#define SIGCLR (RASTER_BASE+0x210) +#define ACRATE (RASTER_BASE+0x214) +#define LUTCONT (RASTER_BASE+0x218) +#define VBLANKSTRTSTOP (RASTER_BASE+0x228) +#define HBLANKSTRTSTOP (RASTER_BASE+0x22C) +#define LUT (RASTER_BASE+0x400) +#define CURSORBLINK1 (RASTER_BASE+0x21C) +#define CURSORBLINK2 (RASTER_BASE+0x220) +#define CURSORBLINK (RASTER_BASE+0x224) +#define EOLOFFSET (RASTER_BASE+0x230) +#define FIFOLEVEL (RASTER_BASE+0x234) +#define GS_LUT2 (RASTER_BASE+0x280) +#define GS_LUT3 (RASTER_BASE+0x300) +#define COLOR_LUT (RASTER_BASE+0x400) + +/* 8004_0000 - 8004_ffff: Graphics */ +#define GRAPHICS_OFFSET 0x040000 +#define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE+GRAPHICS_OFFSET) +#define SRCPIXELSTRT (GRAPHICS_BASE+0x00) +#define DESTPIXELSTRT (GRAPHICS_BASE+0x04) +#define BLKSRCSTRT (GRAPHICS_BASE+0x08) +#define BLKDSTSTRT (GRAPHICS_BASE+0x0C) +#define BLKSRCWIDTH (GRAPHICS_BASE+0x10) +#define SRCLINELENGTH (GRAPHICS_BASE+0x14) +#define BLKDESTWIDTH (GRAPHICS_BASE+0x18) +#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C) +#define DESTLINELENGTH (GRAPHICS_BASE+0x20) +#define BLOCKCTRL (GRAPHICS_BASE+0x24) +#define TRANSPATTRN (GRAPHICS_BASE+0x28) +#define BLOCKMASK (GRAPHICS_BASE+0x2C) +#define BACKGROUND (GRAPHICS_BASE+0x30) +#define LINEINC (GRAPHICS_BASE+0x34) +#define LINEINIT (GRAPHICS_BASE+0x38) +#define LINEPATTRN (GRAPHICS_BASE+0x3C) +/* End old cirrus raster and graphics */ + #endif diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h~ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h~ --- linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h~ 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h~ 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,512 @@ +/* + * linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h + */ + +#ifndef __ASM_ARCH_EP93XX_REGS_H +#define __ASM_ARCH_EP93XX_REGS_H + +/* + * EP93xx linux memory map: + * + * virt phys size + * fe800000 5M per-platform mappings + * fed00000 80800000 2M APB + * fef00000 80000000 1M AHB + */ + +#define EP93XX_AHB_PHYS_BASE 0x80000000 +#define EP93XX_AHB_VIRT_BASE 0xfef00000 +#define EP93XX_AHB_SIZE 0x00100000 + +#define EP93XX_APB_PHYS_BASE 0x80800000 +#define EP93XX_APB_VIRT_BASE 0xfed00000 +#define EP93XX_APB_SIZE 0x00200000 + + +/* AHB peripherals */ +#define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) + +#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) +#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) + +#define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) +#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) + +#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) + +#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) + +#define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) + +#define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) + +#define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) + +#define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) +#define EP93XX_IDE_REG(x) (EP93XX_IDE_BASE + (x)) +#define EP93XX_IDE_CTRL EP93XX_IDE_REG(0x0000) +#define EP93XX_IDE_CFG EP93XX_IDE_REG(0x0004) +#define EP93XX_IDE_DATAOUT EP93XX_IDE_REG(0x0010) +#define EP93XX_IDE_DATAIN EP93XX_IDE_REG(0x0014) + +#define EP93XX_IDE_CTRL_CS0n (1L << 0) +#define EP93XX_IDE_CTRL_CS1n (1L << 1) +#define EP93XX_IDE_CTRL_DA_MASK 0x1C +#define EP93XX_IDE_CTRL_DA(x) ((x << 2) & EP93XX_IDE_CTRL_DA_MASK) +#define EP93XX_IDE_CTRL_DA_CS_MASK (EP93XX_IDE_CTRL_DA_MASK | EP93XX_IDE_CTRL_CS0n | EP93XX_IDE_CTRL_CS1n) +#define EP93XX_IDE_CTRL_DA_CS(x) (((x)) & EP93XX_IDE_CTRL_DA_CS_MASK) +#define EP93XX_IDE_CTRL_DIORn (1L << 5) +#define EP93XX_IDE_CTRL_DIOWn (1L << 6) +#define EP93XX_IDE_CTRL_DASPn (1L << 7) +#define EP93XX_IDE_CTRL_DMARQ (1L << 8) +#define EP93XX_IDE_CTRL_INTRQ (1L << 9) +#define EP93XX_IDE_CTRL_IORDY (1L << 10) + +#define EP93XX_IDE_CFG_IDEEN (1L << 0) +#define EP93XX_IDE_CFG_PIO (1L << 1) +#define EP93XX_IDE_CFG_MDMA (1L << 2) +#define EP93XX_IDE_CFG_UDMA (1L << 3) +#define EP93XX_IDE_CFG_MODE(x) ((x & 0x0F) << 4) +#define EP93XX_IDE_CFG_WST(x) ((x & 0x03) << 8) + + + +/* Old IDE DMA defines */ +/* 800A_0000 - 800A_ffff: IDE Interface */ +#define IDE_OFFSET 0x0a0000 +#define IDE_BASE (EP93XX_AHB_VIRT_BASE+IDE_OFFSET) +#define IDECR (IDE_BASE+0x00) +#define IDECFG (IDE_BASE+0x04) +#define IDEMDMAOP (IDE_BASE+0x08) +#define IDEUDMAOP (IDE_BASE+0x0C) +#define IDEDATAOUT (IDE_BASE+0x10) +#define IDEDATAIN (IDE_BASE+0x14) +#define IDEMDMADATAOUT (IDE_BASE+0x18) +#define IDEMDMADATAIN (IDE_BASE+0x1C) +#define IDEUDMADATAOUT (IDE_BASE+0x20) +#define IDEUDMADATAIN (IDE_BASE+0x24) +#define IDEUDMASTATUS (IDE_BASE+0x28) +#define IDEUDMADEBUG (IDE_BASE+0x2C) +#define IDEUDMAWFST (IDE_BASE+0x30) +#define IDEUDMARFST (IDE_BASE+0x34) + +/***************************************************************************** + * + * Bit definitions for use with assembly code for the ide control register. + * + ****************************************************************************/ +#define IDECtrl_CS0n 0x00000001 +#define IDECtrl_CS1n 0x00000002 +#define IDECtrl_DA_MASK 0x0000001c +#define IDECtrl_DA_SHIFT 2 +#define IDECtrl_DIORn 0x00000020 +#define IDECtrl_DIOWn 0x00000040 +#define IDECtrl_DASPn 0x00000080 +#define IDECtrl_DMARQ 0x00000100 +#define IDECtrl_INTRQ 0x00000200 +#define IDECtrl_IORDY 0x00000400 + +#define IDECfg_IDEEN 0x00000001 +#define IDECfg_PIO 0x00000002 +#define IDECfg_MDMA 0x00000004 +#define IDECfg_UDMA 0x00000008 +#define IDECfg_MODE_MASK 0x000000f0 +#define IDECfg_MODE_SHIFT 4 +#define IDECfg_WST_MASK 0x00000300 +#define IDECfg_WST_SHIFT 8 + +#define IDEMDMAOp_MEN 0x00000001 +#define IDEMDMAOp_RWOP 0x00000002 + +#define IDEUDMAOp_UEN 0x00000001 +#define IDEUDMAOp_RWOP 0x00000002 + +#define IDEUDMASts_CS0n 0x00000001 +#define IDEUDMASts_CS1n 0x00000002 +#define IDEUDMASts_DA_MASK 0x0000001c +#define IDEUDMASts_DA_SHIFT 2 +#define IDEUDMASts_HSHD 0x00000020 +#define IDEUDMASts_STOP 0x00000040 +#define IDEUDMASts_DM 0x00000080 +#define IDEUDMASts_DDOE 0x00000100 +#define IDEUDMASts_DMARQ 0x00000200 +#define IDEUDMASts_DSDD 0x00000400 +#define IDEUDMASts_DMAide 0x00010000 +#define IDEUDMASts_INTide 0x00020000 +#define IDEUDMASts_SBUSY 0x00040000 +#define IDEUDMASts_NDO 0x01000000 +#define IDEUDMASts_NDI 0x02000000 +#define IDEUDMASts_N4X 0x04000000 + +#define IDEUDMADebug_RWOE 0x00000001 +#define IDEUDMADebug_RWPTR 0x00000002 +#define IDEUDMADebug_RWDR 0x00000004 +#define IDEUDMADebug_RROE 0x00000008 +#define IDEUDMADebug_RRPTR 0x00000010 +#define IDEUDMADebug_RRDR 0x00000020 + +#define IDEUDMAWrBufSts_HPTR_MASK 0x0000000f +#define IDEUDMAWrBufSts_HPTR_SHIFT 0 +#define IDEUDMAWrBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMAWrBufSts_TPTR_SHIFT 4 +#define IDEUDMAWrBufSts_EMPTY 0x00000100 +#define IDEUDMAWrBufSts_HOM 0x00000200 +#define IDEUDMAWrBufSts_NFULL 0x00000400 +#define IDEUDMAWrBufSts_FULL 0x00000800 +#define IDEUDMAWrBufSts_CRC_MASK 0xffff0000 +#define IDEUDMAWrBufSts_CRC_SHIFT 16 + +#define IDEUDMARdBufSts_HPTR_MASK 0x0000000f +#define IDEUDMARdBufSts_HPTR_SHIFT 0 +#define IDEUDMARdBufSts_TPTR_MASK 0x000000f0 +#define IDEUDMARdBufSts_TPTR_SHIFT 4 +#define IDEUDMARdBufSts_EMPTY 0x00000100 +#define IDEUDMARdBufSts_HOM 0x00000200 +#define IDEUDMARdBufSts_NFULL 0x00000400 +#define IDEUDMARdBufSts_FULL 0x00000800 +#define IDEUDMARdBufSts_CRC_MASK 0xffff0000 +#define IDEUDMARdBufSts_CRC_SHIFT 16 + + +/*----------------------------------old-------------------------------*/ +#define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) + +#define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) + + +/* APB peripherals */ +#define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) +#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) +#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) +#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) +#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) +#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) +#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) +#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) +#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) +#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) +#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) +#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) +#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) +#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) +#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) +#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) + +/* Cirrus Defines */ +/* 8081_0000 - 8081_ffff: Timers */ +#define TIMERS_OFFSET 0x010000 +#define TIMERS_BASE (EP93XX_APB_VIRT_BASE+TIMERS_OFFSET) + +#define TIMER1LOAD (TIMERS_BASE+0x00) +#define TIMER1VALUE (TIMERS_BASE+0x04) +#define TIMER1CONTROL (TIMERS_BASE+0x08) +#define TIMER1CLEAR (TIMERS_BASE+0x0C) +#define TIMER1TEST (TIMERS_BASE+0x10) + +#define TIMER2LOAD (TIMERS_BASE+0x20) +#define TIMER2VALUE (TIMERS_BASE+0x24) +#define TIMER2CONTROL (TIMERS_BASE+0x28) +#define TIMER2CLEAR (TIMERS_BASE+0x2C) +#define TIMER2TEST (TIMERS_BASE+0x30) + +#define TIMER3LOAD (TIMERS_BASE+0x80) +#define TIMER3VALUE (TIMERS_BASE+0x84) +#define TIMER3CONTROL (TIMERS_BASE+0x88) +#define TIMER3CLEAR (TIMERS_BASE+0x8C) +#define TIMER3TEST (TIMERS_BASE+0x90) + +#define TTIMERBZCONT (TIMERS_BASE+0x40) + +#define TIMER4VALUELOW (TIMERS_BASE+0x60) +#define TIMER4VALUEHIGH (TIMERS_BASE+0x64) +/* End Cirrus Timer Defines */ + +#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) + +#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) + +#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) +#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) +#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90) +#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94) +#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) +#define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c) +#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_A_INT_DEBOUNCE EP93XX_GPIO_REG(0xa8) +#define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac) +#define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0) +#define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4) +#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) +#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) +#define EP93XX_GPIO_B_INT_DEBOUNCE EP93XX_GPIO_REG(0xc4) + +/* 8084_0000 - 8084_ffff: GPIO -- OLD cirrus GPIO defines */ +#define GPIO_OFFSET 0x040000 +#define GPIO_BASE (EP93XX_APB_VIRT_BASE+GPIO_OFFSET) +#define GPIO_PADR (GPIO_BASE+0x00) +#define GPIO_PBDR (GPIO_BASE+0x04) +#define GPIO_PCDR (GPIO_BASE+0x08) +#define GPIO_PDDR (GPIO_BASE+0x0C) +#define GPIO_PADDR (GPIO_BASE+0x10) +#define GPIO_PBDDR (GPIO_BASE+0x14) +#define GPIO_PCDDR (GPIO_BASE+0x18) +#define GPIO_PDDDR (GPIO_BASE+0x1C) +#define GPIO_PEDR (GPIO_BASE+0x20) +#define GPIO_PEDDR (GPIO_BASE+0x24) +// #define 0x8084.0028 Reserved +// #define 0x8084.002C Reserved +#define GPIO_PFDR (GPIO_BASE+0x30) +#define GPIO_PFDDR (GPIO_BASE+0x34) +#define GPIO_PGDR (GPIO_BASE+0x38) +#define GPIO_PGDDR (GPIO_BASE+0x3C) +#define GPIO_PHDR (GPIO_BASE+0x40) +#define GPIO_PHDDR (GPIO_BASE+0x44) +// #define 0x8084.0048 RAZ RAZ +#define GPIO_FINTTYPE1 (GPIO_BASE+0x4C) +#define GPIO_FINTTYPE2 (GPIO_BASE+0x50) +#define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_FINTEN (GPIO_BASE+0x58) +#define GPIO_INTSTATUSF (GPIO_BASE+0x5C) +#define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60) +#define GPIO_FDB (GPIO_BASE+0x64) +#define GPIO_PAPINDR (GPIO_BASE+0x68) +#define GPIO_PBPINDR (GPIO_BASE+0x6C) +#define GPIO_PCPINDR (GPIO_BASE+0x70) +#define GPIO_PDPINDR (GPIO_BASE+0x74) +#define GPIO_PEPINDR (GPIO_BASE+0x78) +#define GPIO_PFPINDR (GPIO_BASE+0x7C) +#define GPIO_PGPINDR (GPIO_BASE+0x80) +#define GPIO_PHPINDR (GPIO_BASE+0x84) +#define GPIO_AINTTYPE1 (GPIO_BASE+0x90) +#define GPIO_AINTTYPE2 (GPIO_BASE+0x94) +#define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_AINTEN (GPIO_BASE+0x9C) +#define GPIO_INTSTATUSA (GPIO_BASE+0xA0) +#define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4) +#define GPIO_ADB (GPIO_BASE+0xA8) +#define GPIO_BINTTYPE1 (GPIO_BASE+0xAC) +#define GPIO_BINTTYPE2 (GPIO_BASE+0xB0) +#define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */ +#define GPIO_BINTEN (GPIO_BASE+0xB8) +#define GPIO_INTSTATUSB (GPIO_BASE+0xBC) +#define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0) +#define GPIO_BDB (GPIO_BASE+0xC4) +#define GPIO_EEDRIVE (GPIO_BASE+0xC8) +//#define Reserved (GPIO_BASE+0xCC) +#define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */ +#define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */ +#define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */ +#define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */ +#define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */ +#define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */ +#define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */ +#define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */ +#define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */ +#define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */ + +/* End of old Cirrus GPIO defines */ + +#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) + +#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) + +#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) + +#define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000) +#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) + +#define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000) +#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) + +#define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000) +#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) + +#define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) + +#define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) +#define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) + +#define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) +#define EP93XX_PWM_SIZE (0x20) +#define EP93XX_PWM(x) (EP93XX_PWM_BASE + (x*EP93XX_PWM_SIZE)) + +#define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) + +#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) +#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) +#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) +#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) +#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 +#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 +#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) +#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) +#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) +#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) +#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) +#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 +#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) + +/* 8093_0000 - 8093_ffff: CSC/Syscon PLL, clock control, & misc. stuff */ +#define SYSCON_OFFSET 0x130000 +#define SYSCON_BASE ((EP93XX_APB_VIRT_BASE)+SYSCON_OFFSET) +#define SYSCON_PWRSR (SYSCON_BASE+0x0000) +#define SYSCON_PWRCNT (SYSCON_BASE+0x0004) +#define SYSCON_HALT (SYSCON_BASE+0x0008) +#define SYSCON_STBY (SYSCON_BASE+0x000c) +#define SYSCON_BLEOI (SYSCON_BASE+0x0010) +#define SYSCON_MCEOI (SYSCON_BASE+0x0014) +#define SYSCON_TEOI (SYSCON_BASE+0x0018) +#define SYSCON_STFCLR (SYSCON_BASE+0x001c) +#define SYSCON_CLKSET1 (SYSCON_BASE+0x0020) +#define SYSCON_CLKSET2 (SYSCON_BASE+0x0024) +#define SYSCON_RESV00 (SYSCON_BASE+0x0028) +#define SYSCON_RESV01 (SYSCON_BASE+0x002c) +#define SYSCON_RESV02 (SYSCON_BASE+0x0030) +#define SYSCON_RESV03 (SYSCON_BASE+0x0034) +#define SYSCON_RESV04 (SYSCON_BASE+0x0038) +#define SYSCON_RESV05 (SYSCON_BASE+0x003c) +#define SYSCON_SCRREG0 (SYSCON_BASE+0x0040) +#define SYSCON_SCRREG1 (SYSCON_BASE+0x0044) +#define SYSCON_CLKTEST (SYSCON_BASE+0x0048) +#define SYSCON_USBRESET (SYSCON_BASE+0x004c) +#define SYSCON_APBWAIT (SYSCON_BASE+0x0050) +#define SYSCON_BMAR (SYSCON_BASE+0x0054) +#define SYSCON_BOOTCLR (SYSCON_BASE+0x0058) +#define SYSCON_DEVCFG (SYSCON_BASE+0x0080) +#define SYSCON_VIDDIV (SYSCON_BASE+0x0084) +#define SYSCON_MIRDIV (SYSCON_BASE+0x0088) +#define SYSCON_I2SDIV (SYSCON_BASE+0x008C) +#define SYSCON_KTDIV (SYSCON_BASE+0x0090) +#define SYSCON_CHIPID (SYSCON_BASE+0x0094) +#define SYSCON_TSTCR (SYSCON_BASE+0x0098) +#define SYSCON_SYSCFG (SYSCON_BASE+0x009C) +#define SYSCON_SWLOCK (SYSCON_BASE+0x00C0) +#define SYSCON_DEVCFG_KEYS 0x00000002 +#define SYSCON_DEVCFG_RasOnP3 0x00000010 +#define SYSCON_DEVCFG_GONK 0x08000000 + +#define SYSCON_KTDIV_KEN 0x00008000 + +#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) + + +/* + * Defines for the ep93xx touchscreen driver + */ + +#define TOUCH_OFFSET 0x100000 +#define TOUCH_BASE (EP93XX_APB_VIRT_BASE+TOUCH_OFFSET) +#define TSSetup (TOUCH_BASE+0x00) /* R/W touchscreen controller setup control register. */ +#define TSXYMaxMin (TOUCH_BASE+0x04) /* R/W touchscreen controller max/min register. */ +#define TSXYResult (TOUCH_BASE+0x08) /* R touchscreen controller result register. */ +#define TSDischarge (TOUCH_BASE+0x0C) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSXSample (TOUCH_BASE+0x10) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSYSample (TOUCH_BASE+0x14) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSDirect (TOUCH_BASE+0x18) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSDetect (TOUCH_BASE+0x1C) /* LOCKED R/W touchscreen Switch Matrix control register. */ +#define TSSWLock (TOUCH_BASE+0x20) /* NA R/W touchscreen software lock register. */ +#define TSSetup2 (TOUCH_BASE+0x24) /* R/W touchscreen setup control register #2. */ + + + +/* 8003_0000 - 8003_ffff: Raster (old sections from Cirrus) */ +#define EP93XX_RASTER_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00030000) +#define RASTER_OFFSET 0x030000 +#define RASTER_BASE (EP93XX_AHB_VIRT_BASE+RASTER_OFFSET) +#define VLINESTOTAL (RASTER_BASE+0x00) +#define VSYNCSTRTSTOP (RASTER_BASE+0x04) +#define VACTIVESTRTSTOP (RASTER_BASE+0x08) +#define VCLKSTRTSTOP (RASTER_BASE+0x0C) +#define HCLKSTOTAL (RASTER_BASE+0x10) +#define HSYNCSTRTSTOP (RASTER_BASE+0x14) +#define HACTIVESTRTSTOP (RASTER_BASE+0x18) +#define HCLKSTRTSTOP (RASTER_BASE+0x1C) +#define BRIGHTNESS (RASTER_BASE+0x20) +#define VIDEOATTRIBS (RASTER_BASE+0x24) +#define VIDSCRNPAGE (RASTER_BASE+0x28) +#define VIDSCRNHPG (RASTER_BASE+0x2C) +#define SCRNLINES (RASTER_BASE+0x30) +#define LINELENGTH (RASTER_BASE+0x34) +#define VLINESTEP (RASTER_BASE+0x38) +#define LINECARRY (RASTER_BASE+0x3C) +#define BLINKRATE (RASTER_BASE+0x40) +#define BLINKMASK (RASTER_BASE+0x44) +#define BLINKPATTRN (RASTER_BASE+0x48) +#define PATTRNMASK (RASTER_BASE+0x4C) +#define BG_OFFSET (RASTER_BASE+0x50) +#define PIXELMODE (RASTER_BASE+0x54) +#define PARLLIFOUT (RASTER_BASE+0x58) +#define PARLLIFIN (RASTER_BASE+0x5C) +#define CURSOR_ADR_START (RASTER_BASE+0x60) +#define CURSOR_ADR_RESET (RASTER_BASE+0x64) +#define CURSORSIZE (RASTER_BASE+0x68) +#define CURSORCOLOR1 (RASTER_BASE+0x6C) +#define CURSORCOLOR2 (RASTER_BASE+0x70) +#define CURSORXYLOC (RASTER_BASE+0x74) +#define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78) +#define RASTER_SWLOCK (RASTER_BASE+0x7C) +#define GS_LUT (RASTER_BASE+0x80) +#define RASTER_TCR (RASTER_BASE+0x100) +#define RASTER_TISRA (RASTER_BASE+0x104) +#define RASTER_TISRB (RASTER_BASE+0x108) +#define CURSOR_TISR (RASTER_BASE+0x10C) +#define RASTER_TOCRA (RASTER_BASE+0x110) +#define RASTER_TOCRB (RASTER_BASE+0x114) +#define FIFO_TOCRA (RASTER_BASE+0x118) +#define FIFO_TOCRB (RASTER_BASE+0x11C) +#define BLINK_TISR (RASTER_BASE+0x120) +#define DAC_TISRA (RASTER_BASE+0x124) +#define DAC_TISRB (RASTER_BASE+0x128) +#define SHIFT_TISR (RASTER_BASE+0x12C) +#define DACMUX_TOCRA (RASTER_BASE+0x130) +#define DACMUX_TOCRB (RASTER_BASE+0x134) +#define PELMUX_TOCR (RASTER_BASE+0x138) +#define VIDEO_TOCRA (RASTER_BASE+0x13C) +#define VIDEO_TOCRB (RASTER_BASE+0x140) +#define YCRCB_TOCR (RASTER_BASE+0x144) +#define CURSOR_TOCR (RASTER_BASE+0x148) +#define VIDEO_TOCRC (RASTER_BASE+0x14C) +#define SHIFT_TOCR (RASTER_BASE+0x150) +#define BLINK_TOCR (RASTER_BASE+0x154) +#define RASTER_TCER (RASTER_BASE+0x180) +#define SIGVAL (RASTER_BASE+0x200) +#define SIGCTL (RASTER_BASE+0x204) +#define VSIGSTRTSTOP (RASTER_BASE+0x208) +#define HSIGSTRTSTOP (RASTER_BASE+0x20C) +#define SIGCLR (RASTER_BASE+0x210) +#define ACRATE (RASTER_BASE+0x214) +#define LUTCONT (RASTER_BASE+0x218) +#define VBLANKSTRTSTOP (RASTER_BASE+0x228) +#define HBLANKSTRTSTOP (RASTER_BASE+0x22C) +#define LUT (RASTER_BASE+0x400) +#define CURSORBLINK1 (RASTER_BASE+0x21C) +#define CURSORBLINK2 (RASTER_BASE+0x220) +#define CURSORBLINK (RASTER_BASE+0x224) +#define EOLOFFSET (RASTER_BASE+0x230) +#define FIFOLEVEL (RASTER_BASE+0x234) +#define GS_LUT2 (RASTER_BASE+0x280) +#define GS_LUT3 (RASTER_BASE+0x300) +#define COLOR_LUT (RASTER_BASE+0x400) + +/* 8004_0000 - 8004_ffff: Graphics */ +#define GRAPHICS_OFFSET 0x040000 +#define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE+GRAPHICS_OFFSET) +#define SRCPIXELSTRT (GRAPHICS_BASE+0x00) +#define DESTPIXELSTRT (GRAPHICS_BASE+0x04) +#define BLKSRCSTRT (GRAPHICS_BASE+0x08) +#define BLKDSTSTRT (GRAPHICS_BASE+0x0C) +#define BLKSRCWIDTH (GRAPHICS_BASE+0x10) +#define SRCLINELENGTH (GRAPHICS_BASE+0x14) +#define BLKDESTWIDTH (GRAPHICS_BASE+0x18) +#define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C) +#define DESTLINELENGTH (GRAPHICS_BASE+0x20) +#define BLOCKCTRL (GRAPHICS_BASE+0x24) +#define TRANSPATTRN (GRAPHICS_BASE+0x28) +#define BLOCKMASK (GRAPHICS_BASE+0x2C) +#define BACKGROUND (GRAPHICS_BASE+0x30) +#define LINEINC (GRAPHICS_BASE+0x34) +#define LINEINIT (GRAPHICS_BASE+0x38) +#define LINEPATTRN (GRAPHICS_BASE+0x3C) +/* End old cirrus raster and graphics */ + +#endif diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h.orig linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h.orig --- linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h.orig 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h.orig 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,130 @@ +/* + * linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h + */ + +#ifndef __ASM_ARCH_EP93XX_REGS_H +#define __ASM_ARCH_EP93XX_REGS_H + +/* + * EP93xx linux memory map: + * + * virt phys size + * fe800000 5M per-platform mappings + * fed00000 80800000 2M APB + * fef00000 80000000 1M AHB + */ + +#define EP93XX_AHB_PHYS_BASE 0x80000000 +#define EP93XX_AHB_VIRT_BASE 0xfef00000 +#define EP93XX_AHB_SIZE 0x00100000 + +#define EP93XX_APB_PHYS_BASE 0x80800000 +#define EP93XX_APB_VIRT_BASE 0xfed00000 +#define EP93XX_APB_SIZE 0x00200000 + + +/* AHB peripherals */ +#define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) + +#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) +#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) + +#define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) +#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) + +#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) + +#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) + +#define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) + +#define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) + +#define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) + +#define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) + +#define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) + +#define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) + + +/* APB peripherals */ +#define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) +#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) +#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) +#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) +#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) +#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) +#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) +#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) +#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) +#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) +#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) +#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) +#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) +#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) +#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) +#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) + +#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) + +#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) + +#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) +#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) +#define EP93XX_GPIO_A_INT_TYPE1 EP93XX_GPIO_REG(0x90) +#define EP93XX_GPIO_A_INT_TYPE2 EP93XX_GPIO_REG(0x94) +#define EP93XX_GPIO_A_INT_ACK EP93XX_GPIO_REG(0x98) +#define EP93XX_GPIO_A_INT_ENABLE EP93XX_GPIO_REG(0x9c) +#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) +#define EP93XX_GPIO_B_INT_TYPE1 EP93XX_GPIO_REG(0xac) +#define EP93XX_GPIO_B_INT_TYPE2 EP93XX_GPIO_REG(0xb0) +#define EP93XX_GPIO_B_INT_ACK EP93XX_GPIO_REG(0xb4) +#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) +#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) + +#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) + +#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) + +#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) + +#define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000) +#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) + +#define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000) +#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) + +#define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000) +#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) + +#define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) + +#define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) +#define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) + +#define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) +#define EP93XX_PWM_SIZE (0x20) +#define EP93XX_PWM(x) (EP93XX_PWM_BASE + (x*EP93XX_PWM_SIZE)) + +#define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) + +#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) +#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) +#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) +#define EP93XX_SYSCON_CLOCK_CONTROL EP93XX_SYSCON_REG(0x04) +#define EP93XX_SYSCON_CLOCK_UARTBAUD 0x20000000 +#define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 +#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) +#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) +#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) +#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) +#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) +#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 +#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) + +#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) + + +#endif diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h.rej linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h.rej --- linux-2.6.20/include/asm-arm/arch-ep93xx/ep93xx-regs.h.rej 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/ep93xx-regs.h.rej 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,962 @@ +*************** +*** 15,39 **** + */ + + #define EP93XX_AHB_PHYS_BASE 0x80000000 +- #define EP93XX_AHB_VIRT_BASE 0xfef00000 + #define EP93XX_AHB_SIZE 0x00100000 + + #define EP93XX_APB_PHYS_BASE 0x80800000 +- #define EP93XX_APB_VIRT_BASE 0xfed00000 + #define EP93XX_APB_SIZE 0x00200000 + + +- /* AHB peripherals */ + #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) + + #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) + + #define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) + #define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) + + #define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) + + #define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) + + #define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) + +--- 15,924 ---- + */ + + #define EP93XX_AHB_PHYS_BASE 0x80000000 ++ #define EP93XX_AHB_VIRT_BASE 0xff000000//0xfef00000 + #define EP93XX_AHB_SIZE 0x00100000 + ++ + #define EP93XX_APB_PHYS_BASE 0x80800000 ++ #define EP93XX_APB_VIRT_BASE 0xff800000//0xfed00000 + #define EP93XX_APB_SIZE 0x00200000 + + ++ #define IO_BASE_PHYS EP93XX_AHB_PHYS_BASE ++ #define IO_BASE_VIRT EP93XX_AHB_VIRT_BASE ++ /* ++ * We don't map the PCMCIA initially. The PCMCIA driver will use ioremap ++ * to be able to see it. But besides that PCMCIA will not exist in the ++ * memory map. ++ */ ++ #define PCMCIA_BASE_VIRT 0xD0000000 // Virtual address of PCMCIA ++ #define PCMCIA_BASE_PHYS 0x40000000 // Physical address of PCMCIA ++ #define PCMCIA_SIZE 0x10000000 // How much? ++ ++ ++ ++ /* ++ * We don't map the PCMCIA initially. The PCMCIA driver will use ioremap ++ * to be able to see it. But besides that PCMCIA will not exist in the */ ++ /* SMC register map */ ++ /* Address Read Location Write Location */ ++ /* 0x8000.2000 SMCBCR0(Bank config register 0) SMCBCR0(Bank config register 0) */ ++ /* 0x8000.2004 SMCBCR1(Bank config register 1) SMCBCR1(Bank config register 1) */ ++ /* 0x8000.2008 SMCBCR2(Bank config register 2) SMCBCR2(Bank config register 2) */ ++ /* 0x8000.200C SMCBCR3(Bank config register 3) SMCBCR3(Bank config register 3) */ ++ /* 0x8000.2010 Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.2014 Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.2018 SMCBCR6(Bank config register 6) SMCBCR6(Bank config register 6) */ ++ /* 0x8000.201C SMCBCR7(Bank config register 7) SMCBCR7(Bank config register 7) */ ++ /* 0x8000.2020 PCAttribute Register PCAttribute Register */ ++ /* 0x8000.2024 PCCommon Register PCCommon Register */ ++ /* 0x8000.2028 PCIO Register PCIO Register */ ++ /* 0x8000.202C Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.2030 Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.2034 Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.2038 Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.203C Reserved, RAZ Reserved, RAZ */ ++ /* 0x8000.2040 PCMCIACtrl Register PCMCIACtrl Register */ ++ ++ #define SRAM_OFFSET 0x080000 ++ #define SRAM_BASE (EP93XX_AHB_VIRT_BASE|SRAM_OFFSET) ++ #define SMCBCR0 (SRAM_BASE+0x00) /* 0x8000.2000 Bank config register 0 */ ++ #define SMCBCR1 (SRAM_BASE+0x04) /* 0x8000.2004 Bank config register 1 */ ++ #define SMCBCR2 (SRAM_BASE+0x08) /* 0x8000.2008 Bank config register 2 */ ++ #define SMCBCR3 (SRAM_BASE+0x0C) /* 0x8000.200C Bank config register 3 */ ++ /* 0x8000.2010 Reserved, RAZ */ ++ /* 0x8000.2014 Reserved, RAZ */ ++ #define SMCBCR6 (SRAM_BASE+0x18) /* 0x8000.2018 Bank config register 6 */ ++ #define SMCBCR7 (SRAM_BASE+0x1C) /* 0x8000.201C Bank config register 7 */ ++ ++ #define SMC_PCAttribute (SRAM_BASE+0x20) /* 0x8000.2020 PCMCIA Attribute Register */ ++ #define SMC_PCCommon (SRAM_BASE+0x24) /* 0x8000.2024 PCMCIA Common Register */ ++ #define SMC_PCIO (SRAM_BASE+0x28) /* 0x8000.2028 PCMCIA IO Register */ ++ /* 0x8000.202C Reserved, RAZ */ ++ /* 0x8000.2030 Reserved, RAZ */ ++ /* 0x8000.2034 Reserved, RAZ */ ++ /* 0x8000.2038 Reserved, RAZ */ ++ /* 0x8000.203C Reserved, RAZ */ ++ #define SMC_PCMCIACtrl (SRAM_BASE+0x40) /* 0x8000.2040 PCMCIA control register */ ++ ++ ++ ++ + #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) ++ // ++ /* 8000_0000 - 8000_ffff: DMA */ ++ #define DMA_OFFSET 0x000000 ++ #define DMA_BASE (EP93XX_DMA_BASE) ++ #define DMAMP_TX_0_CONTROL (DMA_BASE+0x0000) ++ #define DMAMP_TX_0_INTERRUPT (DMA_BASE+0x0004) ++ #define DMAMP_TX_0_PPALLOC (DMA_BASE+0x0008) ++ #define DMAMP_TX_0_STATUS (DMA_BASE+0x000C) ++ #define DMAMP_TX_0_REMAIN (DMA_BASE+0x0014) ++ #define DMAMP_TX_0_MAXCNT0 (DMA_BASE+0x0020) ++ #define DMAMP_TX_0_BASE0 (DMA_BASE+0x0024) ++ #define DMAMP_TX_0_CURRENT0 (DMA_BASE+0x0028) ++ #define DMAMP_TX_0_MAXCNT1 (DMA_BASE+0x0030) ++ #define DMAMP_TX_0_BASE1 (DMA_BASE+0x0034) ++ #define DMAMP_TX_0_CURRENT1 (DMA_BASE+0x0038) ++ ++ #define DMAMP_RX_1_CONTROL (DMA_BASE+0x0040) ++ #define DMAMP_RX_1_INTERRUPT (DMA_BASE+0x0044) ++ #define DMAMP_RX_1_PPALLOC (DMA_BASE+0x0048) ++ #define DMAMP_RX_1_STATUS (DMA_BASE+0x004C) ++ #define DMAMP_RX_1_REMAIN (DMA_BASE+0x0054) ++ #define DMAMP_RX_1_MAXCNT0 (DMA_BASE+0x0060) ++ #define DMAMP_RX_1_BASE0 (DMA_BASE+0x0064) ++ #define DMAMP_RX_1_CURRENT0 (DMA_BASE+0x0068) ++ #define DMAMP_RX_1_MAXCNT1 (DMA_BASE+0x0070) ++ #define DMAMP_RX_1_BASE1 (DMA_BASE+0x0074) ++ #define DMAMP_RX_1_CURRENT1 (DMA_BASE+0x0078) ++ ++ #define DMAMP_TX_2_CONTROL (DMA_BASE+0x0080) ++ #define DMAMP_TX_2_INTERRUPT (DMA_BASE+0x0084) ++ #define DMAMP_TX_2_PPALLOC (DMA_BASE+0x0088) ++ #define DMAMP_TX_2_STATUS (DMA_BASE+0x008C) ++ #define DMAMP_TX_2_REMAIN (DMA_BASE+0x0094) ++ #define DMAMP_TX_2_MAXCNT0 (DMA_BASE+0x00A0) ++ #define DMAMP_TX_2_BASE0 (DMA_BASE+0x00A4) ++ #define DMAMP_TX_2_CURRENT0 (DMA_BASE+0x00A8) ++ #define DMAMP_TX_2_MAXCNT1 (DMA_BASE+0x00B0) ++ #define DMAMP_TX_2_BASE1 (DMA_BASE+0x00B4) ++ #define DMAMP_TX_2_CURRENT1 (DMA_BASE+0x00B8) ++ ++ #define DMAMP_RX_3_CONTROL (DMA_BASE+0x00C0) ++ #define DMAMP_RX_3_INTERRUPT (DMA_BASE+0x00C4) ++ #define DMAMP_RX_3_PPALLOC (DMA_BASE+0x00C8) ++ #define DMAMP_RX_3_STATUS (DMA_BASE+0x00CC) ++ #define DMAMP_RX_3_REMAIN (DMA_BASE+0x00D4) ++ #define DMAMP_RX_3_MAXCNT0 (DMA_BASE+0x00E0) ++ #define DMAMP_RX_3_BASE0 (DMA_BASE+0x00E4) ++ #define DMAMP_RX_3_CURRENT0 (DMA_BASE+0x00E8) ++ #define DMAMP_RX_3_MAXCNT1 (DMA_BASE+0x00F0) ++ #define DMAMP_RX_3_BASE1 (DMA_BASE+0x00F4) ++ #define DMAMP_RX_3_CURRENT1 (DMA_BASE+0x00F8) ++ ++ #define DMAMM_0_CONTROL (DMA_BASE+0x0100) ++ #define DMAMM_0_INTERRUPT (DMA_BASE+0x0104) ++ #define DMAMM_0_STATUS (DMA_BASE+0x010C) ++ #define DMAMM_0_BCR0 (DMA_BASE+0x0110) ++ #define DMAMM_0_BCR1 (DMA_BASE+0x0114) ++ #define DMAMM_0_SAR_BASE0 (DMA_BASE+0x0118) ++ #define DMAMM_0_SAR_BASE1 (DMA_BASE+0x011C) ++ #define DMAMM_0_SAR_CURRENT0 (DMA_BASE+0x0124) ++ #define DMAMM_0_SAR_CURRENT1 (DMA_BASE+0x0128) ++ #define DMAMM_0_DAR_BASE0 (DMA_BASE+0x012C) ++ #define DMAMM_0_DAR_BASE1 (DMA_BASE+0x0130) ++ #define DMAMM_0_DAR_CURRENT0 (DMA_BASE+0x0134) ++ #define DMAMM_0_DAR_CURRENT1 (DMA_BASE+0x013C) ++ ++ #define DMAMM_1_CONTROL (DMA_BASE+0x0140) ++ #define DMAMM_1_INTERRUPT (DMA_BASE+0x0144) ++ #define DMAMM_1_STATUS (DMA_BASE+0x014C) ++ #define DMAMM_1_BCR0 (DMA_BASE+0x0150) ++ #define DMAMM_1_BCR1 (DMA_BASE+0x0154) ++ #define DMAMM_1_SAR_BASE0 (DMA_BASE+0x0158) ++ #define DMAMM_1_SAR_BASE1 (DMA_BASE+0x015C) ++ #define DMAMM_1_SAR_CURRENT0 (DMA_BASE+0x0164) ++ #define DMAMM_1_SAR_CURRENT1 (DMA_BASE+0x0168) ++ #define DMAMM_1_DAR_BASE0 (DMA_BASE+0x016C) ++ #define DMAMM_1_DAR_BASE1 (DMA_BASE+0x0170) ++ #define DMAMM_1_DAR_CURRENT0 (DMA_BASE+0x0174) ++ #define DMAMM_1_DAR_CURRENT1 (DMA_BASE+0x017C) ++ ++ #define DMAMP_RX_5_CONTROL (DMA_BASE+0x0200) ++ #define DMAMP_RX_5_INTERRUPT (DMA_BASE+0x0204) ++ #define DMAMP_RX_5_PPALLOC (DMA_BASE+0x0208) ++ #define DMAMP_RX_5_STATUS (DMA_BASE+0x020C) ++ #define DMAMP_RX_5_REMAIN (DMA_BASE+0x0214) ++ #define DMAMP_RX_5_MAXCNT0 (DMA_BASE+0x0220) ++ #define DMAMP_RX_5_BASE0 (DMA_BASE+0x0224) ++ #define DMAMP_RX_5_CURRENT0 (DMA_BASE+0x0228) ++ #define DMAMP_RX_5_MAXCNT1 (DMA_BASE+0x0230) ++ #define DMAMP_RX_5_BASE1 (DMA_BASE+0x0234) ++ #define DMAMP_RX_5_CURRENT1 (DMA_BASE+0x0238) ++ ++ #define DMAMP_TX_4_CONTROL (DMA_BASE+0x0240) ++ #define DMAMP_TX_4_INTERRUPT (DMA_BASE+0x0244) ++ #define DMAMP_TX_4_PPALLOC (DMA_BASE+0x0248) ++ #define DMAMP_TX_4_STATUS (DMA_BASE+0x024C) ++ #define DMAMP_TX_4_REMAIN (DMA_BASE+0x0254) ++ #define DMAMP_TX_4_MAXCNT0 (DMA_BASE+0x0260) ++ #define DMAMP_TX_4_BASE0 (DMA_BASE+0x0264) ++ #define DMAMP_TX_4_CURRENT0 (DMA_BASE+0x0268) ++ #define DMAMP_TX_4_MAXCNT1 (DMA_BASE+0x0270) ++ #define DMAMP_TX_4_BASE1 (DMA_BASE+0x0274) ++ #define DMAMP_TX_4_CURRENT1 (DMA_BASE+0x0278) ++ ++ #define DMAMP_RX_7_CONTROL (DMA_BASE+0x0280) ++ #define DMAMP_RX_7_INTERRUPT (DMA_BASE+0x0284) ++ #define DMAMP_RX_7_PPALLOC (DMA_BASE+0x0288) ++ #define DMAMP_RX_7_STATUS (DMA_BASE+0x028C) ++ #define DMAMP_RX_7_REMAIN (DMA_BASE+0x0294) ++ #define DMAMP_RX_7_MAXCNT0 (DMA_BASE+0x02A0) ++ #define DMAMP_RX_7_BASE0 (DMA_BASE+0x02A4) ++ #define DMAMP_RX_7_CURRENT0 (DMA_BASE+0x02A8) ++ #define DMAMP_RX_7_MAXCNT1 (DMA_BASE+0x02B0) ++ #define DMAMP_RX_7_BASE1 (DMA_BASE+0x02B4) ++ #define DMAMP_RX_7_CURRENT1 (DMA_BASE+0x02B8) ++ ++ #define DMAMP_TX_6_CONTROL (DMA_BASE+0x02C0) ++ #define DMAMP_TX_6_INTERRUPT (DMA_BASE+0x02C4) ++ #define DMAMP_TX_6_PPALLOC (DMA_BASE+0x02C8) ++ #define DMAMP_TX_6_STATUS (DMA_BASE+0x02CC) ++ #define DMAMP_TX_6_REMAIN (DMA_BASE+0x02D4) ++ #define DMAMP_TX_6_MAXCNT0 (DMA_BASE+0x02E0) ++ #define DMAMP_TX_6_BASE0 (DMA_BASE+0x02E4) ++ #define DMAMP_TX_6_CURRENT0 (DMA_BASE+0x02E8) ++ #define DMAMP_TX_6_MAXCNT1 (DMA_BASE+0x02F0) ++ #define DMAMP_TX_6_BASE1 (DMA_BASE+0x02F4) ++ #define DMAMP_TX_6_CURRENT1 (DMA_BASE+0x02F8) ++ ++ #define DMAMP_RX_9_CONTROL (DMA_BASE+0x0300) ++ #define DMAMP_RX_9_INTERRUPT (DMA_BASE+0x0304) ++ #define DMAMP_RX_9_PPALLOC (DMA_BASE+0x0308) ++ #define DMAMP_RX_9_STATUS (DMA_BASE+0x030C) ++ #define DMAMP_RX_9_REMAIN (DMA_BASE+0x0314) ++ #define DMAMP_RX_9_MAXCNT0 (DMA_BASE+0x0320) ++ #define DMAMP_RX_9_BASE0 (DMA_BASE+0x0324) ++ #define DMAMP_RX_9_CURRENT0 (DMA_BASE+0x0328) ++ #define DMAMP_RX_9_MAXCNT1 (DMA_BASE+0x0330) ++ #define DMAMP_RX_9_BASE1 (DMA_BASE+0x0334) ++ #define DMAMP_RX_9_CURRENT1 (DMA_BASE+0x0338) ++ ++ #define DMAMP_TX_8_CONTROL (DMA_BASE+0x0340) ++ #define DMAMP_TX_8_INTERRUPT (DMA_BASE+0x0344) ++ #define DMAMP_TX_8_PPALLOC (DMA_BASE+0x0348) ++ #define DMAMP_TX_8_STATUS (DMA_BASE+0x034C) ++ #define DMAMP_TX_8_REMAIN (DMA_BASE+0x0354) ++ #define DMAMP_TX_8_MAXCNT0 (DMA_BASE+0x0360) ++ #define DMAMP_TX_8_BASE0 (DMA_BASE+0x0364) ++ #define DMAMP_TX_8_CURRENT0 (DMA_BASE+0x0368) ++ #define DMAMP_TX_8_MAXCNT1 (DMA_BASE+0x0370) ++ #define DMAMP_TX_8_BASE1 (DMA_BASE+0x0374) ++ #define DMAMP_TX_8_CURRENT1 (DMA_BASE+0x0378) ++ ++ #define DMA_ARBITRATION (DMA_BASE+0x0380) ++ #define DMA_INTERRUPT (DMA_BASE+0x03C0) ++ ++ ++ /* ++ * DMA Register Base addresses and Offsets ++ */ ++ #define DMA_M2P_TX_0_BASE DMAMP_TX_0_CONTROL ++ #define DMA_M2P_RX_1_BASE DMAMP_RX_1_CONTROL ++ #define DMA_M2P_TX_2_BASE DMAMP_TX_2_CONTROL ++ #define DMA_M2P_RX_3_BASE DMAMP_RX_3_CONTROL ++ #define DMA_M2M_0_BASE DMAMM_0_CONTROL ++ #define DMA_M2M_1_BASE DMAMM_1_CONTROL ++ #define DMA_M2P_RX_5_BASE DMAMP_RX_5_CONTROL ++ #define DMA_M2P_TX_4_BASE DMAMP_TX_4_CONTROL ++ #define DMA_M2P_RX_7_BASE DMAMP_RX_7_CONTROL ++ #define DMA_M2P_TX_6_BASE DMAMP_TX_6_CONTROL ++ #define DMA_M2P_RX_9_BASE DMAMP_RX_9_CONTROL ++ #define DMA_M2P_TX_8_BASE DMAMP_TX_8_CONTROL ++ ++ #define M2P_OFFSET_CONTROL 0x0000 ++ #define M2P_OFFSET_INTERRUPT 0x0004 ++ #define M2P_OFFSET_PPALLOC 0x0008 ++ #define M2P_OFFSET_STATUS 0x000C ++ #define M2P_OFFSET_REMAIN 0x0014 ++ #define M2P_OFFSET_MAXCNT0 0x0020 ++ #define M2P_OFFSET_BASE0 0x0024 ++ #define M2P_OFFSET_CURRENT0 0x0028 ++ #define M2P_OFFSET_MAXCNT1 0x0030 ++ #define M2P_OFFSET_BASE1 0x0034 ++ #define M2P_OFFSET_CURRENT1 0x0038 ++ ++ #define M2M_OFFSET_CONTROL 0x0000 ++ #define M2M_OFFSET_INTERRUPT 0x0004 ++ #define M2M_OFFSET_STATUS 0x000C ++ #define M2M_OFFSET_BCR0 0x0010 ++ #define M2M_OFFSET_BCR1 0x0014 ++ #define M2M_OFFSET_SAR_BASE0 0x0018 ++ #define M2M_OFFSET_SAR_BASE1 0x001C ++ #define M2M_OFFSET_SAR_CURRENT0 0x0024 ++ #define M2M_OFFSET_SAR_CURRENT1 0x0028 ++ #define M2M_OFFSET_DAR_BASE0 0x002C ++ #define M2M_OFFSET_DAR_BASE1 0x0030 ++ #define M2M_OFFSET_DAR_CURRENT0 0x0034 ++ #define M2M_OFFSET_DAR_CURRENT1 0x003C ++ ++ ++ ++ /* 8003_0000 - 8003_ffff: Raster */ ++ #define RASTER_OFFSET 0x030000 ++ #define RASTER_BASE (EP93XX_AHB_VIRT_BASE|RASTER_OFFSET) ++ #define VLINESTOTAL (RASTER_BASE+0x00) ++ #define VSYNCSTRTSTOP (RASTER_BASE+0x04) ++ #define VACTIVESTRTSTOP (RASTER_BASE+0x08) ++ #define VCLKSTRTSTOP (RASTER_BASE+0x0C) ++ #define HCLKSTOTAL (RASTER_BASE+0x10) ++ #define HSYNCSTRTSTOP (RASTER_BASE+0x14) ++ #define HACTIVESTRTSTOP (RASTER_BASE+0x18) ++ #define HCLKSTRTSTOP (RASTER_BASE+0x1C) ++ #define BRIGHTNESS (RASTER_BASE+0x20) ++ #define VIDEOATTRIBS (RASTER_BASE+0x24) ++ #define VIDSCRNPAGE (RASTER_BASE+0x28) ++ #define VIDSCRNHPG (RASTER_BASE+0x2C) ++ #define SCRNLINES (RASTER_BASE+0x30) ++ #define LINELENGTH (RASTER_BASE+0x34) ++ #define VLINESTEP (RASTER_BASE+0x38) ++ #define LINECARRY (RASTER_BASE+0x3C) ++ #define BLINKRATE (RASTER_BASE+0x40) ++ #define BLINKMASK (RASTER_BASE+0x44) ++ #define BLINKPATTRN (RASTER_BASE+0x48) ++ #define PATTRNMASK (RASTER_BASE+0x4C) ++ #define BG_OFFSET (RASTER_BASE+0x50) ++ #define PIXELMODE (RASTER_BASE+0x54) ++ #define PARLLIFOUT (RASTER_BASE+0x58) ++ #define PARLLIFIN (RASTER_BASE+0x5C) ++ #define CURSOR_ADR_START (RASTER_BASE+0x60) ++ #define CURSOR_ADR_RESET (RASTER_BASE+0x64) ++ #define CURSORSIZE (RASTER_BASE+0x68) ++ #define CURSORCOLOR1 (RASTER_BASE+0x6C) ++ #define CURSORCOLOR2 (RASTER_BASE+0x70) ++ #define CURSORXYLOC (RASTER_BASE+0x74) ++ #define CURSOR_DHSCAN_LH_YLOC (RASTER_BASE+0x78) ++ #define RASTER_SWLOCK (RASTER_BASE+0x7C) ++ #define GS_LUT (RASTER_BASE+0x80) ++ #define RASTER_TCR (RASTER_BASE+0x100) ++ #define RASTER_TISRA (RASTER_BASE+0x104) ++ #define RASTER_TISRB (RASTER_BASE+0x108) ++ #define CURSOR_TISR (RASTER_BASE+0x10C) ++ #define RASTER_TOCRA (RASTER_BASE+0x110) ++ #define RASTER_TOCRB (RASTER_BASE+0x114) ++ #define FIFO_TOCRA (RASTER_BASE+0x118) ++ #define FIFO_TOCRB (RASTER_BASE+0x11C) ++ #define BLINK_TISR (RASTER_BASE+0x120) ++ #define DAC_TISRA (RASTER_BASE+0x124) ++ #define DAC_TISRB (RASTER_BASE+0x128) ++ #define SHIFT_TISR (RASTER_BASE+0x12C) ++ #define DACMUX_TOCRA (RASTER_BASE+0x130) ++ #define DACMUX_TOCRB (RASTER_BASE+0x134) ++ #define PELMUX_TOCR (RASTER_BASE+0x138) ++ #define VIDEO_TOCRA (RASTER_BASE+0x13C) ++ #define VIDEO_TOCRB (RASTER_BASE+0x140) ++ #define YCRCB_TOCR (RASTER_BASE+0x144) ++ #define CURSOR_TOCR (RASTER_BASE+0x148) ++ #define VIDEO_TOCRC (RASTER_BASE+0x14C) ++ #define SHIFT_TOCR (RASTER_BASE+0x150) ++ #define BLINK_TOCR (RASTER_BASE+0x154) ++ #define RASTER_TCER (RASTER_BASE+0x180) ++ #define SIGVAL (RASTER_BASE+0x200) ++ #define SIGCTL (RASTER_BASE+0x204) ++ #define VSIGSTRTSTOP (RASTER_BASE+0x208) ++ #define HSIGSTRTSTOP (RASTER_BASE+0x20C) ++ #define SIGCLR (RASTER_BASE+0x210) ++ #define ACRATE (RASTER_BASE+0x214) ++ #define LUTCONT (RASTER_BASE+0x218) ++ #define VBLANKSTRTSTOP (RASTER_BASE+0x228) ++ #define HBLANKSTRTSTOP (RASTER_BASE+0x22C) ++ #define LUT (RASTER_BASE+0x400) ++ #define CURSORBLINK1 (RASTER_BASE+0x21C) ++ #define CURSORBLINK2 (RASTER_BASE+0x220) ++ #define CURSORBLINK (RASTER_BASE+0x224) ++ #define EOLOFFSET (RASTER_BASE+0x230) ++ #define FIFOLEVEL (RASTER_BASE+0x234) ++ #define GS_LUT2 (RASTER_BASE+0x280) ++ #define GS_LUT3 (RASTER_BASE+0x300) ++ #define COLOR_LUT (RASTER_BASE+0x400) ++ ++ /* 8004_0000 - 8004_ffff: Graphics */ ++ #define GRAPHICS_OFFSET 0x040000 ++ #define GRAPHICS_BASE (EP93XX_AHB_VIRT_BASE|GRAPHICS_OFFSET) ++ #define SRCPIXELSTRT (GRAPHICS_BASE+0x00) ++ #define DESTPIXELSTRT (GRAPHICS_BASE+0x04) ++ #define BLKSRCSTRT (GRAPHICS_BASE+0x08) ++ #define BLKDSTSTRT (GRAPHICS_BASE+0x0C) ++ #define BLKSRCWIDTH (GRAPHICS_BASE+0x10) ++ #define SRCLINELENGTH (GRAPHICS_BASE+0x14) ++ #define BLKDESTWIDTH (GRAPHICS_BASE+0x18) ++ #define BLKDESTHEIGHT (GRAPHICS_BASE+0x1C) ++ #define DESTLINELENGTH (GRAPHICS_BASE+0x20) ++ #define BLOCKCTRL (GRAPHICS_BASE+0x24) ++ #define TRANSPATTRN (GRAPHICS_BASE+0x28) ++ #define BLOCKMASK (GRAPHICS_BASE+0x2C) ++ #define BACKGROUND (GRAPHICS_BASE+0x30) ++ #define LINEINC (GRAPHICS_BASE+0x34) ++ #define LINEINIT (GRAPHICS_BASE+0x38) ++ #define LINEPATTRN (GRAPHICS_BASE+0x3C) ++ ++ ++ /* 800B_0000 - 800B_FFFF: VIC 0 */ ++ #define VIC0_OFFSET 0x0B0000 ++ #define VIC0_BASE (EP93XX_AHB_VIRT_BASE|VIC0_OFFSET) ++ #define VIC0 (VIC0_BASE+0x000) ++ #define VIC0IRQSTATUS (VIC0_BASE+0x000) /* R IRQ status register */ ++ #define VIC0FIQSTATUS (VIC0_BASE+0x004) /* R FIQ status register */ ++ #define VIC0RAWINTR (VIC0_BASE+0x008) /* R Raw interrupt status register */ ++ #define VIC0INTSELECT (VIC0_BASE+0x00C) /* R/W Interrupt select register */ ++ #define VIC0INTENABLE (VIC0_BASE+0x010) /* R/W Interrupt enable register */ ++ #define VIC0INTENCLEAR (VIC0_BASE+0x014) /* W Interrupt enable clear register */ ++ #define VIC0SOFTINT (VIC0_BASE+0x018) /* R/W Software interrupt register */ ++ #define VIC0SOFTINTCLEAR (VIC0_BASE+0x01C) /* R/W Software interrupt clear register */ ++ #define VIC0PROTECTION (VIC0_BASE+0x020) /* R/W Protection enable register */ ++ #define VIC0VECTADDR (VIC0_BASE+0x030) /* R/W Vector address register */ ++ #define VIC0DEFVECTADDR (VIC0_BASE+0x034) /* R/W Default vector address register */ ++ #define VIC0VECTADDR00 (VIC0_BASE+0x100) /* R/W Vector address 00 register */ ++ #define VIC0VECTADDR01 (VIC0_BASE+0x104) /* R/W Vector address 01 register */ ++ #define VIC0VECTADDR02 (VIC0_BASE+0x108) /* R/W Vector address 02 register */ ++ #define VIC0VECTADDR03 (VIC0_BASE+0x10C) /* R/W Vector address 03 register */ ++ #define VIC0VECTADDR04 (VIC0_BASE+0x110) /* R/W Vector address 04 register */ ++ #define VIC0VECTADDR05 (VIC0_BASE+0x114) /* R/W Vector address 05 register */ ++ #define VIC0VECTADDR06 (VIC0_BASE+0x118) /* R/W Vector address 06 register */ ++ #define VIC0VECTADDR07 (VIC0_BASE+0x11C) /* R/W Vector address 07 register */ ++ #define VIC0VECTADDR08 (VIC0_BASE+0x120) /* R/W Vector address 08 register */ ++ #define VIC0VECTADDR09 (VIC0_BASE+0x124) /* R/W Vector address 09 register */ ++ #define VIC0VECTADDR10 (VIC0_BASE+0x128) /* R/W Vector address 10 register */ ++ #define VIC0VECTADDR11 (VIC0_BASE+0x12C) /* R/W Vector address 11 register */ ++ #define VIC0VECTADDR12 (VIC0_BASE+0x130) /* R/W Vector address 12 register */ ++ #define VIC0VECTADDR13 (VIC0_BASE+0x134) /* R/W Vector address 13 register */ ++ #define VIC0VECTADDR14 (VIC0_BASE+0x138) /* R/W Vector address 14 register */ ++ #define VIC0VECTADDR15 (VIC0_BASE+0x13C) /* R/W Vector address 15 register */ ++ #define VIC0VECTCNTL00 (VIC0_BASE+0x200) /* R/W Vector control 00 register */ ++ #define VIC0VECTCNTL01 (VIC0_BASE+0x204) /* R/W Vector control 01 register */ ++ #define VIC0VECTCNTL02 (VIC0_BASE+0x208) /* R/W Vector control 02 register */ ++ #define VIC0VECTCNTL03 (VIC0_BASE+0x20C) /* R/W Vector control 03 register */ ++ #define VIC0VECTCNTL04 (VIC0_BASE+0x210) /* R/W Vector control 04 register */ ++ #define VIC0VECTCNTL05 (VIC0_BASE+0x214) /* R/W Vector control 05 register */ ++ #define VIC0VECTCNTL06 (VIC0_BASE+0x218) /* R/W Vector control 06 register */ ++ #define VIC0VECTCNTL07 (VIC0_BASE+0x21C) /* R/W Vector control 07 register */ ++ #define VIC0VECTCNTL08 (VIC0_BASE+0x220) /* R/W Vector control 08 register */ ++ #define VIC0VECTCNTL09 (VIC0_BASE+0x224) /* R/W Vector control 09 register */ ++ #define VIC0VECTCNTL10 (VIC0_BASE+0x228) /* R/W Vector control 10 register */ ++ #define VIC0VECTCNTL11 (VIC0_BASE+0x22C) /* R/W Vector control 11 register */ ++ #define VIC0VECTCNTL12 (VIC0_BASE+0x230) /* R/W Vector control 12 register */ ++ #define VIC0VECTCNTL13 (VIC0_BASE+0x234) /* R/W Vector control 13 register */ ++ #define VIC0VECTCNTL14 (VIC0_BASE+0x238) /* R/W Vector control 14 register */ ++ #define VIC0VECTCNTL15 (VIC0_BASE+0x23C) /* R/W Vector control 15 register */ ++ #define VIC0ITCR (VIC0_BASE+0x300) /* R/W Test control register */ ++ #define VIC0ITIP1 (VIC0_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN)*/ ++ #define VIC0ITIP2 (VIC0_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ ++ #define VIC0ITOP1 (VIC0_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ ++ #define VIC0ITOP2 (VIC0_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ ++ #define VIC0PERIPHID0 (VIC0_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ ++ #define VIC0PERIPHID1 (VIC0_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ ++ #define VIC0PERIPHID2 (VIC0_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ ++ #define VIC0PERIPHID3 (VIC0_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ ++ ++ ++ /* 800C_0000 - 800C_FFFF: VIC 0 */ ++ #define VIC1_OFFSET 0x0C0000 ++ #define VIC1_BASE (EP93XX_AHB_VIRT_BASE|VIC1_OFFSET) ++ #define VIC1 (VIC1_BASE+0x000) ++ #define VIC1IRQSTATUS (VIC1_BASE+0x000) /* R IRQ status register */ ++ #define VIC1FIQSTATUS (VIC1_BASE+0x004) /* R FIQ status register */ ++ #define VIC1RAWINTR (VIC1_BASE+0x008) /* R Raw interrupt status register */ ++ #define VIC1INTSELECT (VIC1_BASE+0x00C) /* R/W Interrupt select register */ ++ #define VIC1INTENABLE (VIC1_BASE+0x010) /* R/W Interrupt enable register */ ++ #define VIC1INTENCLEAR (VIC1_BASE+0x014) /* W Interrupt enable clear register */ ++ #define VIC1SOFTINT (VIC1_BASE+0x018) /* R/W Software interrupt register */ ++ #define VIC1SOFTINTCLEAR (VIC1_BASE+0x01C) /* R/W Software interrupt clear register */ ++ #define VIC1PROTECTION (VIC1_BASE+0x020) /* R/W Protection enable register */ ++ #define VIC1VECTADDR (VIC1_BASE+0x030) /* R/W Vector address register */ ++ #define VIC1DEFVECTADDR (VIC1_BASE+0x034) /* R/W Default vector address register */ ++ #define VIC1VECTADDR00 (VIC1_BASE+0x100) /* R/W Vector address 00 register */ ++ #define VIC1VECTADDR01 (VIC1_BASE+0x104) /* R/W Vector address 01 register */ ++ #define VIC1VECTADDR02 (VIC1_BASE+0x108) /* R/W Vector address 02 register */ ++ #define VIC1VECTADDR03 (VIC1_BASE+0x10C) /* R/W Vector address 03 register */ ++ #define VIC1VECTADDR04 (VIC1_BASE+0x110) /* R/W Vector address 04 register */ ++ #define VIC1VECTADDR05 (VIC1_BASE+0x114) /* R/W Vector address 05 register */ ++ #define VIC1VECTADDR06 (VIC1_BASE+0x118) /* R/W Vector address 06 register */ ++ #define VIC1VECTADDR07 (VIC1_BASE+0x11C) /* R/W Vector address 07 register */ ++ #define VIC1VECTADDR08 (VIC1_BASE+0x120) /* R/W Vector address 08 register */ ++ #define VIC1VECTADDR09 (VIC1_BASE+0x124) /* R/W Vector address 09 register */ ++ #define VIC1VECTADDR10 (VIC1_BASE+0x128) /* R/W Vector address 10 register */ ++ #define VIC1VECTADDR11 (VIC1_BASE+0x12C) /* R/W Vector address 11 register */ ++ #define VIC1VECTADDR12 (VIC1_BASE+0x130) /* R/W Vector address 12 register */ ++ #define VIC1VECTADDR13 (VIC1_BASE+0x134) /* R/W Vector address 13 register */ ++ #define VIC1VECTADDR14 (VIC1_BASE+0x138) /* R/W Vector address 14 register */ ++ #define VIC1VECTADDR15 (VIC1_BASE+0x13C) /* R/W Vector address 15 register */ ++ #define VIC1VECTCNTL00 (VIC1_BASE+0x200) /* R/W Vector control 00 register */ ++ #define VIC1VECTCNTL01 (VIC1_BASE+0x204) /* R/W Vector control 01 register */ ++ #define VIC1VECTCNTL02 (VIC1_BASE+0x208) /* R/W Vector control 02 register */ ++ #define VIC1VECTCNTL03 (VIC1_BASE+0x20C) /* R/W Vector control 03 register */ ++ #define VIC1VECTCNTL04 (VIC1_BASE+0x210) /* R/W Vector control 04 register */ ++ #define VIC1VECTCNTL05 (VIC1_BASE+0x214) /* R/W Vector control 05 register */ ++ #define VIC1VECTCNTL06 (VIC1_BASE+0x218) /* R/W Vector control 06 register */ ++ #define VIC1VECTCNTL07 (VIC1_BASE+0x21C) /* R/W Vector control 07 register */ ++ #define VIC1VECTCNTL08 (VIC1_BASE+0x220) /* R/W Vector control 08 register */ ++ #define VIC1VECTCNTL09 (VIC1_BASE+0x224) /* R/W Vector control 09 register */ ++ #define VIC1VECTCNTL10 (VIC1_BASE+0x228) /* R/W Vector control 10 register */ ++ #define VIC1VECTCNTL11 (VIC1_BASE+0x22C) /* R/W Vector control 11 register */ ++ #define VIC1VECTCNTL12 (VIC1_BASE+0x230) /* R/W Vector control 12 register */ ++ #define VIC1VECTCNTL13 (VIC1_BASE+0x234) /* R/W Vector control 13 register */ ++ #define VIC1VECTCNTL14 (VIC1_BASE+0x238) /* R/W Vector control 14 register */ ++ #define VIC1VECTCNTL15 (VIC1_BASE+0x23C) /* R/W Vector control 15 register */ ++ #define VIC1ITCR (VIC1_BASE+0x300) /* R/W Test control register */ ++ #define VIC1ITIP1 (VIC1_BASE+0x304) /* R Test input register (nVICIRQIN/nVICFIQIN)*/ ++ #define VIC1ITIP2 (VIC1_BASE+0x308) /* R Test input register (VICVECTADDRIN) */ ++ #define VIC1ITOP1 (VIC1_BASE+0x30C) /* R Test output register (nVICIRQ/nVICFIQ) */ ++ #define VIC1ITOP2 (VIC1_BASE+0x310) /* R Test output register (VICVECTADDROUT) */ ++ #define VIC1PERIPHID0 (VIC1_BASE+0xFE0) /* R Peripheral ID register bits 7:0 */ ++ #define VIC1PERIPHID1 (VIC1_BASE+0xFE4) /* R Peripheral ID register bits 15:8 */ ++ #define VIC1PERIPHID2 (VIC1_BASE+0xFE8) /* R Peripheral ID register bits 23:16 */ ++ #define VIC1PERIPHID3 (VIC1_BASE+0xFEC) /* R Peripheral ID register bits 31:24 */ ++ ++ ++ /////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ///////////////////////////////////APB///////////////////////////////////////////////////////////////////// ++ /////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ /* 8081_0000 - 8081_ffff: Timers */ ++ #define TIMERS_OFFSET 0x010000 ++ #define TIMERS_BASE (EP93XX_APB_VIRT_BASE|TIMERS_OFFSET) ++ ++ #define TIMER1LOAD (TIMERS_BASE+0x00) ++ #define TIMER1VALUE (TIMERS_BASE+0x04) ++ #define TIMER1CONTROL (TIMERS_BASE+0x08) ++ #define TIMER1CLEAR (TIMERS_BASE+0x0C) ++ #define TIMER1TEST (TIMERS_BASE+0x10) ++ ++ #define TIMER2LOAD (TIMERS_BASE+0x20) ++ #define TIMER2VALUE (TIMERS_BASE+0x24) ++ #define TIMER2CONTROL (TIMERS_BASE+0x28) ++ #define TIMER2CLEAR (TIMERS_BASE+0x2C) ++ #define TIMER2TEST (TIMERS_BASE+0x30) ++ ++ #define TIMER3LOAD (TIMERS_BASE+0x80) ++ #define TIMER3VALUE (TIMERS_BASE+0x84) ++ #define TIMER3CONTROL (TIMERS_BASE+0x88) ++ #define TIMER3CLEAR (TIMERS_BASE+0x8C) ++ #define TIMER3TEST (TIMERS_BASE+0x90) ++ ++ #define TTIMERBZCONT (TIMERS_BASE+0x40) ++ ++ #define TIMER4VALUELOW (TIMERS_BASE+0x60) ++ #define TIMER4VALUEHIGH (TIMERS_BASE+0x64) ++ ++ ++ /* 8082_0000 - 8082_ffff: I2S */ ++ #define I2S_OFFSET 0x020000 ++ #define I2S_BASE (EP93XX_APB_VIRT_BASE|I2S_OFFSET) ++ #define I2S_PHYS_BASE (EP93XX_APB_PHYS_BASE + I2S_OFFSET) ++ ++ ++ ++ #define I2STxClkCfg (I2S_BASE+0x00) /* 8082.0000 R/W Transmitter clock config register */ ++ #define I2SRxClkCfg (I2S_BASE+0x04) /* 8082.0004 R/W Receiver clock config register */ ++ #define I2SGlSts (I2S_BASE+0x08) /* 8082.0008 R/W SAI Global Status register. */ ++ #define I2SGlCtrl (I2S_BASE+0x0C) /* 8082.000C R/W SAI Global Control register */ ++ ++ #define I2STX0Lft (I2S_BASE+0x10) /* 8082.0010 R/W Left TX data reg for channel 0 */ ++ #define I2STX0Rt (I2S_BASE+0x14) /* 8082.0014 R/W Right TX data reg for channel 0 */ ++ #define I2STX1Lft (I2S_BASE+0x18) /* 8082.0018 R/W Left TX data reg for channel 1 */ ++ #define I2STX1Rt (I2S_BASE+0x1C) /* 8082.001C R/W Right TX data reg for channel 1 */ ++ #define I2STX2Lft (I2S_BASE+0x20) /* 8082.0020 R/W Left TX data reg for channel 2 */ ++ #define I2STX2Rt (I2S_BASE+0x24) /* 8082.0024 R/W Right TX data reg for channel 2 */ ++ ++ #define I2STXLinCtrlData (I2S_BASE+0x28) /* 8082.0028 R/W TX Line Control data register */ ++ #define I2STXCtrl (I2S_BASE+0x2C) /* 8082.002C R/W TX Control register */ ++ #define I2STXWrdLen (I2S_BASE+0x30) /* 8082.0030 R/W TX Word Length */ ++ #define I2STX0En (I2S_BASE+0x34) /* 8082.0034 R/W TX0 Channel Enable */ ++ #define I2STX1En (I2S_BASE+0x38) /* 8082.0038 R/W TX1 Channel Enable */ ++ #define I2STX2En (I2S_BASE+0x3C) /* 8082.003C R/W TX2 Channel Enable */ ++ ++ #define I2SRX0Lft (I2S_BASE+0x40) /* 8082.0040 R Left RX data reg for channel 0 */ ++ #define I2SRX0Rt (I2S_BASE+0x44) /* 8082.0044 R Right RX data reg for channel 0 */ ++ #define I2SRX1Lft (I2S_BASE+0x48) /* 8082.0048 R Left RX data reg for channel 1 */ ++ #define I2SRX1Rt (I2S_BASE+0x4C) /* 8082.004c R Right RX data reg for channel 1 */ ++ #define I2SRX2Lft (I2S_BASE+0x50) /* 8082.0050 R Left RX data reg for channel 2 */ ++ #define I2SRX2Rt (I2S_BASE+0x54) /* 8082.0054 R Right RX data reg for channel 2 */ ++ ++ #define I2SRXLinCtrlData (I2S_BASE+0x58) /* 8082.0058 R/W RX Line Control data register */ ++ #define I2SRXCtrl (I2S_BASE+0x5C) /* 8082.005C R/W RX Control register */ ++ #define I2SRXWrdLen (I2S_BASE+0x60) /* 8082.0060 R/W RX Word Length */ ++ #define I2SRX0En (I2S_BASE+0x64) /* 8082.0064 R/W RX0 Channel Enable */ ++ #define I2SRX1En (I2S_BASE+0x68) /* 8082.0068 R/W RX1 Channel Enable */ ++ #define I2SRX2En (I2S_BASE+0x6C) /* 8082.006C R/W RX2 Channel Enable */ ++ ++ ++ ++ ++ /* 8084_0000 - 8084_ffff: GPIO */ ++ #define GPIO_OFFSET 0x040000 ++ #define GPIO_BASE (EP93XX_APB_VIRT_BASE|GPIO_OFFSET) ++ #define GPIO_PADR (GPIO_BASE+0x00) ++ #define GPIO_PBDR (GPIO_BASE+0x04) ++ #define GPIO_PCDR (GPIO_BASE+0x08) ++ #define GPIO_PDDR (GPIO_BASE+0x0C) ++ #define GPIO_PADDR (GPIO_BASE+0x10) ++ #define GPIO_PBDDR (GPIO_BASE+0x14) ++ #define GPIO_PCDDR (GPIO_BASE+0x18) ++ #define GPIO_PDDDR (GPIO_BASE+0x1C) ++ #define GPIO_PEDR (GPIO_BASE+0x20) ++ #define GPIO_PEDDR (GPIO_BASE+0x24) ++ // #define 0x8084.0028 Reserved ++ // #define 0x8084.002C Reserved ++ #define GPIO_PFDR (GPIO_BASE+0x30) ++ #define GPIO_PFDDR (GPIO_BASE+0x34) ++ #define GPIO_PGDR (GPIO_BASE+0x38) ++ #define GPIO_PGDDR (GPIO_BASE+0x3C) ++ #define GPIO_PHDR (GPIO_BASE+0x40) ++ #define GPIO_PHDDR (GPIO_BASE+0x44) ++ // #define 0x8084.0048 RAZ RAZ ++ #define GPIO_FINTTYPE1 (GPIO_BASE+0x4C) ++ #define GPIO_FINTTYPE2 (GPIO_BASE+0x50) ++ #define GPIO_FEOI (GPIO_BASE+0x54) /* WRITE ONLY - READ UNDEFINED */ ++ #define GPIO_FINTEN (GPIO_BASE+0x58) ++ #define GPIO_INTSTATUSF (GPIO_BASE+0x5C) ++ #define GPIO_RAWINTSTASUSF (GPIO_BASE+0x60) ++ #define GPIO_FDB (GPIO_BASE+0x64) ++ #define GPIO_PAPINDR (GPIO_BASE+0x68) ++ #define GPIO_PBPINDR (GPIO_BASE+0x6C) ++ #define GPIO_PCPINDR (GPIO_BASE+0x70) ++ #define GPIO_PDPINDR (GPIO_BASE+0x74) ++ #define GPIO_PEPINDR (GPIO_BASE+0x78) ++ #define GPIO_PFPINDR (GPIO_BASE+0x7C) ++ #define GPIO_PGPINDR (GPIO_BASE+0x80) ++ #define GPIO_PHPINDR (GPIO_BASE+0x84) ++ #define GPIO_AINTTYPE1 (GPIO_BASE+0x90) ++ #define GPIO_AINTTYPE2 (GPIO_BASE+0x94) ++ #define GPIO_AEOI (GPIO_BASE+0x98) /* WRITE ONLY - READ UNDEFINED */ ++ #define GPIO_AINTEN (GPIO_BASE+0x9C) ++ #define GPIO_INTSTATUSA (GPIO_BASE+0xA0) ++ #define GPIO_RAWINTSTSTISA (GPIO_BASE+0xA4) ++ #define GPIO_ADB (GPIO_BASE+0xA8) ++ #define GPIO_BINTTYPE1 (GPIO_BASE+0xAC) ++ #define GPIO_BINTTYPE2 (GPIO_BASE+0xB0) ++ #define GPIO_BEOI (GPIO_BASE+0xB4) /* WRITE ONLY - READ UNDEFINED */ ++ #define GPIO_BINTEN (GPIO_BASE+0xB8) ++ #define GPIO_INTSTATUSB (GPIO_BASE+0xBC) ++ #define GPIO_RAWINTSTSTISB (GPIO_BASE+0xC0) ++ #define GPIO_BDB (GPIO_BASE+0xC4) ++ #define GPIO_EEDRIVE (GPIO_BASE+0xC8) ++ //#define Reserved (GPIO_BASE+0xCC) ++ #define GPIO_TCR (GPIO_BASE+0xD0) /* Test Registers */ ++ #define GPIO_TISRA (GPIO_BASE+0xD4) /* Test Registers */ ++ #define GPIO_TISRB (GPIO_BASE+0xD8) /* Test Registers */ ++ #define GPIO_TISRC (GPIO_BASE+0xDC) /* Test Registers */ ++ #define GPIO_TISRD (GPIO_BASE+0xE0) /* Test Registers */ ++ #define GPIO_TISRE (GPIO_BASE+0xE4) /* Test Registers */ ++ #define GPIO_TISRF (GPIO_BASE+0xE8) /* Test Registers */ ++ #define GPIO_TISRG (GPIO_BASE+0xEC) /* Test Registers */ ++ #define GPIO_TISRH (GPIO_BASE+0xF0) /* Test Registers */ ++ #define GPIO_TCER (GPIO_BASE+0xF4) /* Test Registers */ ++ ++ ++ /* 8088_0000 - 8088_ffff: Ac97 Controller (AAC) */ ++ #define AC97_OFFSET 0x080000 ++ #define AC97_BASE (EP93XX_APB_VIRT_BASE|AC97_OFFSET) ++ #define EP93XX_AC97_PHY_BASE (EP93XX_APB_PHYS_BASE|AC97_OFFSET) ++ #define AC97DR1 (AC97_BASE+0x00) /* 8088.0000 R/W Data read or written from/to FIFO1 */ ++ #define AC97RXCR1 (AC97_BASE+0x04) /* 8088.0004 R/W Control register for receive */ ++ #define AC97TXCR1 (AC97_BASE+0x08) /* 8088.0008 R/W Control register for transmit */ ++ #define AC97SR1 (AC97_BASE+0x0C) /* 8088.000C R Status register */ ++ #define AC97RISR1 (AC97_BASE+0x10) /* 8088.0010 R Raw interrupt status register */ ++ #define AC97ISR1 (AC97_BASE+0x14) /* 8088.0014 R Interrupt Status */ ++ #define AC97IE1 (AC97_BASE+0x18) /* 8088.0018 R/W Interrupt Enable */ ++ /* 8088.001C Reserved - RAZ */ ++ #define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ ++ #define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */ ++ #define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ ++ #define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */ ++ #define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ ++ #define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */ ++ #define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ ++ /* 8088.003C Reserved - RAZ */ ++ #define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ ++ #define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */ ++ #define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ ++ #define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */ ++ #define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ ++ #define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */ ++ #define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ ++ /* 8088.005C Reserved - RAZ */ ++ #define AC97DR2 (AC97_BASE+0x20) /* 8088.0020 R/W Data read or written from/to FIFO2 */ ++ #define AC97RXCR2 (AC97_BASE+0x24) /* 8088.0024 R/W Control register for receive */ ++ #define AC97TXCR2 (AC97_BASE+0x28) /* 8088.0028 R/W Control register for transmit */ ++ #define AC97SR2 (AC97_BASE+0x2C) /* 8088.002C R Status register */ ++ #define AC97RISR2 (AC97_BASE+0x30) /* 8088.0030 R Raw interrupt status register */ ++ #define AC97ISR2 (AC97_BASE+0x34) /* 8088.0034 R Interrupt Status */ ++ #define AC97IE2 (AC97_BASE+0x38) /* 8088.0038 R/W Interrupt Enable */ ++ /* 8088.003C Reserved - RAZ */ ++ #define AC97DR3 (AC97_BASE+0x40) /* 8088.0040 R/W Data read or written from/to FIFO3. */ ++ #define AC97RXCR3 (AC97_BASE+0x44) /* 8088.0044 R/W Control register for receive */ ++ #define AC97TXCR3 (AC97_BASE+0x48) /* 8088.0048 R/W Control register for transmit */ ++ #define AC97SR3 (AC97_BASE+0x4C) /* 8088.004C R Status register */ ++ #define AC97RISR3 (AC97_BASE+0x50) /* 8088.0050 R Raw interrupt status register */ ++ #define AC97ISR3 (AC97_BASE+0x54) /* 8088.0054 R Interrupt Status */ ++ #define AC97IE3 (AC97_BASE+0x58) /* 8088.0058 R/W Interrupt Enable */ ++ /* 8088.005C Reserved - RAZ */ ++ #define AC97DR4 (AC97_BASE+0x60) /* 8088.0060 R/W Data read or written from/to FIFO4. */ ++ #define AC97RXCR4 (AC97_BASE+0x64) /* 8088.0064 R/W Control register for receive */ ++ #define AC97TXCR4 (AC97_BASE+0x68) /* 8088.0068 R/W Control register for transmit */ ++ #define AC97SR4 (AC97_BASE+0x6C) /* 8088.006C R Status register */ ++ #define AC97RISR4 (AC97_BASE+0x70) /* 8088.0070 R Raw interrupt status register */ ++ #define AC97ISR4 (AC97_BASE+0x74) /* 8088.0074 R Interrupt Status */ ++ #define AC97IE4 (AC97_BASE+0x78) /* 8088.0078 R/W Interrupt Enable */ ++ /* 8088.007C Reserved - RAZ */ ++ #define AC97S1DATA (AC97_BASE+0x80) /* 8088.0080 R/W Data received/transmitted on SLOT1 */ ++ #define AC97S2DATA (AC97_BASE+0x84) /* 8088.0084 R/W Data received/transmitted on SLOT2 */ ++ #define AC97S12DATA (AC97_BASE+0x88) /* 8088.0088 R/W Data received/transmitted on SLOT12 */ ++ #define AC97RGIS (AC97_BASE+0x8C) /* 8088.008C R/W Raw Global interrupt status register*/ ++ #define AC97GIS (AC97_BASE+0x90) /* 8088.0090 R Global interrupt status register */ ++ #define AC97IM (AC97_BASE+0x94) /* 8088.0094 R/W Interrupt mask register */ ++ #define AC97EOI (AC97_BASE+0x98) /* 8088.0098 W Interrupt clear register */ ++ #define AC97GCR (AC97_BASE+0x9C) /* 8088.009C R/W Main Control register */ ++ #define AC97RESET (AC97_BASE+0xA0) /* 8088.00A0 R/W RESET control register. */ ++ #define AC97SYNC (AC97_BASE+0xA4) /* 8088.00A4 R/W SYNC control register. */ ++ #define AC97GCIS (AC97_BASE+0xA8) /* 8088.00A8 R Global chan FIFO int status register */ ++ ++ ++ /* 808A_0000 - 808A_ffff: SSP - (SPI) */ ++ #define SSP_OFFSET 0x0A0000 ++ #define SSP_BASE (EP93XX_APB_VIRT_BASE|SSP_OFFSET) ++ #define SSPCR0 (SSP_BASE+0x00) ++ #define SSPCR1 (SSP_BASE+0x04) ++ #define SSPDR (SSP_BASE+0x08) ++ #define SSPSR (SSP_BASE+0x0c) ++ #define SSPCPSR (SSP_BASE+0x10) ++ #define SSPIIR (SSP_BASE+0x14) ++ ++ ++ /*808B_0000 - 808B_ffff: IrDA */ ++ #define IRDA_OFFSET 0x0B0000 ++ #define IRDA_BASE (EP93XX_APB_VIRT_BASE|IRDA_OFFSET) ++ #define IrEnable (IRDA_BASE+0x00) ++ #define IrCtrl (IRDA_BASE+0x04) ++ #define IrAdrMatchVal (IRDA_BASE+0x08) ++ #define IrFlag (IRDA_BASE+0x0C) ++ #define IrData (IRDA_BASE+0x10) ++ #define IrDataTail1 (IRDA_BASE+0x14) ++ #define IrDataTail2 (IRDA_BASE+0x18) ++ #define IrDataTail3 (IRDA_BASE+0x1c) ++ #define IrRIB (IRDA_BASE+0x20) ++ #define IrTR0 (IRDA_BASE+0x24) ++ #define IrDMACR (IRDA_BASE+0x28) ++ #define SIRTR0 (IRDA_BASE+0x30) ++ #define MISR (IRDA_BASE+0x80) ++ #define MIMR (IRDA_BASE+0x84) ++ #define MIIR (IRDA_BASE+0x88) ++ #define FISR (IRDA_BASE+0x180) ++ #define FIMR (IRDA_BASE+0x184) ++ #define FIIR (IRDA_BASE+0x188) ++ ++ ++ /* 808C_0000 - 808C_ffff: UART1 */ ++ #define UART1_OFFSET 0x0C0000 ++ #define UART1_BASE (EP93XX_APB_VIRT_BASE|UART1_OFFSET) ++ #define UART1_BASE_VIRT (EP93XX_APB_PHYS_BASE|UART1_OFFSET) ++ #define UART1DR (UART1_BASE+0x000) ++ #define UART1RSR (UART1_BASE+0x004) ++ #define UART1ECR (UART1_BASE+0x004) ++ #define UART1CR_H (UART1_BASE+0x008) ++ #define UART1CR_M (UART1_BASE+0x00C) ++ #define UART1CR_L (UART1_BASE+0x010) ++ #define UART1CR (UART1_BASE+0x014) ++ #define UART1FR (UART1_BASE+0x018) ++ #define UART1IIR (UART1_BASE+0x01C) ++ #define UART1ICR (UART1_BASE+0x01C) ++ #define UART1ILPR (UART1_BASE+0x020) ++ #define UART1DMACR (UART1_BASE+0x028) ++ #define UART1TMR (UART1_BASE+0x084) ++ #define UART1MCR (UART1_BASE+0x100) ++ #define UART1MSR (UART1_BASE+0x104) ++ #define UART1TCR (UART1_BASE+0x108) ++ #define UART1TISR (UART1_BASE+0x10C) ++ #define UART1TOCR (UART1_BASE+0x110) ++ #define HDLC1CR (UART1_BASE+0x20c) ++ #define HDLC1AMV (UART1_BASE+0x210) ++ #define HDLC1AMSK (UART1_BASE+0x214) ++ #define HDLC1RIB (UART1_BASE+0x218) ++ #define HDLC1SR (UART1_BASE+0x21c) ++ ++ /* Offsets to the various UART registers */ ++ #define UARTDR 0x0000 ++ #define UARTRSR 0x0004 ++ #define UARTECR 0x0004 ++ #define UARTCR_H 0x0008 ++ #define UARTCR_M 0x000C ++ #define UARTCR_L 0x0010 ++ #define UARTCR 0x0014 ++ #define UARTFR 0x0018 ++ #define UARTIIR 0x001C ++ #define UARTICR 0x001C ++ #define UARTMCR 0x0100 ++ #define UARTMSR 0x0104 ++ ++ /* 808d_0000 - 808d_ffff: UART2 */ ++ #define UART2_OFFSET 0x0D0000 ++ #define UART2_BASE (EP93XX_APB_VIRT_BASE|UART2_OFFSET) ++ #define UART2_BASE_VIRT (EP93XX_APB_PHYS_BASE|UART2_OFFSET) ++ #define UART2DR (UART2_BASE+0x00) ++ #define UART2RSR (UART2_BASE+0x04) /* Read */ ++ #define UART2ECR (UART2_BASE+0x04) /* Write */ ++ #define UART2CR_H (UART2_BASE+0x08) ++ #define UART2CR_M (UART2_BASE+0x0C) ++ #define UART2CR_L (UART2_BASE+0x10) ++ #define UART2CR (UART2_BASE+0x14) ++ #define UART2FR (UART2_BASE+0x18) ++ #define UART2IIR (UART2_BASE+0x1C) /* Read */ ++ #define UART2ICR (UART2_BASE+0x1C) /* Write */ ++ #define UART2ILPR (UART2_BASE+0x20) ++ #define UART2DMACR (UART2_BASE+0x28) ++ #define UART2TMR (UART2_BASE+0x84) ++ ++ ++ /* 808e_0000 - 808e_ffff: UART3 */ ++ #define UART3_OFFSET 0x0E0000 ++ #define UART3_BASE (EP93XX_APB_VIRT_BASE|UART3_OFFSET) ++ #define UART3_BASE_VIRT (EP93XX_APB_PHYS_BASE|UART3_OFFSET) ++ #define UART3DR (UART3_BASE+0x00) ++ #define UART3RSR (UART3_BASE+0x04) /* Read */ ++ #define UART3ECR (UART3_BASE+0x04) /* Write */ ++ #define UART3CR_H (UART3_BASE+0x08) ++ #define UART3CR_M (UART3_BASE+0x0C) ++ #define UART3CR_L (UART3_BASE+0x10) ++ #define UART3CR (UART3_BASE+0x14) ++ #define UART3FR (UART3_BASE+0x18) ++ #define UART3IIR (UART3_BASE+0x1C) /* Read */ ++ #define UART3ICR (UART3_BASE+0x1C) /* Write */ ++ #define UART3ILPR (UART3_BASE+0x20) ++ #define UART3DMACR (UART3_BASE+0x28) ++ #define UART3TCR (UART3_BASE+0x80) ++ #define UART3TISR (UART3_BASE+0x88) ++ #define UART3TOCR (UART3_BASE+0x8C) ++ #define UART3TMR (UART3_BASE+0x84) ++ #define UART3MCR (UART3_BASE+0x100) /* Modem Control Reg */ ++ #define UART3MSR (UART3_BASE+0x104) /* Modem Status Reg */ ++ ++ #define UART3HDLCCR (UART3_BASE+0x20C) /* HDLC Registers */ ++ #define UART3HDLCAMV (UART3_BASE+0x210) /* HDLC Registers */ ++ #define UART3HDLCAMSK (UART3_BASE+0x214) /* HDLC Registers */ ++ #define UART3HDLCCRIB (UART3_BASE+0x218) /* HDLC Registers */ ++ #define UART3HDLCSR (UART3_BASE+0x21C) /* HDLC Registers */ ++ ++ /* 808f_0000 - 808f_ffff: KEY Matrix */ ++ #define KEY_OFFSET 0x0F0000 ++ #define KEY_BASE (EP93XX_APB_VIRT_BASE|KEY_OFFSET) ++ #define SCANINIT (KEY_BASE+0x00) ++ #define KEY_DIAG (KEY_BASE+0x04) ++ #define KEY_REG (KEY_BASE+0x08) ++ #define KEY_TCR (KEY_BASE+0x10) ++ #define KEY_TISR (KEY_BASE+0x14) ++ #define KEY_TOCR (KEY_BASE+0x18) ++ ++ ++ #define TOUCH_OFFSET 0x100000 ++ #define TOUCH_BASE (EP93XX_APB_VIRT_BASE|TOUCH_OFFSET) ++ #define TSSetup (TOUCH_BASE+0x00) /* R/W touchscreen controller setup control register. */ ++ #define TSXYMaxMin (TOUCH_BASE+0x04) /* R/W touchscreen controller max/min register. */ ++ #define TSXYResult (TOUCH_BASE+0x08) /* R touchscreen controller result register. */ ++ #define TSDischarge (TOUCH_BASE+0x0C) /* LOCKED R/W touchscreen Switch Matrix control register. */ ++ #define TSXSample (TOUCH_BASE+0x10) /* LOCKED R/W touchscreen Switch Matrix control register. */ ++ #define TSYSample (TOUCH_BASE+0x14) /* LOCKED R/W touchscreen Switch Matrix control register. */ ++ #define TSDirect (TOUCH_BASE+0x18) /* LOCKED R/W touchscreen Switch Matrix control register. */ ++ #define TSDetect (TOUCH_BASE+0x1C) /* LOCKED R/W touchscreen Switch Matrix control register. */ ++ #define TSSWLock (TOUCH_BASE+0x20) /* NA R/W touchscreen software lock register. */ ++ #define TSSetup2 (TOUCH_BASE+0x24) /* R/W touchscreen setup control register #2. */ ++ ++ ++ /* 8093_0000 - 8093_ffff: CSC/Syscon PLL, clock control, & misc. stuff */ ++ #define SYSCON_OFFSET 0x130000 ++ #define SYSCON_BASE ((EP93XX_APB_VIRT_BASE)|SYSCON_OFFSET) ++ #define SYSCON_PWRSR (SYSCON_BASE+0x0000) ++ #define SYSCON_PWRCNT (SYSCON_BASE+0x0004) ++ #define SYSCON_HALT (SYSCON_BASE+0x0008) ++ #define SYSCON_STBY (SYSCON_BASE+0x000c) ++ #define SYSCON_BLEOI (SYSCON_BASE+0x0010) ++ #define SYSCON_MCEOI (SYSCON_BASE+0x0014) ++ #define SYSCON_TEOI (SYSCON_BASE+0x0018) ++ #define SYSCON_STFCLR (SYSCON_BASE+0x001c) ++ #define SYSCON_CLKSET1 (SYSCON_BASE+0x0020) ++ #define SYSCON_CLKSET2 (SYSCON_BASE+0x0024) ++ #define SYSCON_RESV00 (SYSCON_BASE+0x0028) ++ #define SYSCON_RESV01 (SYSCON_BASE+0x002c) ++ #define SYSCON_RESV02 (SYSCON_BASE+0x0030) ++ #define SYSCON_RESV03 (SYSCON_BASE+0x0034) ++ #define SYSCON_RESV04 (SYSCON_BASE+0x0038) ++ #define SYSCON_RESV05 (SYSCON_BASE+0x003c) ++ #define SYSCON_SCRREG0 (SYSCON_BASE+0x0040) ++ #define SYSCON_SCRREG1 (SYSCON_BASE+0x0044) ++ #define SYSCON_CLKTEST (SYSCON_BASE+0x0048) ++ #define SYSCON_USBRESET (SYSCON_BASE+0x004c) ++ #define SYSCON_APBWAIT (SYSCON_BASE+0x0050) ++ #define SYSCON_BMAR (SYSCON_BASE+0x0054) ++ #define SYSCON_BOOTCLR (SYSCON_BASE+0x0058) ++ #define SYSCON_DEVCFG (SYSCON_BASE+0x0080) ++ #define SYSCON_VIDDIV (SYSCON_BASE+0x0084) ++ #define SYSCON_MIRDIV (SYSCON_BASE+0x0088) ++ #define SYSCON_I2SDIV (SYSCON_BASE+0x008C) ++ #define SYSCON_KTDIV (SYSCON_BASE+0x0090) ++ #define SYSCON_CHIPID (SYSCON_BASE+0x0094) ++ #define SYSCON_TSTCR (SYSCON_BASE+0x0098) ++ #define SYSCON_SYSCFG (SYSCON_BASE+0x009C) ++ #define SYSCON_SWLOCK (SYSCON_BASE+0x00C0) ++ ++ #define SYSCON_DEVCFG_KEYS 0x00000002 ++ #define SYSCON_DEVCFG_RasOnP3 0x00000010 ++ #define SYSCON_DEVCFG_GONK 0x08000000 ++ ++ #define SYSCON_KTDIV_KEN 0x00008000 ++ ++ ++ ++ ++ ++ ++ ++ ++ + ++ ++ ++ // + #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) ++ #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) + + #define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) + #define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) + + #define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) ++ #define EP93XX_RASTER_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00030000) + + #define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) ++ #define EP93XX_GRAPHICS_ACCEL_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00040000 ++ + + #define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) + +*************** +*** 116,123 **** + #define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 + #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) + #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) + #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) + #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 + #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) + + #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) +--- 1143,1155 ---- + #define EP93XX_SYSCON_CLOCK_USH_EN 0x10000000 + #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) + #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) ++ #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) ++ #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) + #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) + #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 ++ ++ #define EP93XX_SYSCON_BMAR EP93XX_SYSCON_REG(0x54) ++ #define EP93XX_SYSCON_CHIPID EP93XX_SYSCON_REG(0x94) + #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) + + #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/hardware.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/hardware.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/hardware.h 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/hardware.h 2007-07-12 14:20:47.000000000 -0500 @@ -3,7 +3,9 @@ */ #include "ep93xx-regs.h" - +#include "regs_touch.h" +#include "regs_syscon.h" +#include "regs_raster.h" #define pcibios_assign_all_busses() 0 #include "platform.h" diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/irqs.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/irqs.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/irqs.h 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/irqs.h 2007-07-12 14:20:47.000000000 -0500 @@ -34,6 +34,7 @@ #define IRQ_EP93XX_UART3TX 28 #define IRQ_EP93XX_KEY 29 #define IRQ_EP93XX_TOUCH 30 +#define IRQ_EP93XX_GRAPHICS 31 #define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc #define IRQ_EP93XX_EXT0 32 diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/memory.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/memory.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/memory.h 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/memory.h 2007-07-12 14:20:47.000000000 -0500 @@ -5,7 +5,9 @@ #ifndef __ASM_ARCH_MEMORY_H #define __ASM_ARCH_MEMORY_H +#ifndef CONFIG_RUNTIME_PHYS_OFFSET #define PHYS_OFFSET UL(0x00000000) +#endif #define __bus_to_virt(x) __phys_to_virt(x) #define __virt_to_bus(x) __virt_to_phys(x) diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/regs_raster.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/regs_raster.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/regs_raster.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/regs_raster.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,347 @@ +/*============================================================================= + * + * FILE: regs_raster.h + * + * DESCRIPTION: ep93xx Raster Engine Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + *============================================================================= + */ +#ifndef _REGS_RASTER_H_ +#define _REGS_RASTER_H_ + +//----------------------------------------------------------------------------- +// VLINESTOTAL Register Definitions +//----------------------------------------------------------------------------- +#define VLINESTOTAL_MASK 0x000007ff + +//----------------------------------------------------------------------------- +// VSYNCSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VSYNCSTRTSTOP_STRT_MASK 0x07ff0000 +#define VSYNCSTRTSTOP_STRT_SHIFT 0 +#define VSYNCSTRTSTOP_STOP_MASK 0x000007ff +#define VSYNCSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// VACTIVESTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VACTIVESTRTSTOP_STRT_MASK 0x07ff0000 +#define VACTIVESTRTSTOP_STRT_SHIFT 0 +#define VACTIVESTRTSTOP_STOP_MASK 0x000007ff +#define VACTIVESTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// VCLKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VCLKSTRTSTOP_STRT_MASK 0x07ff0000 +#define VCLKSTRTSTOP_STRT_SHIFT 0 +#define VCLKSTRTSTOP_STOP_MASK 0x000007ff +#define VCLKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// VBLANKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define VBLANKSTRTSTOP_STRT_MASK 0x07ff0000 +#define VBLANKSTRTSTOP_STRT_SHIFT 0 +#define VBLANKSTRTSTOP_STOP_MASK 0x000007ff +#define VBLANKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// HSYNCSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HSYNCSTRTSTOP_STRT_MASK 0x07ff0000 +#define HSYNCSTRTSTOP_STRT_SHIFT 0 +#define HSYNCSTRTSTOP_STOP_MASK 0x000007ff +#define HSYNCSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// HACTIVESTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HACTIVESTRTSTOP_STRT_MASK 0x07ff0000 +#define HACTIVESTRTSTOP_STRT_SHIFT 0 +#define HACTIVESTRTSTOP_STOP_MASK 0x000007ff +#define HACTIVESTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// HCLKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HCLKSTRTSTOP_STRT_MASK 0x07ff0000 +#define HCLKSTRTSTOP_STRT_SHIFT 0 +#define HCLKSTRTSTOP_STOP_MASK 0x000007ff +#define HCLKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// BRIGHTNESS Register Definitions +//----------------------------------------------------------------------------- +#define BRIGHTNESS_MASK 0x0000ffff +#define BRIGHTNESS_CNT_MASK 0x000000ff +#define BRIGHTNESS_CNT_SHIFT 0 +#define BRIGHTNESS_CMP_MASK 0x0000ff00 +#define BRIGHTNESS_CMP_SHIFT 8 + +//----------------------------------------------------------------------------- +// VIDEOATTRIBS Register Definitions +//----------------------------------------------------------------------------- +#define VIDEOATTRIBS_MASK 0x001fffff +#define VIDEOATTRIBS_EN 0x00000001 +#define VIDEOATTRIBS_PCLKEN 0x00000002 +#define VIDEOATTRIBS_SYNCEN 0x00000004 +#define VIDEOATTRIBS_DATAEN 0x00000008 +#define VIDEOATTRIBS_CSYNC 0x00000010 +#define VIDEOATTRIBS_VCPOL 0x00000020 +#define VIDEOATTRIBS_HSPOL 0x00000040 +#define VIDEOATTRIBS_BLKPOL 0x00000080 +#define VIDEOATTRIBS_INVCLK 0x00000100 +#define VIDEOATTRIBS_ACEN 0x00000200 +#define VIDEOATTRIBS_LCDEN 0x00000400 +#define VIDEOATTRIBS_CCIREN 0x00001000 +#define VIDEOATTRIBS_PIFEN 0x00002000 +#define VIDEOATTRIBS_INTEN 0x00004000 +#define VIDEOATTRIBS_INT 0x00008000 +#define VIDEOATTRIBS_INTRLC 0x00010000 +#define VIDEOATTRIBS_EQUSER 0x00020000 +#define VIDEOATTRIBS_DHORZ 0x00040000 +#define VIDEOATTRIBS_DVERT 0x00080000 +#define VIDEOATTRIBS_BKPXD 0x00100000 + +#define VIDEOATTRIBS_SDSEL_MASK 0x00600000 +#define VIDEOATTRIBS_SDSEL_SHIFT 21 + +//----------------------------------------------------------------------------- +// HBLANKSTRTSTOP Register Definitions +//----------------------------------------------------------------------------- +#define HBLANKSTRTSTOP_STRT_MASK 0x07ff0000 +#define HBLANKSTRTSTOP_STRT_SHIFT 0 +#define HBLANKSTRTSTOP_STOP_MASK 0x000007ff +#define HBLANKSTRTSTOP_STOP_SHIFT 16 + +//----------------------------------------------------------------------------- +// LINECARRY Register Definitions +//----------------------------------------------------------------------------- +#define LINECARRY_LCARY_MASK 0x000007ff +#define LINECARRY_LCARY_SHIFT 0 + +//----------------------------------------------------------------------------- +// BLINKRATE Register Definitons +//----------------------------------------------------------------------------- +#define BLINKRATE_MASK 0x000000ff + +//----------------------------------------------------------------------------- +// BLINKMASK Register Definitons +//----------------------------------------------------------------------------- +#define BLINKMASK_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// VIDSCRNPAGE Register Definitons +//----------------------------------------------------------------------------- +#define VIDSCRNPAGE_PAGE_MASK 0x0ffffffc + +//----------------------------------------------------------------------------- +// VIDSCRNHPG Register Definitons +//----------------------------------------------------------------------------- +#define VIDSCRNHPG_MASK 0x0ffffffc + +//----------------------------------------------------------------------------- +// SCRNLINES Register Definitons +//----------------------------------------------------------------------------- +#define SCRNLINES_MASK 0x000007ff + +//----------------------------------------------------------------------------- +// LINELENGTH Register Definitons +//----------------------------------------------------------------------------- +#define LINELENGTH_MASK 0x000007ff + +//----------------------------------------------------------------------------- +// VLINESTEP Register Definitons +//----------------------------------------------------------------------------- +#define VLINESTEP_MASK 0x00000fff + +//----------------------------------------------------------------------------- +// RASTER_SWLOCK Register Definitons +//----------------------------------------------------------------------------- +#define RASTER_SWLOCK_MASK_WR 0xff +#define RASTER_SWLOCK_MASK_R 0x1 +#define RASTER_SWLOCK_VALUE 0xaa + +//----------------------------------------------------------------------------- +// LUTCONT Register Definitions +//----------------------------------------------------------------------------- +#define LUTCONT_MASK 0x00000003 +#define LUTCONT_SWTCH 0x00000001 +#define LUTCONT_STAT 0x00000002 +#define LUTCONT_RAM0 0 +#define LUTCONT_RAM1 1 + +//----------------------------------------------------------------------------- +// CURSORBLINK1 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORBLINK1_MASK 0x00ffffff +//----------------------------------------------------------------------------- +// CURSORBLINK2 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORBLINK2_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// CURSORBLINK Register Definitions +//----------------------------------------------------------------------------- +#define CURSORBLINK_MASK 0x000001ff +#define CURSORBLINK_RATE_MASK 0x000000ff +#define CURSORBLINK_RATE_SHIFT 0 +#define CURSORBLINK_EN 0x00000100 + +//----------------------------------------------------------------------------- +// BLINKPATRN Register Definitions +//----------------------------------------------------------------------------- +#define BLINKPATRN_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// PATRNMASK Register Definitions +//----------------------------------------------------------------------------- +#define PATRNMASK_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// BG_OFFSET Register Definitions +//----------------------------------------------------------------------------- +#define BG_OFFSET_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// PIXELMODE Register Definitions +//----------------------------------------------------------------------------- +#define PIXELMODE_P_MASK 0x00000007 +#define PIXELMODE_P_MUX_DISABLE 0x00000000 +#define PIXELMODE_P_4BPP 0x00000001 +#define PIXELMODE_P_8BPP 0x00000002 +#define PIXELMODE_P_16BPP 0x00000004 +#define PIXELMODE_P_24BPP 0x00000006 +#define PIXELMODE_P_32BPP 0x00000007 + +#define PIXELMODE_S_MASK 0x00000038 +#define PIXELMODE_S_1PPC 0x00000000 +#define PIXELMODE_S_1PPCMAPPED 0x00000008 +#define PIXELMODE_S_2PPC 0x00000010 +#define PIXELMODE_S_4PPC 0x00000018 +#define PIXELMODE_S_8PPC 0x00000020 +#define PIXELMODE_S_223PPC 0x00000028 +#define PIXELMODE_S_DS223PPC 0x00000030 +#define PIXELMODE_S_UNDEF 0x00000038 + +#define PIXELMODE_M_MASK 0x000003c0 +#define PIXELMODE_M_NOBLINK 0x00000000 +#define PIXELMODE_M_ANDBLINK 0x00000040 +#define PIXELMODE_M_ORBLINK 0x00000080 +#define PIXELMODE_M_XORBLINK 0x000000c0 +#define PIXELMODE_M_BGBLINK 0x00000100 +#define PIXELMODE_M_OFFSINGBLINK 0x00000140 +#define PIXELMODE_M_OFF888BLINK 0x00000180 +#define PIXELMODE_M_DIMBLINK 0x00000300 +#define PIXELMODE_M_BRTBLINK 0x00000340 +#define PIXELMODE_M_DIM888BLINK 0x00000380 +#define PIXELMODE_M_BRT888BLINK 0x000003c0 + +#define PIXELMODE_C_MASK 0x00003c00 +#define PIXELMODE_C_LUT 0x00000000 +#define PIXELMODE_C_888 0x00001000 +#define PIXELMODE_C_565 0x00001400 +#define PIXELMODE_C_555 0x00001800 +#define PIXELMODE_C_GSLUT 0x00002000 + +#define PIXELMODE_DSCAN 0x00004000 +#define PIXELMODE_TRBSW 0x00008000 + +//----------------------------------------------------------------------------- +//PARLLIFOUT Register Defintions +//----------------------------------------------------------------------------- +#define PARLLIFOUT_DAT_MASK 0x0000000f +#define PARLLIFOUT_DAT_SHIFT 0 +#define PARLLIFOUT_RD 0x00000010 + +//----------------------------------------------------------------------------- +//PARLLIFIN Register Defintions +//----------------------------------------------------------------------------- +#define PARLLIFIN_DAT_MASK 0x0000000f +#define PARLLIFIN_DAT_SHIFT 0 +#define PARLLIFIN_CNT_MASK 0x000f0000 +#define PARLLIFIN_CNT_SHIFT 16 +#define PARLLIFIN_ESTRT_MASK 0x00f00000 +#define PARLLIFIN_ESTRT_SHIFT 20 + +//----------------------------------------------------------------------------- +// CURSORADRSTART Register Defintions +//----------------------------------------------------------------------------- +#define CURSOR_ADR_START_MASK 0xfffffffc + +//----------------------------------------------------------------------------- +// CURSORADRSTART Register Defintions +//----------------------------------------------------------------------------- +#define CURSOR_ADR_RESET_MASK 0xfffffffc + +//----------------------------------------------------------------------------- +// CURSORCOLOR1 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORCOLOR1_MASK 0x00ffffff +//----------------------------------------------------------------------------- +// CURSORCOLOR2 Register Definitions +//----------------------------------------------------------------------------- +#define CURSORCOLOR2_MASK 0x00ffffff + +//----------------------------------------------------------------------------- +// CURSORXYLOC Register Definitions +//----------------------------------------------------------------------------- +#define CURSORXYLOC_MASK 0x07ff87ff +#define CURSORXYLOC_XLOC_MASK 0x000007ff +#define CURSORXYLOC_XLOC_SHIFT 0 +#define CURSORXYLOC_CEN 0x00008000 +#define CURSORXYLOC_YLOC_MASK 0x07ff0000 +#define CURSORXYLOC_YLOC_SHIFT 16 + +//----------------------------------------------------------------------------- +// CURSOR_DSCAN_LH_YLOC Register Definitions +//----------------------------------------------------------------------------- +#define CURSOR_DSCAN_LH_YLOC_MASK 0x000087ff + +#define CURSOR_DSCAN_LH_YLOC_YLOC_MASK 0x000007ff +#define CURSOR_DSCAN_LH_YLOC_YLOC_SHIFT 0 +#define CURSOR_DSCAN_LH_YLOC_CLHEN 0x00008000 + +//----------------------------------------------------------------------------- +// CURSORSIZE Register Definitions +//----------------------------------------------------------------------------- +#define CURSORSIZE_MASK 0x0000ffff + +#define CURSORSIZE_CWID_MASK 0x00000003 +#define CURSORSIZE_CWID_SHIFT 0 +#define CURSORSIZE_CWID_1_WORD 0 +#define CURSORSIZE_CWID_2_WORD 1 +#define CURSORSIZE_CWID_3_WORD 2 +#define CURSORSIZE_CWID_4_WORD 3 + +#define CURSORSIZE_CLINS_MASK 0x000000fc +#define CURSORSIZE_CLINS_SHIFT 2 + +#define CURSORSIZE_CSTEP_MASK 0x00000300 +#define CURSORSIZE_CSTEP_SHIFT 8 +#define CURSORSIZE_CSTEP_1_WORD 0 +#define CURSORSIZE_CSTEP_2_WORD 1 +#define CURSORSIZE_CSTEP_3_WORD 2 +#define CURSORSIZE_CSTEP_4_WORD 3 + +#define CURSORSIZE_DLNS_MASK 0x0000fc00 +#define CURSORSIZE_DLNS_SHIFT 10 + +#endif /* _REGS_RASTER_H_ */ diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/regs_syscon.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/regs_syscon.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/regs_syscon.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/regs_syscon.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,284 @@ +/*============================================================================= + * + * FILE: reg_syscon.h + * + * DESCRIPTION: ep93xx Syscon Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + *============================================================================= + */ +#ifndef _REGS_SYSCON_H_ +#define _REGS_SYSCON_H_ + +//============================================================================= +#ifndef __ASSEMBLY__ + +#define SysconSetLocked(registername,value) \ + { \ + outl( 0xAA, EP93XX_SYSCON_SWLOCK); \ + outl( value, registername); \ + } + +#endif /* Not __ASSEMBLY__ */ +//============================================================================= + +//----------------------------------------------------------------------------- +// SYSCON_CLKSET1 +//----------------------------------------------------------------------------- +#define SYSCON_CLKSET1_PLL1_X2IPD_SHIFT 0 +#define SYSCON_CLKSET1_PLL1_X2IPD_MASK 0x0000001f +#define SYSCON_CLKSET1_PLL1_X2FBD2_SHIFT 5 +#define SYSCON_CLKSET1_PLL1_X2FBD2_MASK 0x000007e0 +#define SYSCON_CLKSET1_PLL1_X1FBD1_SHIFT 11 +#define SYSCON_CLKSET1_PLL1_X1FBD1_MASK 0x0000f800 +#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16 +#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000 +#define SYSCON_CLKSET1_PCLKDIV_SHIFT 18 +#define SYSCON_CLKSET1_PCLKDIV_MASK 0x000c0000 +#define SYSCON_CLKSET1_HCLKDIV_SHIFT 20 +#define SYSCON_CLKSET1_HCLKDIV_MASK 0x00700000 +#define SYSCON_CLKSET1_nBYP1 0x00800000 +#define SYSCON_CLKSET1_SMCROM 0x01000000 +#define SYSCON_CLKSET1_FCLKDIV_SHIFT 25 +#define SYSCON_CLKSET1_FCLKDIV_MASK 0x0e000000 + +#define SYSCON_CLKSET1_HSEL 0x00000001 +#define SYSCON_CLKSET1_PLL1_EXCLKSEL 0x00000002 + +#define SYSCON_CLKSET1_PLL1_P_MASK 0x0000007C +#define SYSCON_CLKSET1_PLL1_P_SHIFT 2 + +#define SYSCON_CLKSET1_PLL1_M1_MASK 0x00000780 +#define SYSCON_CLKSET1_PLL1_M1_SHIFT 7 +#define SYSCON_CLKSET1_PLL1_M2_MASK 0x0000F800 +#define SYSCON_CLKSET1_PLL1_M2_SHIFT 11 +#define SYSCON_CLKSET1_PLL1_PS_MASK 0x00030000 +#define SYSCON_CLKSET1_PLL1_PS_SHIFT 16 +#define SYSCON_CLKSET1_PCLK_DIV_MASK 0x000C0000 +#define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18 +#define SYSCON_CLKSET1_HCLK_DIV_MASK 0x00700000 +#define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20 +#define SYSCON_CLKSET1_SMCROM 0x01000000 +#define SYSCON_CLKSET1_FCLK_DIV_MASK 0x0E000000 +#define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25 + +#define SYSCON_CLKSET2_PLL2_EN 0x00000001 +#define SYSCON_CLKSET2_PLL2EXCLKSEL 0x00000002 +#define SYSCON_CLKSET2_PLL2_P_MASK 0x0000007C +#define SYSCON_CLKSET2_PLL2_P_SHIFT 2 +#define SYSCON_CLKSET2_PLL2_M2_MASK 0x00000F80 +#define SYSCON_CLKSET2_PLL2_M2_SHIFT 7 +#define SYSCON_CLKSET2_PLL2_M1_MASK 0x0001F000 +#define SYSCON_CLKSET2_PLL2_M1 12 +#define SYSCON_CLKSET2_PLL2_PS_MASK 0x000C0000 +#define SYSCON_CLKSET2_PLL2_PS_SHIFT 18 +#define SYSCON_CLKSET2_USBDIV_MASK 0xF0000000 +#define SYSCON_CLKSET2_USBDIV_SHIFT 28 + +//----------------------------------------------------------------------------- +// DEV_CFG Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_DEVCFG_SHena 0x00000001 +#define SYSCON_DEVCFG_KEYS 0x00000002 +#define SYSCON_DEVCFG_ADCPD 0x00000004 +#define SYSCON_DEVCFG_RAS 0x00000008 +#define SYSCON_DEVCFG_RASonP3 0x00000010 +#define SYSCON_DEVCFG_TTIC 0x00000020 +#define SYSCON_DEVCFG_I2SonAC97 0x00000040 +#define SYSCON_DEVCFG_I2SonSSP 0x00000080 +#define SYSCON_DEVCFG_EonIDE 0x00000100 +#define SYSCON_DEVCFG_PonG 0x00000200 +#define SYSCON_DEVCFG_GonIDE 0x00000400 +#define SYSCON_DEVCFG_HonIDE 0x00000800 +#define SYSCON_DEVCFG_HC1CEN 0x00001000 +#define SYSCON_DEVCFG_HC1IN 0x00002000 +#define SYSCON_DEVCFG_HC3CEN 0x00004000 +#define SYSCON_DEVCFG_HC3IN 0x00008000 +#define SYSCON_DEVCFG_TIN 0x00020000 +#define SYSCON_DEVCFG_U1EN 0x00040000 +#define SYSCON_DEVCFG_EXVC 0x00080000 +#define SYSCON_DEVCFG_U2EN 0x00100000 +#define SYSCON_DEVCFG_A1onG 0x00200000 +#define SYSCON_DEVCFG_A2onG 0x00400000 +#define SYSCON_DEVCFG_CPENA 0x00800000 +#define SYSCON_DEVCFG_U3EN 0x01000000 +#define SYSCON_DEVCFG_MonG 0x02000000 +#define SYSCON_DEVCFG_TonG 0x04000000 +#define SYSCON_DEVCFG_GonK 0x08000000 +#define SYSCON_DEVCFG_IonU2 0x10000000 +#define SYSCON_DEVCFG_D0onG 0x20000000 +#define SYSCON_DEVCFG_D1onG 0x40000000 +#define SYSCON_DEVCFG_SWRST 0x80000000 + +//----------------------------------------------------------------------------- +// VIDDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_VIDDIV_VDIV_MASK 0x0000007f +#define SYSCON_VIDDIV_VDIV_SHIFT 0 +#define SYSCON_VIDDIV_PDIV_MASK 0x00000300 +#define SYSCON_VIDDIV_PDIV_SHIFT 8 +#define SYSCON_VIDDIV_PSEL 0x00002000 +#define SYSCON_VIDDIV_ESEL 0x00004000 +#define SYSCON_VIDDIV_VENA 0x00008000 + +//----------------------------------------------------------------------------- +// MIRDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_MIRDIV_MDIV_MASK 0x0000003f +#define SYSCON_MIRDIV_MDIV_SHIFT 0 +#define SYSCON_MIRDIV_PDIV_MASK 0x00000300 +#define SYSCON_MIRDIV_PDIV_SHIFT 8 +#define SYSCON_MIRDIV_PSEL 0x00002000 +#define SYSCON_MIRDIV_ESEL 0x00004000 +#define SYSCON_MIRDIV_MENA 0x00008000 + +//----------------------------------------------------------------------------- +// I2SDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_I2SDIV_MDIV_MASK 0x0000007f +#define SYSCON_I2SDIV_MDIV_SHIFT 0 +#define SYSCON_I2SDIV_PDIV_MASK 0x00000300 +#define SYSCON_I2SDIV_PDIV_SHIFT 8 +#define SYSCON_I2SDIV_PSEL 0x00002000 +#define SYSCON_I2SDIV_ESEL 0x00004000 +#define SYSCON_I2SDIV_MENA 0x00008000 +#define SYSCON_I2SDIV_SDIV 0x00010000 +#define SYSCON_I2SDIV_LRDIV_MASK 0x00060000 +#define SYSCON_I2SDIV_LRDIV_SHIFT 17 +#define SYSCON_I2SDIV_SPOL 0x00080000 +#define SYSCON_I2SDIV_DROP 0x00100000 +#define SYSCON_I2SDIV_ORIDE 0x20000000 +#define SYSCON_I2SDIV_SLAVE 0x40000000 +#define SYSCON_I2SDIV_SENA 0x80000000 + +#define SYSCON_I2SDIV_PDIV_OFF 0x00000000 +#define SYSCON_I2SDIV_PDIV_2 0x00000100 +#define SYSCON_I2SDIV_PDIV_25 0x00000200 +#define SYSCON_I2SDIV_PDIV_3 0x00000300 + +#define SYSCON_I2SDIV_LRDIV_32 0x00000000 +#define SYSCON_I2SDIV_LRDIV_64 0x00020000 +#define SYSCON_I2SDIV_LRDIV_128 0x00040000 + +//----------------------------------------------------------------------------- +// KTDIV Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_KTDIV_KDIV 0x00000001 +#define SYSCON_KTDIV_KEN 0x00008000 +#define SYSCON_KTDIV_ADIV 0x00010000 +#define SYSCON_KTDIV_TSEN 0x80000000 + +//----------------------------------------------------------------------------- +// CHIPID Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_CHIPID_ID_MASK 0x0000ffff +#define SYSCON_CHIPID_ID_SHIFT 0 +#define SYSCON_CHIPID_PKID 0x00010000 +#define SYSCON_CHIPID_BND 0x00040000 +#define SYSCON_CHIPID_FAB_MASK 0x0e000000 +#define SYSCON_CHIPID_FAB_SHIFT 25 +#define SYSCON_CHIPID_REV_MASK 0xf0000000 +#define SYSCON_CHIPID_REV_SHIFT 28 + +//----------------------------------------------------------------------------- +// TESTCR Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_TESTCR_TMODE_MASK 0x000000ff +#define SYSCON_TESTCR_TMODE_SHIFT 0 +#define SYSCON_TESTCR_BONDO 0x00000100 +#define SYSCON_TESTCR_PACKO 0x00000800 +#define SYSCON_TESTCR_ETOM 0x00002000 +#define SYSCON_TESTCR_TOM 0x00004000 +#define SYSCON_TESTCR_OVR 0x00008000 +#define SYSCON_TESTCR_TonIDE 0x00010000 +#define SYSCON_TESTCR_RonG 0x00020000 + +//----------------------------------------------------------------------------- +// SYSCFG Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_SYSCFG_LCSn1 0x00000001 +#define SYSCON_SYSCFG_LCSn2 0x00000002 +#define SYSCON_SYSCFG_LCSn3 0x00000004 +#define SYSCON_SYSCFG_LEECK 0x00000008 +#define SYSCON_SYSCFG_LEEDA 0x00000010 +#define SYSCON_SYSCFG_LASDO 0x00000020 +#define SYSCON_SYSCFG_LCSn6 0x00000040 +#define SYSCON_SYSCFG_LCSn7 0x00000080 +#define SYSCON_SYSCFG_SBOOT 0x00000100 +#define SYSCON_SYSCFG_FAB_MASK 0x0e000000 +#define SYSCON_SYSCFG_FAB_SHIFT 25 +#define SYSCON_SYSCFG_REV_MASK 0xf0000000 +#define SYSCON_SYSCFG_REV_SHIFT 28 + + +//----------------------------------------------------------------------------- +// PWRSR Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_PWRSR_CHIPMAN_MASK 0xFF000000 +#define SYSCON_PWRSR_CHIPMAN_SHIFT 24 +#define SYSCON_PWRSR_CHIPID_MASK 0x00FF0000 +#define SYSCON_PWRSR_CHIPID_SHIFT 16 +#define SYSCON_PWRSR_WDTFLG 0x00008000 +#define SYSCON_PWRSR_CLDFLG 0x00002000 +#define SYSCON_PWRSR_TEST_RESET 0x00001000 +#define SYSCON_PWRSR_RSTFLG 0x00000800 +#define SYSCON_PWRSR_SWRESET 0x00000400 +#define SYSCON_PWRSR_PLL2_LOCKREG 0x00000200 +#define SYSCON_PWRSR_PLL2_LOCK 0x00000100 +#define SYSCON_PWRSR_PLL1_LOCKREG 0x00000080 +#define SYSCON_PWRSR_PLL1_LOCK 0x00000040 +#define SYSCON_PWRSR_RTCDIV 0x0000003F + +//----------------------------------------------------------------------------- +// PWRCNT Register Defines +//----------------------------------------------------------------------------- +#define SYSCON_PWRCNT_FIREN 0x80000000 +#define SYSCON_PWRCNT_UARTBAUD 0x20000000 +#define SYSCON_PWRCNT_USHEN 0x10000000 +#define SYSCON_PWRCNT_DMA_M2MCH1 0x08000000 +#define SYSCON_PWRCNT_DMA_M2MCH0 0x04000000 +#define SYSCON_PWRCNT_DMA_M2PCH8 0x02000000 +#define SYSCON_PWRCNT_DMA_M2PCH9 0x01000000 +#define SYSCON_PWRCNT_DMA_M2PCH6 0x00800000 +#define SYSCON_PWRCNT_DMA_M2PCH7 0x00400000 +#define SYSCON_PWRCNT_DMA_M2PCH4 0x00200000 +#define SYSCON_PWRCNT_DMA_M2PCH5 0x00100000 +#define SYSCON_PWRCNT_DMA_M2PCH2 0x00080000 +#define SYSCON_PWRCNT_DMA_M2PCH3 0x00040000 +#define SYSCON_PWRCNT_DMA_M2PCH0 0x00020000 +#define SYSCON_PWRCNT_DMA_M2PCH1 0x00010000 + +//----------------------------------------------------------------------------- +// BMAR Register Defines +//----------------------------------------------------------------------------- +#define BMAR_PRIORD_00 0x00000000 +#define BMAR_PRIORD_01 0x00000001 +#define BMAR_PRIORD_02 0x00000002 +#define BMAR_PRIORD_03 0x00000003 +#define BMAR_PRI_CORE 0x00000008 +#define BMAR_DMA_ENIRQ 0x00000010 +#define BMAR_DMA_ENFIQ 0x00000020 +#define BMAR_USB_ENIRQ 0x00000040 +#define BMAR_USB_ENFIQ 0x00000080 +#define BMAR_MAC_ENIRQ 0x00000100 +#define BMAR_MAC_ENFIQ 0x00000200 +#define BMAR_GRAPHICS_ENIRQ 0x00000400 +#define BMAR_GRAPHICS_ENFIQ 0x00000800 + + +#endif // _REGS_SYSCON_H_ diff -urN -x CVS linux-2.6.20/include/asm-arm/arch-ep93xx/regs_touch.h linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/regs_touch.h --- linux-2.6.20/include/asm-arm/arch-ep93xx/regs_touch.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/arch-ep93xx/regs_touch.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,95 @@ +/*============================================================================= + * + * FILE: regs_touch.h + * + * DESCRIPTION: Analog Touchscreen Register Definition + * + * Copyright Cirrus Logic, 2001-2003 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + *============================================================================= + */ +#ifndef _REGS_TOUCH_H_ +#define _REGS_TOUCH_H_ + +/* + *----------------------------------------------------------------------------- + * Individual bit #defines + *----------------------------------------------------------------------------- + */ +#define TSSETUP_SDLY_MASK 0x000003FF +#define TSSETUP_SDLY_SHIFT 0 +#define TSSETUP_NSMP_4 0x00000000 +#define TSSETUP_NSMP_8 0x00000400 +#define TSSETUP_NSMP_16 0x00000800 +#define TSSETUP_NSMP_32 0x00000C00 +#define TSSETUP_NSMP_MASK 0x00000C00 +#define TSSETUP_DEV_4 0x00000000 +#define TSSETUP_DEV_8 0x00001000 +#define TSSETUP_DEV_12 0x00002000 +#define TSSETUP_DEV_16 0x00003000 +#define TSSETUP_DEV_24 0x00004000 +#define TSSETUP_DEV_32 0x00005000 +#define TSSETUP_DEV_64 0x00006000 +#define TSSETUP_DEV_128 0x00007000 +#define TSSETUP_ENABLE 0x00008000 +#define TSSETUP_DLY_MASK 0x03FF0000 +#define TSSETUP_DLY_SHIFT 16 +#define TSSETUP_TDTCT 0x80000000 + +#define TSMAXMIN_XMIN_MASK 0x000000FF +#define TSMAXMIN_XMIN_SHIFT 0 +#define TSMAXMIN_YMIN_MASK 0x0000FF00 +#define TSMAXMIN_YMIN_SHIFT 8 +#define TSMAXMIN_XMAX_MASK 0x00FF0000 +#define TSMAXMIN_XMAX_SHIFT 16 +#define TSMAXMIN_YMAX_MASK 0xFF000000 +#define TSMAXMIN_YMAX_SHIFT 24 + +#define TSXYRESULT_X_MASK 0x00000FFF +#define TSXYRESULT_X_SHIFT 0 +#define TSXYRESULT_AD_MASK 0x0000FFFF +#define TSXYRESULT_AD_SHIFT 0 +#define TSXYRESULT_Y_MASK 0x0FFF0000 +#define TSXYRESULT_Y_SHIFT 16 +#define TSXYRESULT_SDR 0x80000000 + +#define TSX_SAMPLE_MASK 0x00003FFF +#define TSX_SAMPLE_SHIFT 0x00 +#define TSY_SAMPLE_MASK 0x3FFF0000 +#define TSY_SAMPLE_SHIFT 0x10 + +#define TSSETUP2_TINT 0x00000001 +#define TSSETUP2_NICOR 0x00000002 +#define TSSETUP2_PINT 0x00000004 +#define TSSETUP2_PENSTS 0x00000008 +#define TSSETUP2_PINTEN 0x00000010 +#define TSSETUP2_DEVINT 0x00000020 +#define TSSETUP2_DINTEN 0x00000040 +#define TSSETUP2_DTMEN 0x00000080 +#define TSSETUP2_DISDEV 0x00000100 +#define TSSETUP2_NSIGND 0x00000200 +#define TSSETUP2_S28EN 0x00000400 +#define TSSETUP2_RINTEN 0x00000800 + +#define TSXYRESULT_SDR 0x80000000 + +/* + *----------------------------------------------------------------------------- + *----------------------------------------------------------------------------- + */ + + +#endif /* _REGS_TOUCH_H_ */ diff -urN -x CVS linux-2.6.20/include/asm-arm/memory.h linux-2.6.20-AT91/include/asm-arm/memory.h --- linux-2.6.20/include/asm-arm/memory.h 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/include/asm-arm/memory.h 2007-07-12 14:20:47.000000000 -0500 @@ -73,6 +73,14 @@ */ #define IOREMAP_MAX_ORDER 24 +/* + * PHYS_OFFSET determined at run time? + */ +#if defined(CONFIG_RUNTIME_PHYS_OFFSET) && !defined(__ASSEMBLY__) +extern unsigned long phys_offset; +#define PHYS_OFFSET (phys_offset) +#endif + #else /* CONFIG_MMU */ /* diff -urN -x CVS linux-2.6.20/include/linux/chelper.h linux-2.6.20-AT91/include/linux/chelper.h --- linux-2.6.20/include/linux/chelper.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/linux/chelper.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,36 @@ +#ifndef CHELPER_H_ +#define CHELPER_H_ + +#include + +/************************************************************ + * helper functions + */ + + static inline ssize_t sfs_getint(const char *buf,size_t count,size_t *size){ + char *endp; + u32 data = simple_strtoul(buf,&endp,0); + *size = (size_t)(endp - buf); + if (*endp && isspace(*endp))(*size)++; + if (*size != count)*size = -EINVAL; + return data; + } + + +static inline ssize_t store8(const char *buf,size_t count,void *address,u8 *shadow){ + size_t size; + u8 data = sfs_getint(buf,count,&size); + if(address)iowrite8(data,address); + if(shadow)*shadow=data; + return size; +} + +static inline ssize_t store16(const char *buf,size_t count,void *address,u16 *shadow){ + size_t size; + u16 data = sfs_getint(buf,count,&size); + if(address)iowrite16(data,address); + if(shadow)*shadow=data; + return size; +} + +#endif /*CHELPER_H_*/ diff -urN -x CVS linux-2.6.20/include/linux/class/gpio.h linux-2.6.20-AT91/include/linux/class/gpio.h --- linux-2.6.20/include/linux/class/gpio.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/linux/class/gpio.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,14 @@ +#ifndef GPIO_H_ +#define GPIO_H_ + +#include +#include + +#ifdef CONFIG_GPIOCLASS +struct class *gpio_declare(void); +struct class_device *gpio_device_create(void *data, void *ddr,const char *name); +struct class_device *gpo_device_create(void *data,const char *name); +struct class_device *gpi_device_create(void *data,const char *name); +#endif + +#endif /*GPIO_H_*/ diff -urN -x CVS linux-2.6.20/include/linux/class/pwm.h linux-2.6.20-AT91/include/linux/class/pwm.h --- linux-2.6.20/include/linux/class/pwm.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/linux/class/pwm.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,16 @@ +#ifndef PWM_H_ +#define PWM_H_ +#include +#include + +#ifdef CONFIG_PWMCLASS +struct class *pwm_declare(void); +struct class_device *pwmd_device_create(void *duty, const char *name); + +#ifdef CONFIG_EP93XX_PWM +struct class_device *ep93xx_pwm_device_create(unsigned long base, const char *name); +#endif //CONFIG_EP93XX_PWM + +#endif //CONFIG_PWMCLASS + +#endif /*PWM_H_*/ diff -urN -x CVS linux-2.6.20/include/linux/ioex/ecoreex.h linux-2.6.20-AT91/include/linux/ioex/ecoreex.h --- linux-2.6.20/include/linux/ioex/ecoreex.h 1969-12-31 18:00:00.000000000 -0600 +++ linux-2.6.20-AT91/include/linux/ioex/ecoreex.h 2007-07-12 14:20:47.000000000 -0500 @@ -0,0 +1,9 @@ +#ifndef ECOREEX_H_ +#define ECOREEX_H_ + +struct ecoreex_data +{ + int key_offset; +}; + +#endif /*ECOREEX_H_*/ diff -urN -x CVS linux-2.6.20/init/main.c linux-2.6.20-AT91/init/main.c --- linux-2.6.20/init/main.c 2007-02-04 12:44:54.000000000 -0600 +++ linux-2.6.20-AT91/init/main.c 2007-07-12 14:20:45.000000000 -0500 @@ -713,6 +713,9 @@ kernel_execve(init_filename, argv_init, envp_init); } +/* Addition for Cirrus ep93xx frame buffer driver */ +int pls_proba = 0; + static int init(void * unused) { lock_kernel(); @@ -790,6 +793,7 @@ printk(KERN_WARNING "Failed to execute %s. Attempting " "defaults...\n", execute_command); } + pls_proba = 1; /* Cirrus frame buffer driver */ run_init_process("/sbin/init"); run_init_process("/etc/init"); run_init_process("/bin/init"); @@ -797,3 +801,6 @@ panic("No init found. Try passing init= option to kernel."); } +/* Once again, dirty dirty Cirrus code */ +EXPORT_SYMBOL(pls_proba); + Binary files linux-2.6.20/scripts/kconfig/mconf and linux-2.6.20-AT91/scripts/kconfig/mconf differ